2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
33 #include "pseudo_irg.h"
38 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
55 #include "../beirg_t.h"
56 #include "../benode_t.h"
57 #include "../belower.h"
58 #include "../besched_t.h"
61 #include "../beirgmod.h"
62 #include "../be_dbgout.h"
63 #include "../beblocksched.h"
64 #include "../bemachine.h"
65 #include "../beilpsched.h"
66 #include "../bespillslots.h"
67 #include "../bemodule.h"
68 #include "../begnuas.h"
69 #include "../bestate.h"
70 #include "../beflags.h"
71 #include "../betranshlp.h"
73 #include "bearch_ia32_t.h"
75 #include "ia32_new_nodes.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "gen_ia32_machine.h"
78 #include "ia32_common_transform.h"
79 #include "ia32_transform.h"
80 #include "ia32_emitter.h"
81 #include "ia32_map_regs.h"
82 #include "ia32_optimize.h"
84 #include "ia32_dbg_stat.h"
85 #include "ia32_finish.h"
86 #include "ia32_util.h"
88 #include "ia32_architecture.h"
91 #include "ia32_pbqp_transform.h"
93 transformer_t be_transformer = TRANSFORMER_DEFAULT;
96 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
99 static set *cur_reg_set = NULL;
101 ir_mode *mode_fpcw = NULL;
102 ia32_code_gen_t *ia32_current_cg = NULL;
105 * The environment for the intrinsic mapping.
107 static ia32_intrinsic_env_t intrinsic_env = {
109 NULL, /* the irg, these entities belong to */
110 NULL, /* entity for __divdi3 library call */
111 NULL, /* entity for __moddi3 library call */
112 NULL, /* entity for __udivdi3 library call */
113 NULL, /* entity for __umoddi3 library call */
117 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
119 static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
120 create_const_node_func func,
121 const arch_register_t* reg)
123 ir_node *block, *res;
128 block = get_irg_start_block(cg->irg);
129 res = func(NULL, block);
130 arch_set_irn_register(res, reg);
133 add_irn_dep(get_irg_end(cg->irg), res);
134 /* add_irn_dep(get_irg_start(cg->irg), res); */
139 /* Creates the unique per irg GP NoReg node. */
140 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
141 return create_const(cg, &cg->noreg_gp, new_bd_ia32_NoReg_GP,
142 &ia32_gp_regs[REG_GP_NOREG]);
145 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
146 return create_const(cg, &cg->noreg_vfp, new_bd_ia32_NoReg_VFP,
147 &ia32_vfp_regs[REG_VFP_NOREG]);
150 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
151 return create_const(cg, &cg->noreg_xmm, new_bd_ia32_NoReg_XMM,
152 &ia32_xmm_regs[REG_XMM_NOREG]);
155 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
156 return create_const(cg, &cg->unknown_gp, new_bd_ia32_Unknown_GP,
157 &ia32_gp_regs[REG_GP_UKNWN]);
160 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
161 return create_const(cg, &cg->unknown_vfp, new_bd_ia32_Unknown_VFP,
162 &ia32_vfp_regs[REG_VFP_UKNWN]);
165 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
166 return create_const(cg, &cg->unknown_xmm, new_bd_ia32_Unknown_XMM,
167 &ia32_xmm_regs[REG_XMM_UKNWN]);
170 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
171 return create_const(cg, &cg->fpu_trunc_mode, new_bd_ia32_ChangeCW,
172 &ia32_fp_cw_regs[REG_FPCW]);
177 * Returns the admissible noreg register node for input register pos of node irn.
179 static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
181 const arch_register_req_t *req = arch_get_register_req(irn, pos);
183 assert(req != NULL && "Missing register requirements");
184 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
185 return ia32_new_NoReg_gp(cg);
187 if (ia32_cg_config.use_sse2) {
188 return ia32_new_NoReg_xmm(cg);
190 return ia32_new_NoReg_vfp(cg);
194 /**************************************************
197 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
198 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
199 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
200 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
203 **************************************************/
206 * Return register requirements for an ia32 node.
207 * If the node returns a tuple (mode_T) then the proj's
208 * will be asked for this information.
210 static const arch_register_req_t *ia32_get_irn_reg_req(const ir_node *node,
213 ir_mode *mode = get_irn_mode(node);
216 if (mode == mode_X || is_Block(node)) {
217 return arch_no_register_req;
220 if (mode == mode_T && pos < 0) {
221 return arch_no_register_req;
224 node_pos = pos == -1 ? 0 : pos;
226 if (mode == mode_M || pos >= 0) {
227 return arch_no_register_req;
230 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
231 node = skip_Proj_const(node);
234 if (is_ia32_irn(node)) {
235 const arch_register_req_t *req;
237 req = get_ia32_in_req(node, pos);
239 req = get_ia32_out_req(node, node_pos);
246 /* unknowns should be transformed already */
247 return arch_no_register_req;
250 static arch_irn_class_t ia32_classify(const ir_node *irn) {
251 arch_irn_class_t classification = 0;
253 irn = skip_Proj_const(irn);
256 classification |= arch_irn_class_branch;
258 if (! is_ia32_irn(irn))
259 return classification;
261 if (is_ia32_is_reload(irn))
262 classification |= arch_irn_class_reload;
264 if (is_ia32_is_spill(irn))
265 classification |= arch_irn_class_spill;
267 if (is_ia32_is_remat(irn))
268 classification |= arch_irn_class_remat;
270 return classification;
274 * The IA32 ABI callback object.
277 be_abi_call_flags_bits_t flags; /**< The call flags. */
278 const arch_env_t *aenv; /**< The architecture environment. */
279 ir_graph *irg; /**< The associated graph. */
282 static ir_entity *ia32_get_frame_entity(const ir_node *irn) {
283 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
286 static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent) {
287 set_ia32_frame_ent(irn, ent);
290 static void ia32_set_frame_offset(ir_node *irn, int bias)
292 if (get_ia32_frame_ent(irn) == NULL)
295 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
296 ia32_code_gen_t *cg = ia32_current_cg;
297 int omit_fp = be_abi_omit_fp(cg->birg->abi);
299 /* Pop nodes modify the stack pointer before calculating the
300 * destination address, so fix this here
305 add_ia32_am_offs_int(irn, bias);
308 static int ia32_get_sp_bias(const ir_node *node)
310 if (is_ia32_Call(node))
311 return -(int)get_ia32_call_attr_const(node)->pop;
313 if (is_ia32_Push(node))
316 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
323 * Generate the routine prologue.
325 * @param self The callback object.
326 * @param mem A pointer to the mem node. Update this if you define new memory.
327 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
328 * @param stack_bias Points to the current stack bias, can be modified if needed.
330 * @return The register which shall be used as a stack frame base.
332 * All nodes which define registers in @p reg_map must keep @p reg_map current.
334 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
336 ia32_abi_env_t *env = self;
337 ia32_code_gen_t *cg = ia32_current_cg;
338 const arch_env_t *arch_env = env->aenv;
340 if (! env->flags.try_omit_fp) {
341 ir_graph *irg = env->irg;
342 ir_node *bl = get_irg_start_block(irg);
343 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
344 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
345 ir_node *noreg = ia32_new_NoReg_gp(cg);
348 /* mark bp register as ignore */
349 be_set_constr_single_reg_out(get_Proj_pred(curr_bp),
350 get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore);
353 push = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
354 curr_sp = new_r_Proj(irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
355 *mem = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M);
357 /* the push must have SP out register */
358 arch_set_irn_register(curr_sp, arch_env->sp);
360 /* this modifies the stack bias, because we pushed 32bit */
363 /* move esp to ebp */
364 curr_bp = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp);
365 be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
366 arch_register_req_type_ignore);
368 /* beware: the copy must be done before any other sp use */
369 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
370 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
371 arch_register_req_type_produces_sp);
373 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
374 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
383 * Generate the routine epilogue.
384 * @param self The callback object.
385 * @param bl The block for the epilog
386 * @param mem A pointer to the mem node. Update this if you define new memory.
387 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
388 * @return The register which shall be used as a stack frame base.
390 * All nodes which define registers in @p reg_map must keep @p reg_map current.
392 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
394 ia32_abi_env_t *env = self;
395 const arch_env_t *arch_env = env->aenv;
396 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
397 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
398 ir_graph *irg = env->irg;
400 if (env->flags.try_omit_fp) {
401 /* simply remove the stack frame here */
402 curr_sp = be_new_IncSP(arch_env->sp, irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
404 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
406 if (ia32_cg_config.use_leave) {
410 leave = new_bd_ia32_Leave(NULL, bl, curr_bp);
411 curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
412 curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
416 /* the old SP is not needed anymore (kill the proj) */
417 assert(is_Proj(curr_sp));
420 /* copy ebp to esp */
421 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
422 arch_set_irn_register(curr_sp, arch_env->sp);
423 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
424 arch_register_req_type_ignore);
427 pop = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
428 curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
429 curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
431 *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
433 arch_set_irn_register(curr_sp, arch_env->sp);
434 arch_set_irn_register(curr_bp, arch_env->bp);
437 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
438 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
442 * Initialize the callback object.
443 * @param call The call object.
444 * @param aenv The architecture environment.
445 * @param irg The graph with the method.
446 * @return Some pointer. This pointer is passed to all other callback functions as self object.
448 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
450 ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
451 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
452 env->flags = fl.bits;
459 * Destroy the callback object.
460 * @param self The callback object.
462 static void ia32_abi_done(void *self) {
467 * Produces the type which sits between the stack args and the locals on the stack.
468 * it will contain the return address and space to store the old base pointer.
469 * @return The Firm type modeling the ABI between type.
471 static ir_type *ia32_abi_get_between_type(void *self)
473 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
474 static ir_type *omit_fp_between_type = NULL;
475 static ir_type *between_type = NULL;
477 ia32_abi_env_t *env = self;
479 if (! between_type) {
480 ir_entity *old_bp_ent;
481 ir_entity *ret_addr_ent;
482 ir_entity *omit_fp_ret_addr_ent;
484 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
485 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
487 between_type = new_type_struct(IDENT("ia32_between_type"));
488 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
489 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
491 set_entity_offset(old_bp_ent, 0);
492 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
493 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
494 set_type_state(between_type, layout_fixed);
496 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
497 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
499 set_entity_offset(omit_fp_ret_addr_ent, 0);
500 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
501 set_type_state(omit_fp_between_type, layout_fixed);
504 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
509 * Get the estimated cycle count for @p irn.
511 * @param self The this pointer.
512 * @param irn The node.
514 * @return The estimated cycle count for this operation
516 static int ia32_get_op_estimated_cost(const ir_node *irn)
519 ia32_op_type_t op_tp;
523 if (!is_ia32_irn(irn))
526 assert(is_ia32_irn(irn));
528 cost = get_ia32_latency(irn);
529 op_tp = get_ia32_op_type(irn);
531 if (is_ia32_CopyB(irn)) {
534 else if (is_ia32_CopyB_i(irn)) {
535 int size = get_ia32_copyb_size(irn);
536 cost = 20 + (int)ceil((4/3) * size);
538 /* in case of address mode operations add additional cycles */
539 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
541 In case of stack access and access to fixed addresses add 5 cycles
542 (we assume they are in cache), other memory operations cost 20
545 if (is_ia32_use_frame(irn) || (
546 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
547 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
559 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
561 * @param irn The original operation
562 * @param i Index of the argument we want the inverse operation to yield
563 * @param inverse struct to be filled with the resulting inverse op
564 * @param obstack The obstack to use for allocation of the returned nodes array
565 * @return The inverse operation or NULL if operation invertible
567 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
570 ir_node *block, *noreg, *nomem;
573 /* we cannot invert non-ia32 irns */
574 if (! is_ia32_irn(irn))
577 /* operand must always be a real operand (not base, index or mem) */
578 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
581 /* we don't invert address mode operations */
582 if (get_ia32_op_type(irn) != ia32_Normal)
585 /* TODO: adjust for new immediates... */
586 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
590 block = get_nodes_block(irn);
591 mode = get_irn_mode(irn);
592 irn_mode = get_irn_mode(irn);
593 noreg = get_irn_n(irn, 0);
595 dbg = get_irn_dbg_info(irn);
597 /* initialize structure */
598 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
602 switch (get_ia32_irn_opcode(irn)) {
605 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
606 /* we have an add with a const here */
607 /* invers == add with negated const */
608 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
610 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
611 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
612 set_ia32_commutative(inverse->nodes[0]);
614 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
615 /* we have an add with a symconst here */
616 /* invers == sub with const */
617 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
619 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
622 /* normal add: inverse == sub */
623 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
630 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
631 /* we have a sub with a const/symconst here */
632 /* invers == add with this const */
633 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
634 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
635 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
639 if (i == n_ia32_binary_left) {
640 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
643 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
651 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
652 /* xor with const: inverse = xor */
653 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
654 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
655 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
659 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
665 inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
670 inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
675 /* inverse operation not supported */
682 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
684 if(mode_is_float(mode))
691 * Get the mode that should be used for spilling value node
693 static ir_mode *get_spill_mode(const ir_node *node)
695 ir_mode *mode = get_irn_mode(node);
696 return get_spill_mode_mode(mode);
700 * Checks whether an addressmode reload for a node with mode mode is compatible
701 * with a spillslot of mode spill_mode
703 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
705 return !mode_is_float(mode) || mode == spillmode;
709 * Check if irn can load its operand at position i from memory (source addressmode).
710 * @param irn The irn to be checked
711 * @param i The operands position
712 * @return Non-Zero if operand can be loaded
714 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
716 ir_node *op = get_irn_n(irn, i);
717 const ir_mode *mode = get_irn_mode(op);
718 const ir_mode *spillmode = get_spill_mode(op);
720 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
721 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
722 !ia32_is_spillmode_compatible(mode, spillmode) ||
723 is_ia32_use_frame(irn)) /* must not already use frame */
726 switch (get_ia32_am_support(irn)) {
731 if (i != n_ia32_unary_op)
737 case n_ia32_binary_left: {
738 const arch_register_req_t *req;
739 if (!is_ia32_commutative(irn))
742 /* we can't swap left/right for limited registers
743 * (As this (currently) breaks constraint handling copies)
745 req = get_ia32_in_req(irn, n_ia32_binary_left);
746 if (req->type & arch_register_req_type_limited)
751 case n_ia32_binary_right:
760 panic("Unknown AM type");
763 /* HACK: must not already use "real" memory.
764 * This can happen for Call and Div */
765 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
771 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
775 ir_mode *dest_op_mode;
777 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
779 set_ia32_op_type(irn, ia32_AddrModeS);
781 load_mode = get_irn_mode(get_irn_n(irn, i));
782 dest_op_mode = get_ia32_ls_mode(irn);
783 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
784 set_ia32_ls_mode(irn, load_mode);
786 set_ia32_use_frame(irn);
787 set_ia32_need_stackent(irn);
789 if (i == n_ia32_binary_left &&
790 get_ia32_am_support(irn) == ia32_am_binary &&
791 /* immediates are only allowed on the right side */
792 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
793 ia32_swap_left_right(irn);
794 i = n_ia32_binary_right;
797 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
799 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
800 set_irn_n(irn, n_ia32_mem, spill);
801 set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i));
802 set_ia32_is_reload(irn);
805 static const be_abi_callbacks_t ia32_abi_callbacks = {
808 ia32_abi_get_between_type,
813 /* fill register allocator interface */
815 static const arch_irn_ops_t ia32_irn_ops = {
816 ia32_get_irn_reg_req,
818 ia32_get_frame_entity,
819 ia32_set_frame_entity,
820 ia32_set_frame_offset,
823 ia32_get_op_estimated_cost,
824 ia32_possible_memory_operand,
825 ia32_perform_memory_operand,
828 /**************************************************
831 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
832 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
833 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
834 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
837 **************************************************/
839 static ir_entity *mcount = NULL;
841 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
843 static void ia32_before_abi(void *self) {
844 lower_mode_b_config_t lower_mode_b_config = {
845 mode_Iu, /* lowered mode */
846 mode_Bu, /* preferred mode for set */
847 0, /* don't lower direct compares */
849 ia32_code_gen_t *cg = self;
851 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
853 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
855 if (mcount == NULL) {
856 ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
857 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
858 /* FIXME: enter the right ld_ident here */
859 set_entity_ld_ident(mcount, get_entity_ident(mcount));
860 set_entity_visibility(mcount, visibility_external_allocated);
862 instrument_initcall(cg->irg, mcount);
867 * Transforms the standard firm graph into
870 static void ia32_prepare_graph(void *self) {
871 ia32_code_gen_t *cg = self;
873 /* do local optimizations */
874 optimize_graph_df(cg->irg);
876 /* TODO: we often have dead code reachable through out-edges here. So for
877 * now we rebuild edges (as we need correct user count for code selection)
880 edges_deactivate(cg->irg);
881 edges_activate(cg->irg);
885 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
887 switch (be_transformer) {
888 case TRANSFORMER_DEFAULT:
889 /* transform remaining nodes into assembler instructions */
890 ia32_transform_graph(cg);
894 case TRANSFORMER_PBQP:
895 case TRANSFORMER_RAND:
896 /* transform nodes into assembler instructions by PBQP magic */
897 ia32_transform_graph_by_pbqp(cg);
902 panic("invalid transformer");
905 /* do local optimizations (mainly CSE) */
906 optimize_graph_df(cg->irg);
909 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
911 /* optimize address mode */
912 ia32_optimize_graph(cg);
914 /* do code placement, to optimize the position of constants */
918 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
921 ir_node *turn_back_am(ir_node *node)
923 ir_graph *irg = current_ir_graph;
924 dbg_info *dbgi = get_irn_dbg_info(node);
925 ir_node *block = get_nodes_block(node);
926 ir_node *base = get_irn_n(node, n_ia32_base);
927 ir_node *index = get_irn_n(node, n_ia32_index);
928 ir_node *mem = get_irn_n(node, n_ia32_mem);
931 ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
932 ir_node *load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
934 ia32_copy_am_attrs(load, node);
935 if (is_ia32_is_reload(node))
936 set_ia32_is_reload(load);
937 set_irn_n(node, n_ia32_mem, new_NoMem());
939 switch (get_ia32_am_support(node)) {
941 set_irn_n(node, n_ia32_unary_op, load_res);
945 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
946 set_irn_n(node, n_ia32_binary_left, load_res);
948 set_irn_n(node, n_ia32_binary_right, load_res);
953 panic("Unknown AM type");
955 noreg = ia32_new_NoReg_gp(ia32_current_cg);
956 set_irn_n(node, n_ia32_base, noreg);
957 set_irn_n(node, n_ia32_index, noreg);
958 set_ia32_am_offs_int(node, 0);
959 set_ia32_am_sc(node, NULL);
960 set_ia32_am_scale(node, 0);
961 clear_ia32_am_sc_sign(node);
963 /* rewire mem-proj */
964 if (get_irn_mode(node) == mode_T) {
965 const ir_edge_t *edge;
966 foreach_out_edge(node, edge) {
967 ir_node *out = get_edge_src_irn(edge);
968 if (get_irn_mode(out) == mode_M) {
969 set_Proj_pred(out, load);
970 set_Proj_proj(out, pn_ia32_Load_M);
976 set_ia32_op_type(node, ia32_Normal);
977 if (sched_is_scheduled(node))
978 sched_add_before(node, load);
983 static ir_node *flags_remat(ir_node *node, ir_node *after)
985 /* we should turn back source address mode when rematerializing nodes */
990 if (is_Block(after)) {
993 block = get_nodes_block(after);
996 type = get_ia32_op_type(node);
1002 case ia32_AddrModeD:
1003 /* TODO implement this later... */
1004 panic("found DestAM with flag user %+F this should not happen", node);
1007 default: assert(type == ia32_Normal); break;
1010 copy = exact_copy(node);
1011 set_nodes_block(copy, block);
1012 sched_add_after(after, copy);
1018 * Called before the register allocator.
1020 static void ia32_before_ra(void *self) {
1021 ia32_code_gen_t *cg = self;
1023 /* setup fpu rounding modes */
1024 ia32_setup_fpu_mode(cg);
1027 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1030 ia32_add_missing_keeps(cg);
1035 * Transforms a be_Reload into a ia32 Load.
1037 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1038 ir_graph *irg = get_irn_irg(node);
1039 dbg_info *dbg = get_irn_dbg_info(node);
1040 ir_node *block = get_nodes_block(node);
1041 ir_entity *ent = be_get_frame_entity(node);
1042 ir_mode *mode = get_irn_mode(node);
1043 ir_mode *spillmode = get_spill_mode(node);
1044 ir_node *noreg = ia32_new_NoReg_gp(cg);
1045 ir_node *sched_point = NULL;
1046 ir_node *ptr = get_irg_frame(irg);
1047 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1048 ir_node *new_op, *proj;
1049 const arch_register_t *reg;
1051 if (sched_is_scheduled(node)) {
1052 sched_point = sched_prev(node);
1055 if (mode_is_float(spillmode)) {
1056 if (ia32_cg_config.use_sse2)
1057 new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
1059 new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
1061 else if (get_mode_size_bits(spillmode) == 128) {
1062 /* Reload 128 bit SSE registers */
1063 new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
1066 new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
1068 set_ia32_op_type(new_op, ia32_AddrModeS);
1069 set_ia32_ls_mode(new_op, spillmode);
1070 set_ia32_frame_ent(new_op, ent);
1071 set_ia32_use_frame(new_op);
1072 set_ia32_is_reload(new_op);
1074 DBG_OPT_RELOAD2LD(node, new_op);
1076 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1079 sched_add_after(sched_point, new_op);
1083 /* copy the register from the old node to the new Load */
1084 reg = arch_get_irn_register(node);
1085 arch_set_irn_register(proj, reg);
1087 SET_IA32_ORIG_NODE(new_op, node);
1089 exchange(node, proj);
1093 * Transforms a be_Spill node into a ia32 Store.
1095 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1096 ir_graph *irg = get_irn_irg(node);
1097 dbg_info *dbg = get_irn_dbg_info(node);
1098 ir_node *block = get_nodes_block(node);
1099 ir_entity *ent = be_get_frame_entity(node);
1100 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1101 ir_mode *mode = get_spill_mode(spillval);
1102 ir_node *noreg = ia32_new_NoReg_gp(cg);
1103 ir_node *nomem = new_NoMem();
1104 ir_node *ptr = get_irg_frame(irg);
1105 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1107 ir_node *sched_point = NULL;
1109 if (sched_is_scheduled(node)) {
1110 sched_point = sched_prev(node);
1113 /* No need to spill unknown values... */
1114 if(is_ia32_Unknown_GP(val) ||
1115 is_ia32_Unknown_VFP(val) ||
1116 is_ia32_Unknown_XMM(val)) {
1121 exchange(node, store);
1125 if (mode_is_float(mode)) {
1126 if (ia32_cg_config.use_sse2)
1127 store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
1129 store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
1130 } else if (get_mode_size_bits(mode) == 128) {
1131 /* Spill 128 bit SSE registers */
1132 store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
1133 } else if (get_mode_size_bits(mode) == 8) {
1134 store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
1136 store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
1139 set_ia32_op_type(store, ia32_AddrModeD);
1140 set_ia32_ls_mode(store, mode);
1141 set_ia32_frame_ent(store, ent);
1142 set_ia32_use_frame(store);
1143 set_ia32_is_spill(store);
1144 SET_IA32_ORIG_NODE(store, node);
1145 DBG_OPT_SPILL2ST(node, store);
1148 sched_add_after(sched_point, store);
1152 exchange(node, store);
1155 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1156 dbg_info *dbg = get_irn_dbg_info(node);
1157 ir_node *block = get_nodes_block(node);
1158 ir_node *noreg = ia32_new_NoReg_gp(cg);
1159 ir_graph *irg = get_irn_irg(node);
1160 ir_node *frame = get_irg_frame(irg);
1162 ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
1164 set_ia32_frame_ent(push, ent);
1165 set_ia32_use_frame(push);
1166 set_ia32_op_type(push, ia32_AddrModeS);
1167 set_ia32_ls_mode(push, mode_Is);
1168 set_ia32_is_spill(push);
1170 sched_add_before(schedpoint, push);
1174 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1175 dbg_info *dbg = get_irn_dbg_info(node);
1176 ir_node *block = get_nodes_block(node);
1177 ir_node *noreg = ia32_new_NoReg_gp(cg);
1178 ir_graph *irg = get_irn_irg(node);
1179 ir_node *frame = get_irg_frame(irg);
1181 ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp);
1183 set_ia32_frame_ent(pop, ent);
1184 set_ia32_use_frame(pop);
1185 set_ia32_op_type(pop, ia32_AddrModeD);
1186 set_ia32_ls_mode(pop, mode_Is);
1187 set_ia32_is_reload(pop);
1189 sched_add_before(schedpoint, pop);
1194 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1196 ir_graph *irg = get_irn_irg(node);
1197 dbg_info *dbg = get_irn_dbg_info(node);
1198 ir_node *block = get_nodes_block(node);
1199 ir_mode *spmode = mode_Iu;
1200 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1203 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1204 arch_set_irn_register(sp, spreg);
1210 * Transform MemPerm, currently we do this the ugly way and produce
1211 * push/pop into/from memory cascades. This is possible without using
1214 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
1216 ir_graph *irg = get_irn_irg(node);
1217 ir_node *block = get_nodes_block(node);
1218 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1219 int arity = be_get_MemPerm_entity_arity(node);
1220 ir_node **pops = ALLOCAN(ir_node*, arity);
1224 const ir_edge_t *edge;
1225 const ir_edge_t *next;
1228 for(i = 0; i < arity; ++i) {
1229 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1230 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1231 ir_type *enttype = get_entity_type(inent);
1232 unsigned entsize = get_type_size_bytes(enttype);
1233 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1234 ir_node *mem = get_irn_n(node, i + 1);
1237 /* work around cases where entities have different sizes */
1238 if(entsize2 < entsize)
1240 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1242 push = create_push(cg, node, node, sp, mem, inent);
1243 sp = create_spproj(node, push, pn_ia32_Push_stack);
1245 /* add another push after the first one */
1246 push = create_push(cg, node, node, sp, mem, inent);
1247 add_ia32_am_offs_int(push, 4);
1248 sp = create_spproj(node, push, pn_ia32_Push_stack);
1251 set_irn_n(node, i, new_Bad());
1255 for(i = arity - 1; i >= 0; --i) {
1256 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1257 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1258 ir_type *enttype = get_entity_type(outent);
1259 unsigned entsize = get_type_size_bytes(enttype);
1260 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1263 /* work around cases where entities have different sizes */
1264 if(entsize2 < entsize)
1266 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1268 pop = create_pop(cg, node, node, sp, outent);
1269 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1271 add_ia32_am_offs_int(pop, 4);
1273 /* add another pop after the first one */
1274 pop = create_pop(cg, node, node, sp, outent);
1275 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1282 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1283 sched_add_before(node, keep);
1285 /* exchange memprojs */
1286 foreach_out_edge_safe(node, edge, next) {
1287 ir_node *proj = get_edge_src_irn(edge);
1288 int p = get_Proj_proj(proj);
1292 set_Proj_pred(proj, pops[p]);
1293 set_Proj_proj(proj, pn_ia32_Pop_M);
1296 /* remove memperm */
1297 arity = get_irn_arity(node);
1298 for(i = 0; i < arity; ++i) {
1299 set_irn_n(node, i, new_Bad());
1305 * Block-Walker: Calls the transform functions Spill and Reload.
1307 static void ia32_after_ra_walker(ir_node *block, void *env) {
1308 ir_node *node, *prev;
1309 ia32_code_gen_t *cg = env;
1311 /* beware: the schedule is changed here */
1312 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1313 prev = sched_prev(node);
1315 if (be_is_Reload(node)) {
1316 transform_to_Load(cg, node);
1317 } else if (be_is_Spill(node)) {
1318 transform_to_Store(cg, node);
1319 } else if (be_is_MemPerm(node)) {
1320 transform_MemPerm(cg, node);
1326 * Collects nodes that need frame entities assigned.
1328 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1330 be_fec_env_t *env = data;
1331 const ir_mode *mode;
1334 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1335 mode = get_spill_mode_mode(get_irn_mode(node));
1336 align = get_mode_size_bytes(mode);
1337 } else if (is_ia32_irn(node) &&
1338 get_ia32_frame_ent(node) == NULL &&
1339 is_ia32_use_frame(node)) {
1340 if (is_ia32_need_stackent(node))
1343 switch (get_ia32_irn_opcode(node)) {
1345 case iro_ia32_Load: {
1346 const ia32_attr_t *attr = get_ia32_attr_const(node);
1348 if (attr->data.need_32bit_stackent) {
1350 } else if (attr->data.need_64bit_stackent) {
1353 mode = get_ia32_ls_mode(node);
1354 if (is_ia32_is_reload(node))
1355 mode = get_spill_mode_mode(mode);
1357 align = get_mode_size_bytes(mode);
1361 case iro_ia32_vfild:
1363 case iro_ia32_xLoad: {
1364 mode = get_ia32_ls_mode(node);
1369 case iro_ia32_FldCW: {
1370 /* although 2 byte would be enough 4 byte performs best */
1378 panic("unexpected frame user while collection frame entity nodes");
1380 case iro_ia32_FnstCW:
1381 case iro_ia32_Store8Bit:
1382 case iro_ia32_Store:
1385 case iro_ia32_vfist:
1386 case iro_ia32_vfisttp:
1388 case iro_ia32_xStore:
1389 case iro_ia32_xStoreSimple:
1396 be_node_needs_frame_entity(env, node, mode, align);
1400 * We transform Spill and Reload here. This needs to be done before
1401 * stack biasing otherwise we would miss the corrected offset for these nodes.
1403 static void ia32_after_ra(void *self) {
1404 ia32_code_gen_t *cg = self;
1405 ir_graph *irg = cg->irg;
1406 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1408 /* create and coalesce frame entities */
1409 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1410 be_assign_entities(fec_env);
1411 be_free_frame_entity_coalescer(fec_env);
1413 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1417 * Last touchups for the graph before emit: x87 simulation to replace the
1418 * virtual with real x87 instructions, creating a block schedule and peephole
1421 static void ia32_finish(void *self) {
1422 ia32_code_gen_t *cg = self;
1423 ir_graph *irg = cg->irg;
1425 ia32_finish_irg(irg, cg);
1427 /* we might have to rewrite x87 virtual registers */
1428 if (cg->do_x87_sim) {
1429 x87_simulate_graph(cg->birg);
1432 /* do peephole optimisations */
1433 ia32_peephole_optimization(cg);
1435 /* create block schedule, this also removes empty blocks which might
1436 * produce critical edges */
1437 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1441 * Emits the code, closes the output file and frees
1442 * the code generator interface.
1444 static void ia32_codegen(void *self) {
1445 ia32_code_gen_t *cg = self;
1446 ir_graph *irg = cg->irg;
1448 ia32_gen_routine(cg, irg);
1452 /* remove it from the isa */
1455 assert(ia32_current_cg == cg);
1456 ia32_current_cg = NULL;
1458 /* de-allocate code generator */
1459 del_set(cg->reg_set);
1464 * Returns the node representing the PIC base.
1466 static ir_node *ia32_get_pic_base(void *self) {
1468 ia32_code_gen_t *cg = self;
1469 ir_node *get_eip = cg->get_eip;
1470 if (get_eip != NULL)
1473 block = get_irg_start_block(cg->irg);
1474 get_eip = new_bd_ia32_GetEIP(NULL, block);
1475 cg->get_eip = get_eip;
1477 be_dep_on_frame(get_eip);
1481 static void *ia32_cg_init(be_irg_t *birg);
1483 static const arch_code_generator_if_t ia32_code_gen_if = {
1485 ia32_get_pic_base, /* return node used as base in pic code addresses */
1486 ia32_before_abi, /* before abi introduce hook */
1489 ia32_before_ra, /* before register allocation hook */
1490 ia32_after_ra, /* after register allocation hook */
1491 ia32_finish, /* called before codegen */
1492 ia32_codegen /* emit && done */
1496 * Initializes a IA32 code generator.
1498 static void *ia32_cg_init(be_irg_t *birg) {
1499 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env;
1500 ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t);
1502 cg->impl = &ia32_code_gen_if;
1503 cg->irg = birg->irg;
1504 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1507 cg->blk_sched = NULL;
1508 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1509 cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
1512 /* Linux gprof implementation needs base pointer */
1513 birg->main_env->options->omit_fp = 0;
1520 if (isa->name_obst) {
1521 obstack_free(isa->name_obst, NULL);
1522 obstack_init(isa->name_obst);
1526 cur_reg_set = cg->reg_set;
1528 assert(ia32_current_cg == NULL);
1529 ia32_current_cg = cg;
1531 return (arch_code_generator_t *)cg;
1536 /*****************************************************************
1537 * ____ _ _ _____ _____
1538 * | _ \ | | | | |_ _|/ ____| /\
1539 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1540 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1541 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1542 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1544 *****************************************************************/
1547 * Set output modes for GCC
1549 static const tarval_mode_info mo_integer = {
1556 * set the tarval output mode of all integer modes to decimal
1558 static void set_tarval_output_modes(void)
1562 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1563 ir_mode *mode = get_irp_mode(i);
1565 if (mode_is_int(mode))
1566 set_tarval_mode_output_option(mode, &mo_integer);
1570 const arch_isa_if_t ia32_isa_if;
1573 * The template that generates a new ISA object.
1574 * Note that this template can be changed by command line
1577 static ia32_isa_t ia32_isa_template = {
1579 &ia32_isa_if, /* isa interface implementation */
1580 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1581 &ia32_gp_regs[REG_EBP], /* base pointer register */
1582 -1, /* stack direction */
1583 2, /* power of two stack alignment, 2^2 == 4 */
1584 NULL, /* main environment */
1585 7, /* costs for a spill instruction */
1586 5, /* costs for a reload instruction */
1588 NULL, /* 16bit register names */
1589 NULL, /* 8bit register names */
1590 NULL, /* 8bit register names high */
1593 NULL, /* current code generator */
1594 NULL, /* abstract machine */
1596 NULL, /* name obstack */
1600 static void init_asm_constraints(void)
1602 be_init_default_asm_constraint_flags();
1604 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1605 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1606 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1607 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1608 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1609 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1610 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1611 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1612 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1613 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1614 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1615 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1616 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1617 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1618 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1619 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1620 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1621 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1622 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1623 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1625 /* no support for autodecrement/autoincrement */
1626 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1627 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1628 /* no float consts */
1629 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1630 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1631 /* makes no sense on x86 */
1632 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1633 /* no support for sse consts yet */
1634 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1635 /* no support for x87 consts yet */
1636 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1637 /* no support for mmx registers yet */
1638 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1639 /* not available in 32bit mode */
1640 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1641 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1643 /* no code yet to determine register class needed... */
1644 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1648 * Initializes the backend ISA.
1650 static arch_env_t *ia32_init(FILE *file_handle) {
1651 static int inited = 0;
1659 set_tarval_output_modes();
1661 isa = XMALLOC(ia32_isa_t);
1662 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1664 if(mode_fpcw == NULL) {
1665 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1668 ia32_register_init();
1669 ia32_create_opcodes(&ia32_irn_ops);
1671 be_emit_init(file_handle);
1672 isa->regs_16bit = pmap_create();
1673 isa->regs_8bit = pmap_create();
1674 isa->regs_8bit_high = pmap_create();
1675 isa->types = pmap_create();
1676 isa->tv_ent = pmap_create();
1677 isa->cpu = ia32_init_machine_description();
1679 ia32_build_16bit_reg_map(isa->regs_16bit);
1680 ia32_build_8bit_reg_map(isa->regs_8bit);
1681 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1684 isa->name_obst = XMALLOC(struct obstack);
1685 obstack_init(isa->name_obst);
1688 /* enter the ISA object into the intrinsic environment */
1689 intrinsic_env.isa = isa;
1691 /* emit asm includes */
1692 n = get_irp_n_asms();
1693 for (i = 0; i < n; ++i) {
1694 be_emit_cstring("#APP\n");
1695 be_emit_ident(get_irp_asm(i));
1696 be_emit_cstring("\n#NO_APP\n");
1699 /* needed for the debug support */
1700 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1701 be_emit_cstring(".Ltext0:\n");
1702 be_emit_write_line();
1704 /* we mark referenced global entities, so we can only emit those which
1705 * are actually referenced. (Note: you mustn't use the type visited flag
1706 * elsewhere in the backend)
1708 inc_master_type_visited();
1710 return &isa->arch_env;
1716 * Closes the output file and frees the ISA structure.
1718 static void ia32_done(void *self) {
1719 ia32_isa_t *isa = self;
1721 /* emit now all global declarations */
1722 be_gas_emit_decls(isa->arch_env.main_env, 1);
1724 pmap_destroy(isa->regs_16bit);
1725 pmap_destroy(isa->regs_8bit);
1726 pmap_destroy(isa->regs_8bit_high);
1727 pmap_destroy(isa->tv_ent);
1728 pmap_destroy(isa->types);
1731 obstack_free(isa->name_obst, NULL);
1741 * Return the number of register classes for this architecture.
1742 * We report always these:
1743 * - the general purpose registers
1744 * - the SSE floating point register set
1745 * - the virtual floating point registers
1746 * - the SSE vector register set
1748 static unsigned ia32_get_n_reg_class(const void *self) {
1754 * Return the register class for index i.
1756 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1760 assert(i < N_CLASSES);
1761 return &ia32_reg_classes[i];
1765 * Get the register class which shall be used to store a value of a given mode.
1766 * @param self The this pointer.
1767 * @param mode The mode in question.
1768 * @return A register class which can hold values of the given mode.
1770 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
1771 const ir_mode *mode)
1775 if (mode_is_float(mode)) {
1776 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1779 return &ia32_reg_classes[CLASS_ia32_gp];
1783 * Get the ABI restrictions for procedure calls.
1784 * @param self The this pointer.
1785 * @param method_type The type of the method (procedure) in question.
1786 * @param abi The abi object to be modified
1788 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1796 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1800 /* set abi flags for calls */
1801 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1802 call_flags.bits.store_args_sequential = 0;
1803 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1804 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1805 call_flags.bits.call_has_imm = 0; /* No call immediates, we handle this by ourselves */
1807 /* set parameter passing style */
1808 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1810 if (get_method_variadicity(method_type) == variadicity_variadic) {
1811 /* pass all parameters of a variadic function on the stack */
1814 cc = get_method_calling_convention(method_type);
1815 if (get_method_additional_properties(method_type) & mtp_property_private &&
1816 ia32_cg_config.optimize_cc) {
1817 /* set the calling conventions to register parameter */
1818 cc = (cc & ~cc_bits) | cc_reg_param;
1822 /* we have to pop the shadow parameter ourself for compound calls */
1823 if( (get_method_calling_convention(method_type) & cc_compound_ret)
1824 && !(cc & cc_reg_param)) {
1825 pop_amount += get_mode_size_bytes(mode_P_data);
1828 n = get_method_n_params(method_type);
1829 for (i = regnum = 0; i < n; i++) {
1831 const arch_register_t *reg = NULL;
1833 tp = get_method_param_type(method_type, i);
1834 mode = get_type_mode(tp);
1836 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1839 be_abi_call_param_reg(abi, i, reg);
1842 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1843 * movl has a shorter opcode than mov[sz][bw]l */
1844 ir_mode *load_mode = mode;
1847 unsigned size = get_mode_size_bytes(mode);
1849 if (cc & cc_callee_clear_stk) {
1850 pop_amount += (size + 3U) & ~3U;
1853 if (size < 4) load_mode = mode_Iu;
1856 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1860 be_abi_call_set_pop(abi, pop_amount);
1862 /* set return registers */
1863 n = get_method_n_ress(method_type);
1865 assert(n <= 2 && "more than two results not supported");
1867 /* In case of 64bit returns, we will have two 32bit values */
1869 tp = get_method_res_type(method_type, 0);
1870 mode = get_type_mode(tp);
1872 assert(!mode_is_float(mode) && "two FP results not supported");
1874 tp = get_method_res_type(method_type, 1);
1875 mode = get_type_mode(tp);
1877 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1879 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1880 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1883 const arch_register_t *reg;
1885 tp = get_method_res_type(method_type, 0);
1886 assert(is_atomic_type(tp));
1887 mode = get_type_mode(tp);
1889 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1891 be_abi_call_res_reg(abi, 0, reg);
1895 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1899 if(!is_ia32_irn(irn)) {
1903 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1904 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1905 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1906 || is_ia32_Immediate(irn))
1913 * Initializes the code generator interface.
1915 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1918 return &ia32_code_gen_if;
1922 * Returns the estimated execution time of an ia32 irn.
1924 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1926 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
1929 list_sched_selector_t ia32_sched_selector;
1932 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1934 static const list_sched_selector_t *ia32_get_list_sched_selector(
1935 const void *self, list_sched_selector_t *selector)
1938 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1939 ia32_sched_selector.exectime = ia32_sched_exectime;
1940 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1941 return &ia32_sched_selector;
1944 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1951 * Returns the necessary byte alignment for storing a register of given class.
1953 static int ia32_get_reg_class_alignment(const void *self,
1954 const arch_register_class_t *cls)
1956 ir_mode *mode = arch_register_class_mode(cls);
1957 int bytes = get_mode_size_bytes(mode);
1960 if (mode_is_float(mode) && bytes > 8)
1965 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1966 const void *self, const ir_node *irn)
1968 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1969 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1970 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1973 static const be_execution_unit_t *_allowed_units_GP[] = {
1974 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1975 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1976 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1977 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1978 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1979 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1980 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1983 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1984 &be_machine_execution_units_DUMMY[0],
1987 static const be_execution_unit_t **_units_callret[] = {
1988 _allowed_units_BRANCH,
1991 static const be_execution_unit_t **_units_other[] = {
1995 static const be_execution_unit_t **_units_dummy[] = {
1996 _allowed_units_DUMMY,
1999 const be_execution_unit_t ***ret;
2002 if (is_ia32_irn(irn)) {
2003 ret = get_ia32_exec_units(irn);
2004 } else if (is_be_node(irn)) {
2005 if (be_is_Return(irn)) {
2006 ret = _units_callret;
2007 } else if (be_is_Barrier(irn)) {
2021 * Return the abstract ia32 machine.
2023 static const be_machine_t *ia32_get_machine(const void *self) {
2024 const ia32_isa_t *isa = self;
2029 * Return irp irgs in the desired order.
2031 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2038 static void ia32_mark_remat(const void *self, ir_node *node) {
2040 if (is_ia32_irn(node)) {
2041 set_ia32_is_remat(node);
2046 * Check for Abs or -Abs.
2048 static int psi_is_Abs_or_Nabs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f) {
2055 /* must be <, <=, >=, > */
2056 pnc = get_Proj_proj(sel);
2057 if (pnc != pn_Cmp_Ge && pnc != pn_Cmp_Gt &&
2058 pnc != pn_Cmp_Le && pnc != pn_Cmp_Lt)
2061 l = get_Cmp_left(cmp);
2062 r = get_Cmp_right(cmp);
2064 /* must be x cmp 0 */
2065 if ((l != t && l != f) || !is_Const(r) || !is_Const_null(r))
2068 if ((!is_Minus(t) || get_Minus_op(t) != f) &&
2069 (!is_Minus(f) || get_Minus_op(f) != t))
2075 * Check for Abs only
2077 static int psi_is_Abs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f) {
2084 /* must be <, <=, >=, > */
2085 pnc = get_Proj_proj(sel);
2086 if (pnc != pn_Cmp_Ge && pnc != pn_Cmp_Gt &&
2087 pnc != pn_Cmp_Le && pnc != pn_Cmp_Lt)
2090 l = get_Cmp_left(cmp);
2091 r = get_Cmp_right(cmp);
2093 /* must be x cmp 0 */
2094 if ((l != t && l != f) || !is_Const(r) || !is_Const_null(r))
2097 if ((!is_Minus(t) || get_Minus_op(t) != f) &&
2098 (!is_Minus(f) || get_Minus_op(f) != t))
2101 if (pnc & pn_Cmp_Gt) {
2102 /* x >= 0 ? -x : x is NABS */
2106 /* x < 0 ? x : -x is NABS */
2115 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2117 * @param sel A selector of a Cond.
2118 * @param phi_list List of Phi nodes about to be converted (linked via get_Phi_next() field)
2119 * @param i First data predecessor involved in if conversion
2120 * @param j Second data predecessor involved in if conversion
2122 * @return 1 if allowed, 0 otherwise
2124 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2127 ir_node *cmp = NULL;
2129 /* we can't handle Psis with 64bit compares yet */
2131 cmp = get_Proj_pred(sel);
2133 ir_node *left = get_Cmp_left(cmp);
2134 ir_mode *cmp_mode = get_irn_mode(left);
2135 if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32) {
2136 /* 64bit Abs IS supported */
2137 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2138 ir_node *t = get_Phi_pred(phi, i);
2139 ir_node *f = get_Phi_pred(phi, j);
2141 if (! psi_is_Abs(cmp, sel, t, f))
2151 if (ia32_cg_config.use_cmov) {
2152 if (ia32_cg_config.use_sse2 && cmp != NULL) {
2153 pn_Cmp pn = get_Proj_proj(sel);
2154 ir_node *cl = get_Cmp_left(cmp);
2155 ir_node *cr = get_Cmp_right(cmp);
2157 /* check the Phi nodes: no 64bit and no floating point cmov */
2158 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2159 ir_mode *mode = get_irn_mode(phi);
2161 if (mode_is_float(mode)) {
2162 /* check for Min, Max */
2163 ir_node *t = get_Phi_pred(phi, i);
2164 ir_node *f = get_Phi_pred(phi, j);
2167 /* SSE2 supports Min & Max */
2168 if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2169 if (cl == t && cr == f) {
2170 /* Psi(a <=/>= b, a, b) => MIN, MAX */
2172 } else if (cl == f && cr == t) {
2173 /* Psi(a <=/>= b, b, a) => MAX, MIN */
2180 } else if (get_mode_size_bits(mode) > 32)
2184 /* check the Phi nodes: no 64bit and no floating point cmov */
2185 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2186 ir_mode *mode = get_irn_mode(phi);
2188 if (mode_is_float(mode)) {
2189 ir_node *t = get_Phi_pred(phi, i);
2190 ir_node *f = get_Phi_pred(phi, j);
2192 if (! psi_is_Abs_or_Nabs(cmp, sel, t, f))
2194 } else if (get_mode_size_bits(mode) > 32)
2204 /* No Cmov, only some special cases */
2208 /* Now some supported cases here */
2209 pn = get_Proj_proj(sel);
2210 cl = get_Cmp_left(cmp);
2211 cr = get_Cmp_right(cmp);
2213 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2214 ir_mode *mode = get_irn_mode(phi);
2218 t = get_Phi_pred(phi, i);
2219 f = get_Phi_pred(phi, j);
2221 if (mode_is_float(mode)) {
2222 /* only abs or nabs supported */
2223 if (! psi_is_Abs_or_Nabs(cmp, sel, t, f))
2225 } else if (get_mode_size_bits(mode) > 32) {
2230 if (is_Const(t) && is_Const(f)) {
2231 if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) {
2232 /* always support Psi(x, C1, C2) */
2235 } else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2238 } else if (cl == t && cr == f) {
2239 /* Psi(a <=/>= b, a, b) => Min, Max */
2241 } else if (cl == f && cr == t) {
2242 /* Psi(a <=/>= b, b, a) => Max, Min */
2245 } else if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) &&
2246 is_Const(f) && is_Const_null(f) && is_Sub(t) &&
2247 get_Sub_left(t) == cl && get_Sub_right(t) == cr) {
2248 /* Psi(a >=u b, a - b, 0) unsigned Doz */
2250 } else if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) &&
2251 is_Const(t) && is_Const_null(t) && is_Sub(f) &&
2252 get_Sub_left(f) == cl && get_Sub_right(f) == cr) {
2253 /* Psi(a <=u b, 0, a - b) unsigned Doz */
2255 } else if (is_Const(cr) && is_Const_null(cr)) {
2256 if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) {
2257 /* Psi(a <=/>= 0 ? a : -a) Nabs/Abs */
2259 } else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) {
2260 /* Psi(a <=/>= 0 ? -a : a) Abs/Nabs */
2268 /* all checks passed */
2274 static asm_constraint_flags_t ia32_parse_asm_constraint(const void *self, const char **c)
2279 /* we already added all our simple flags to the flags modifier list in
2280 * init, so this flag we don't know. */
2281 return ASM_CONSTRAINT_FLAG_INVALID;
2284 static int ia32_is_valid_clobber(const void *self, const char *clobber)
2288 return ia32_get_clobber_register(clobber) != NULL;
2292 * Returns the libFirm configuration parameter for this backend.
2294 static const backend_params *ia32_get_libfirm_params(void) {
2295 static const ir_settings_if_conv_t ifconv = {
2296 4, /* maxdepth, doesn't matter for Psi-conversion */
2297 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2299 static const ir_settings_arch_dep_t ad = {
2300 1, /* also use subs */
2301 4, /* maximum shifts */
2302 31, /* maximum shift amount */
2303 ia32_evaluate_insn, /* evaluate the instruction sequence */
2305 1, /* allow Mulhs */
2306 1, /* allow Mulus */
2307 32 /* Mulh allowed up to 32 bit */
2309 static backend_params p = {
2310 1, /* need dword lowering */
2311 1, /* support inline assembly */
2312 0, /* no immediate floating point mode. */
2313 NULL, /* no additional opcodes */
2314 NULL, /* will be set later */
2315 ia32_create_intrinsic_fkt,
2316 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2317 NULL, /* will be set below */
2318 NULL /* will be set below */
2321 ia32_setup_cg_config();
2323 /* doesn't really belong here, but this is the earliest place the backend
2325 init_asm_constraints();
2328 p.if_conv_info = &ifconv;
2332 static const lc_opt_enum_int_items_t gas_items[] = {
2333 { "elf", GAS_FLAVOUR_ELF },
2334 { "mingw", GAS_FLAVOUR_MINGW },
2335 { "yasm", GAS_FLAVOUR_YASM },
2336 { "macho", GAS_FLAVOUR_MACH_O },
2340 static lc_opt_enum_int_var_t gas_var = {
2341 (int*) &be_gas_flavour, gas_items
2344 #ifdef FIRM_GRGEN_BE
2345 static const lc_opt_enum_int_items_t transformer_items[] = {
2346 { "default", TRANSFORMER_DEFAULT },
2347 { "pbqp", TRANSFORMER_PBQP },
2348 { "random", TRANSFORMER_RAND },
2352 static lc_opt_enum_int_var_t transformer_var = {
2353 (int*)&be_transformer, transformer_items
2357 static const lc_opt_table_entry_t ia32_options[] = {
2358 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2359 #ifdef FIRM_GRGEN_BE
2360 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2362 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2363 &ia32_isa_template.arch_env.stack_alignment),
2367 const arch_isa_if_t ia32_isa_if = {
2370 ia32_handle_intrinsics,
2371 ia32_get_n_reg_class,
2373 ia32_get_reg_class_for_mode,
2375 ia32_get_code_generator_if,
2376 ia32_get_list_sched_selector,
2377 ia32_get_ilp_sched_selector,
2378 ia32_get_reg_class_alignment,
2379 ia32_get_libfirm_params,
2380 ia32_get_allowed_execution_units,
2384 ia32_parse_asm_constraint,
2385 ia32_is_valid_clobber
2388 void be_init_arch_ia32(void)
2390 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2391 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2393 lc_opt_add_table(ia32_grp, ia32_options);
2394 be_register_isa_if("ia32", &ia32_isa_if);
2396 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2398 ia32_init_emitter();
2400 ia32_init_optimize();
2401 ia32_init_transform();
2403 ia32_init_architecture();
2406 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);