2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
37 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
57 #include "../benode.h"
58 #include "../belower.h"
59 #include "../besched.h"
62 #include "../beirgmod.h"
63 #include "../be_dbgout.h"
64 #include "../beblocksched.h"
65 #include "../bemachine.h"
66 #include "../bespillslots.h"
67 #include "../bemodule.h"
68 #include "../begnuas.h"
69 #include "../bestate.h"
70 #include "../beflags.h"
71 #include "../betranshlp.h"
72 #include "../belistsched.h"
73 #include "../beabihelper.h"
75 #include "bearch_ia32_t.h"
77 #include "ia32_new_nodes.h"
78 #include "gen_ia32_regalloc_if.h"
79 #include "gen_ia32_machine.h"
80 #include "ia32_common_transform.h"
81 #include "ia32_transform.h"
82 #include "ia32_emitter.h"
83 #include "ia32_optimize.h"
85 #include "ia32_dbg_stat.h"
86 #include "ia32_finish.h"
88 #include "ia32_architecture.h"
91 #include "ia32_pbqp_transform.h"
93 transformer_t be_transformer = TRANSFORMER_DEFAULT;
96 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
98 ir_mode *ia32_mode_fpcw = NULL;
100 /** The current omit-fp state */
101 static ir_type *omit_fp_between_type = NULL;
102 static ir_type *between_type = NULL;
103 static ir_entity *old_bp_ent = NULL;
104 static ir_entity *ret_addr_ent = NULL;
105 static ir_entity *omit_fp_ret_addr_ent = NULL;
108 * The environment for the intrinsic mapping.
110 static ia32_intrinsic_env_t intrinsic_env = {
112 NULL, /* the irg, these entities belong to */
113 NULL, /* entity for __divdi3 library call */
114 NULL, /* entity for __moddi3 library call */
115 NULL, /* entity for __udivdi3 library call */
116 NULL, /* entity for __umoddi3 library call */
120 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
123 * Used to create per-graph unique pseudo nodes.
125 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
126 create_const_node_func func,
127 const arch_register_t* reg)
129 ir_node *block, *res;
134 block = get_irg_start_block(irg);
135 res = func(NULL, block);
136 arch_set_irn_register(res, reg);
142 /* Creates the unique per irg GP NoReg node. */
143 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
145 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
146 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
147 &ia32_registers[REG_GP_NOREG]);
150 ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
152 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
153 return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
154 &ia32_registers[REG_VFP_NOREG]);
157 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
159 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
160 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
161 &ia32_registers[REG_XMM_NOREG]);
164 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
166 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
167 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
168 &ia32_registers[REG_FPCW]);
173 * Returns the admissible noreg register node for input register pos of node irn.
175 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
177 ir_graph *irg = get_irn_irg(irn);
178 const arch_register_req_t *req = arch_get_register_req(irn, pos);
180 assert(req != NULL && "Missing register requirements");
181 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
182 return ia32_new_NoReg_gp(irg);
184 if (ia32_cg_config.use_sse2) {
185 return ia32_new_NoReg_xmm(irg);
187 return ia32_new_NoReg_vfp(irg);
191 static arch_irn_class_t ia32_classify(const ir_node *irn)
193 arch_irn_class_t classification = arch_irn_class_none;
195 assert(is_ia32_irn(irn));
197 if (is_ia32_is_reload(irn))
198 classification |= arch_irn_class_reload;
200 if (is_ia32_is_spill(irn))
201 classification |= arch_irn_class_spill;
203 if (is_ia32_is_remat(irn))
204 classification |= arch_irn_class_remat;
206 return classification;
210 * The IA32 ABI callback object.
213 be_abi_call_flags_bits_t flags; /**< The call flags. */
214 ir_graph *irg; /**< The associated graph. */
217 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
219 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
222 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
224 if (is_be_node(node))
225 be_node_set_frame_entity(node, entity);
227 set_ia32_frame_ent(node, entity);
230 static void ia32_set_frame_offset(ir_node *irn, int bias)
232 if (get_ia32_frame_ent(irn) == NULL)
235 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
236 ir_graph *irg = get_irn_irg(irn);
237 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
238 if (layout->sp_relative) {
239 /* Pop nodes modify the stack pointer before calculating the
240 * destination address, so fix this here
245 add_ia32_am_offs_int(irn, bias);
248 static int ia32_get_sp_bias(const ir_node *node)
250 if (is_ia32_Call(node))
251 return -(int)get_ia32_call_attr_const(node)->pop;
253 if (is_ia32_Push(node))
256 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
259 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
260 return SP_BIAS_RESET;
266 static int get_start_reg_index(ir_graph *irg, const arch_register_t *reg)
268 ir_node *start = get_irg_start(irg);
269 unsigned n_outs = arch_irn_get_n_outs(start);
272 /* do a naive linear search... */
273 for (i = 0; i < (int)n_outs; ++i) {
274 const arch_register_req_t *out_req
275 = arch_get_out_register_req(start, i);
276 if (! (out_req->type & arch_register_req_type_limited))
278 if (rbitset_is_set(out_req->limited, reg->index))
281 panic("Tried querying undefined register '%s' at Start", reg->name);
284 ir_node *ia32_get_initial_reg_value(ir_graph *irg, const arch_register_t *reg)
286 int i = get_start_reg_index(irg, reg);
287 ir_node *start = get_irg_start(irg);
288 ir_mode *mode = arch_register_class_mode(arch_register_get_class(reg));
289 const ir_edge_t *edge;
291 foreach_out_edge(start, edge) {
292 ir_node *proj = get_edge_src_irn(edge);
293 if (!is_Proj(proj)) // maybe End/Anchor
295 if (get_Proj_proj(proj) == i) {
299 ir_node *res = new_r_Proj(start, mode, i);
304 * Build the between type and entities if not already build.
306 static void ia32_build_between_type(void)
308 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
309 if (! between_type) {
310 ir_type *old_bp_type = new_type_primitive(mode_Iu);
311 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
313 between_type = new_type_struct(IDENT("ia32_between_type"));
314 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
315 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
317 set_entity_offset(old_bp_ent, 0);
318 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
319 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
320 set_type_state(between_type, layout_fixed);
322 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
323 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
325 set_entity_offset(omit_fp_ret_addr_ent, 0);
326 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
327 set_type_state(omit_fp_between_type, layout_fixed);
333 * Produces the type which sits between the stack args and the locals on the stack.
334 * it will contain the return address and space to store the old base pointer.
335 * @return The Firm type modeling the ABI between type.
337 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
339 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
340 ia32_build_between_type();
341 return layout->sp_relative ? omit_fp_between_type : between_type;
345 * Return the stack entity that contains the return address.
347 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
349 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
350 ia32_build_between_type();
351 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
355 * Return the stack entity that contains the frame address.
357 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
359 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
360 ia32_build_between_type();
361 return layout->sp_relative ? NULL : old_bp_ent;
365 * Get the estimated cycle count for @p irn.
367 * @param self The this pointer.
368 * @param irn The node.
370 * @return The estimated cycle count for this operation
372 static int ia32_get_op_estimated_cost(const ir_node *irn)
375 ia32_op_type_t op_tp;
379 if (!is_ia32_irn(irn))
382 assert(is_ia32_irn(irn));
384 cost = get_ia32_latency(irn);
385 op_tp = get_ia32_op_type(irn);
387 if (is_ia32_CopyB(irn)) {
390 else if (is_ia32_CopyB_i(irn)) {
391 int size = get_ia32_copyb_size(irn);
392 cost = 20 + (int)ceil((4/3) * size);
394 /* in case of address mode operations add additional cycles */
395 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
397 In case of stack access and access to fixed addresses add 5 cycles
398 (we assume they are in cache), other memory operations cost 20
401 if (is_ia32_use_frame(irn) || (
402 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
403 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
415 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
417 * @param irn The original operation
418 * @param i Index of the argument we want the inverse operation to yield
419 * @param inverse struct to be filled with the resulting inverse op
420 * @param obstack The obstack to use for allocation of the returned nodes array
421 * @return The inverse operation or NULL if operation invertible
423 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
434 ir_node *block, *noreg, *nomem;
437 /* we cannot invert non-ia32 irns */
438 if (! is_ia32_irn(irn))
441 /* operand must always be a real operand (not base, index or mem) */
442 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
445 /* we don't invert address mode operations */
446 if (get_ia32_op_type(irn) != ia32_Normal)
449 /* TODO: adjust for new immediates... */
450 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
454 block = get_nodes_block(irn);
455 mode = get_irn_mode(irn);
456 irn_mode = get_irn_mode(irn);
457 noreg = get_irn_n(irn, 0);
458 nomem = new_r_NoMem(irg);
459 dbg = get_irn_dbg_info(irn);
461 /* initialize structure */
462 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
466 switch (get_ia32_irn_opcode(irn)) {
468 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
469 /* we have an add with a const here */
470 /* invers == add with negated const */
471 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
473 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
474 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
475 set_ia32_commutative(inverse->nodes[0]);
477 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
478 /* we have an add with a symconst here */
479 /* invers == sub with const */
480 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
482 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
485 /* normal add: inverse == sub */
486 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
491 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
492 /* we have a sub with a const/symconst here */
493 /* invers == add with this const */
494 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
495 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
496 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
500 if (i == n_ia32_binary_left) {
501 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
504 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
510 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
511 /* xor with const: inverse = xor */
512 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
513 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
514 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
518 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
523 inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
528 inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
533 /* inverse operation not supported */
541 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
543 if (mode_is_float(mode))
550 * Get the mode that should be used for spilling value node
552 static ir_mode *get_spill_mode(const ir_node *node)
554 ir_mode *mode = get_irn_mode(node);
555 return get_spill_mode_mode(mode);
559 * Checks whether an addressmode reload for a node with mode mode is compatible
560 * with a spillslot of mode spill_mode
562 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
564 return !mode_is_float(mode) || mode == spillmode;
568 * Check if irn can load its operand at position i from memory (source addressmode).
569 * @param irn The irn to be checked
570 * @param i The operands position
571 * @return Non-Zero if operand can be loaded
573 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
575 ir_node *op = get_irn_n(irn, i);
576 const ir_mode *mode = get_irn_mode(op);
577 const ir_mode *spillmode = get_spill_mode(op);
579 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
580 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
581 !ia32_is_spillmode_compatible(mode, spillmode) ||
582 is_ia32_use_frame(irn)) /* must not already use frame */
585 switch (get_ia32_am_support(irn)) {
590 if (i != n_ia32_unary_op)
596 case n_ia32_binary_left: {
597 const arch_register_req_t *req;
598 if (!is_ia32_commutative(irn))
601 /* we can't swap left/right for limited registers
602 * (As this (currently) breaks constraint handling copies)
604 req = arch_get_in_register_req(irn, n_ia32_binary_left);
605 if (req->type & arch_register_req_type_limited)
610 case n_ia32_binary_right:
619 panic("Unknown AM type");
622 /* HACK: must not already use "real" memory.
623 * This can happen for Call and Div */
624 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
630 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
634 ir_mode *dest_op_mode;
636 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
638 set_ia32_op_type(irn, ia32_AddrModeS);
640 load_mode = get_irn_mode(get_irn_n(irn, i));
641 dest_op_mode = get_ia32_ls_mode(irn);
642 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
643 set_ia32_ls_mode(irn, load_mode);
645 set_ia32_use_frame(irn);
646 set_ia32_need_stackent(irn);
648 if (i == n_ia32_binary_left &&
649 get_ia32_am_support(irn) == ia32_am_binary &&
650 /* immediates are only allowed on the right side */
651 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
652 ia32_swap_left_right(irn);
653 i = n_ia32_binary_right;
656 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
658 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
659 set_irn_n(irn, n_ia32_mem, spill);
660 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
661 set_ia32_is_reload(irn);
664 static const be_abi_callbacks_t ia32_abi_callbacks = {
665 ia32_abi_get_between_type,
668 /* register allocator interface */
669 static const arch_irn_ops_t ia32_irn_ops = {
671 ia32_get_frame_entity,
672 ia32_set_frame_offset,
675 ia32_get_op_estimated_cost,
676 ia32_possible_memory_operand,
677 ia32_perform_memory_operand,
680 static ir_entity *mcount = NULL;
681 static int gprof = 0;
683 static void ia32_before_abi(ir_graph *irg)
686 if (mcount == NULL) {
687 ir_type *tp = new_type_method(0, 0);
688 ident *id = new_id_from_str("mcount");
689 mcount = new_entity(get_glob_type(), id, tp);
690 /* FIXME: enter the right ld_ident here */
691 set_entity_ld_ident(mcount, get_entity_ident(mcount));
692 set_entity_visibility(mcount, ir_visibility_external);
694 instrument_initcall(irg, mcount);
699 * Transforms the standard firm graph into
702 static void ia32_prepare_graph(ir_graph *irg)
704 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
707 switch (be_transformer) {
708 case TRANSFORMER_DEFAULT:
709 /* transform remaining nodes into assembler instructions */
710 ia32_transform_graph(irg);
713 case TRANSFORMER_PBQP:
714 case TRANSFORMER_RAND:
715 /* transform nodes into assembler instructions by PBQP magic */
716 ia32_transform_graph_by_pbqp(irg);
720 panic("invalid transformer");
723 ia32_transform_graph(irg);
726 /* do local optimizations (mainly CSE) */
727 optimize_graph_df(irg);
730 dump_ir_graph(irg, "transformed");
732 /* optimize address mode */
733 ia32_optimize_graph(irg);
735 /* do code placement, to optimize the position of constants */
739 dump_ir_graph(irg, "place");
742 ir_node *ia32_turn_back_am(ir_node *node)
744 dbg_info *dbgi = get_irn_dbg_info(node);
745 ir_graph *irg = get_irn_irg(node);
746 ir_node *block = get_nodes_block(node);
747 ir_node *base = get_irn_n(node, n_ia32_base);
748 ir_node *index = get_irn_n(node, n_ia32_index);
749 ir_node *mem = get_irn_n(node, n_ia32_mem);
752 ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
753 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
755 ia32_copy_am_attrs(load, node);
756 if (is_ia32_is_reload(node))
757 set_ia32_is_reload(load);
758 set_irn_n(node, n_ia32_mem, new_r_NoMem(irg));
760 switch (get_ia32_am_support(node)) {
762 set_irn_n(node, n_ia32_unary_op, load_res);
766 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
767 set_irn_n(node, n_ia32_binary_left, load_res);
769 set_irn_n(node, n_ia32_binary_right, load_res);
774 panic("Unknown AM type");
776 noreg = ia32_new_NoReg_gp(current_ir_graph);
777 set_irn_n(node, n_ia32_base, noreg);
778 set_irn_n(node, n_ia32_index, noreg);
779 set_ia32_am_offs_int(node, 0);
780 set_ia32_am_sc(node, NULL);
781 set_ia32_am_scale(node, 0);
782 clear_ia32_am_sc_sign(node);
784 /* rewire mem-proj */
785 if (get_irn_mode(node) == mode_T) {
786 const ir_edge_t *edge;
787 foreach_out_edge(node, edge) {
788 ir_node *out = get_edge_src_irn(edge);
789 if (get_irn_mode(out) == mode_M) {
790 set_Proj_pred(out, load);
791 set_Proj_proj(out, pn_ia32_Load_M);
797 set_ia32_op_type(node, ia32_Normal);
798 if (sched_is_scheduled(node))
799 sched_add_before(node, load);
804 static ir_node *flags_remat(ir_node *node, ir_node *after)
806 /* we should turn back source address mode when rematerializing nodes */
811 if (is_Block(after)) {
814 block = get_nodes_block(after);
817 type = get_ia32_op_type(node);
820 ia32_turn_back_am(node);
824 /* TODO implement this later... */
825 panic("found DestAM with flag user %+F this should not happen", node);
828 default: assert(type == ia32_Normal); break;
831 copy = exact_copy(node);
832 set_nodes_block(copy, block);
833 sched_add_after(after, copy);
839 * Called before the register allocator.
841 static void ia32_before_ra(ir_graph *irg)
843 /* setup fpu rounding modes */
844 ia32_setup_fpu_mode(irg);
847 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
850 be_add_missing_keeps(irg);
855 * Transforms a be_Reload into a ia32 Load.
857 static void transform_to_Load(ir_node *node)
859 ir_graph *irg = get_irn_irg(node);
860 dbg_info *dbg = get_irn_dbg_info(node);
861 ir_node *block = get_nodes_block(node);
862 ir_entity *ent = be_get_frame_entity(node);
863 ir_mode *mode = get_irn_mode(node);
864 ir_mode *spillmode = get_spill_mode(node);
865 ir_node *noreg = ia32_new_NoReg_gp(irg);
866 ir_node *sched_point = NULL;
867 ir_node *ptr = get_irg_frame(irg);
868 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
869 ir_node *new_op, *proj;
870 const arch_register_t *reg;
872 if (sched_is_scheduled(node)) {
873 sched_point = sched_prev(node);
876 if (mode_is_float(spillmode)) {
877 if (ia32_cg_config.use_sse2)
878 new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
880 new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
882 else if (get_mode_size_bits(spillmode) == 128) {
883 /* Reload 128 bit SSE registers */
884 new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
887 new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
889 set_ia32_op_type(new_op, ia32_AddrModeS);
890 set_ia32_ls_mode(new_op, spillmode);
891 set_ia32_frame_ent(new_op, ent);
892 set_ia32_use_frame(new_op);
893 set_ia32_is_reload(new_op);
895 DBG_OPT_RELOAD2LD(node, new_op);
897 proj = new_rd_Proj(dbg, new_op, mode, pn_ia32_Load_res);
900 sched_add_after(sched_point, new_op);
904 /* copy the register from the old node to the new Load */
905 reg = arch_get_irn_register(node);
906 arch_set_irn_register(proj, reg);
908 SET_IA32_ORIG_NODE(new_op, node);
910 exchange(node, proj);
914 * Transforms a be_Spill node into a ia32 Store.
916 static void transform_to_Store(ir_node *node)
918 ir_graph *irg = get_irn_irg(node);
919 dbg_info *dbg = get_irn_dbg_info(node);
920 ir_node *block = get_nodes_block(node);
921 ir_entity *ent = be_get_frame_entity(node);
922 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
923 ir_mode *mode = get_spill_mode(spillval);
924 ir_node *noreg = ia32_new_NoReg_gp(irg);
925 ir_node *nomem = new_r_NoMem(irg);
926 ir_node *ptr = get_irg_frame(irg);
927 ir_node *val = get_irn_n(node, n_be_Spill_val);
929 ir_node *sched_point = NULL;
931 if (sched_is_scheduled(node)) {
932 sched_point = sched_prev(node);
935 if (mode_is_float(mode)) {
936 if (ia32_cg_config.use_sse2)
937 store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
939 store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
940 } else if (get_mode_size_bits(mode) == 128) {
941 /* Spill 128 bit SSE registers */
942 store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
943 } else if (get_mode_size_bits(mode) == 8) {
944 store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
946 store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
949 set_ia32_op_type(store, ia32_AddrModeD);
950 set_ia32_ls_mode(store, mode);
951 set_ia32_frame_ent(store, ent);
952 set_ia32_use_frame(store);
953 set_ia32_is_spill(store);
954 SET_IA32_ORIG_NODE(store, node);
955 DBG_OPT_SPILL2ST(node, store);
958 sched_add_after(sched_point, store);
962 exchange(node, store);
965 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
967 dbg_info *dbg = get_irn_dbg_info(node);
968 ir_node *block = get_nodes_block(node);
969 ir_graph *irg = get_irn_irg(node);
970 ir_node *noreg = ia32_new_NoReg_gp(irg);
971 ir_node *frame = get_irg_frame(irg);
973 ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
975 set_ia32_frame_ent(push, ent);
976 set_ia32_use_frame(push);
977 set_ia32_op_type(push, ia32_AddrModeS);
978 set_ia32_ls_mode(push, mode_Is);
979 set_ia32_is_spill(push);
981 sched_add_before(schedpoint, push);
985 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
987 dbg_info *dbg = get_irn_dbg_info(node);
988 ir_node *block = get_nodes_block(node);
989 ir_graph *irg = get_irn_irg(node);
990 ir_node *noreg = ia32_new_NoReg_gp(irg);
991 ir_node *frame = get_irg_frame(irg);
993 ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_r_NoMem(irg), sp);
995 set_ia32_frame_ent(pop, ent);
996 set_ia32_use_frame(pop);
997 set_ia32_op_type(pop, ia32_AddrModeD);
998 set_ia32_ls_mode(pop, mode_Is);
999 set_ia32_is_reload(pop);
1001 sched_add_before(schedpoint, pop);
1006 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1008 dbg_info *dbg = get_irn_dbg_info(node);
1009 ir_mode *spmode = mode_Iu;
1010 const arch_register_t *spreg = &ia32_registers[REG_ESP];
1013 sp = new_rd_Proj(dbg, pred, spmode, pos);
1014 arch_set_irn_register(sp, spreg);
1020 * Transform MemPerm, currently we do this the ugly way and produce
1021 * push/pop into/from memory cascades. This is possible without using
1024 static void transform_MemPerm(ir_node *node)
1026 ir_node *block = get_nodes_block(node);
1027 ir_graph *irg = get_irn_irg(node);
1028 ir_node *sp = ia32_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
1029 int arity = be_get_MemPerm_entity_arity(node);
1030 ir_node **pops = ALLOCAN(ir_node*, arity);
1034 const ir_edge_t *edge;
1035 const ir_edge_t *next;
1038 for (i = 0; i < arity; ++i) {
1039 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1040 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1041 ir_type *enttype = get_entity_type(inent);
1042 unsigned entsize = get_type_size_bytes(enttype);
1043 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1044 ir_node *mem = get_irn_n(node, i + 1);
1047 /* work around cases where entities have different sizes */
1048 if (entsize2 < entsize)
1050 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1052 push = create_push(node, node, sp, mem, inent);
1053 sp = create_spproj(node, push, pn_ia32_Push_stack);
1055 /* add another push after the first one */
1056 push = create_push(node, node, sp, mem, inent);
1057 add_ia32_am_offs_int(push, 4);
1058 sp = create_spproj(node, push, pn_ia32_Push_stack);
1061 set_irn_n(node, i, new_r_Bad(irg));
1065 for (i = arity - 1; i >= 0; --i) {
1066 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1067 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1068 ir_type *enttype = get_entity_type(outent);
1069 unsigned entsize = get_type_size_bytes(enttype);
1070 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1073 /* work around cases where entities have different sizes */
1074 if (entsize2 < entsize)
1076 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1078 pop = create_pop(node, node, sp, outent);
1079 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1081 add_ia32_am_offs_int(pop, 4);
1083 /* add another pop after the first one */
1084 pop = create_pop(node, node, sp, outent);
1085 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1092 keep = be_new_Keep(block, 1, in);
1093 sched_add_before(node, keep);
1095 /* exchange memprojs */
1096 foreach_out_edge_safe(node, edge, next) {
1097 ir_node *proj = get_edge_src_irn(edge);
1098 int p = get_Proj_proj(proj);
1102 set_Proj_pred(proj, pops[p]);
1103 set_Proj_proj(proj, pn_ia32_Pop_M);
1106 /* remove memperm */
1107 arity = get_irn_arity(node);
1108 for (i = 0; i < arity; ++i) {
1109 set_irn_n(node, i, new_r_Bad(irg));
1115 * Block-Walker: Calls the transform functions Spill and Reload.
1117 static void ia32_after_ra_walker(ir_node *block, void *env)
1119 ir_node *node, *prev;
1122 /* beware: the schedule is changed here */
1123 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1124 prev = sched_prev(node);
1126 if (be_is_Reload(node)) {
1127 transform_to_Load(node);
1128 } else if (be_is_Spill(node)) {
1129 transform_to_Store(node);
1130 } else if (be_is_MemPerm(node)) {
1131 transform_MemPerm(node);
1137 * Collects nodes that need frame entities assigned.
1139 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1141 be_fec_env_t *env = (be_fec_env_t*)data;
1142 const ir_mode *mode;
1145 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1146 mode = get_spill_mode_mode(get_irn_mode(node));
1147 align = get_mode_size_bytes(mode);
1148 } else if (is_ia32_irn(node) &&
1149 get_ia32_frame_ent(node) == NULL &&
1150 is_ia32_use_frame(node)) {
1151 if (is_ia32_need_stackent(node))
1154 switch (get_ia32_irn_opcode(node)) {
1156 case iro_ia32_Load: {
1157 const ia32_attr_t *attr = get_ia32_attr_const(node);
1159 if (attr->data.need_32bit_stackent) {
1161 } else if (attr->data.need_64bit_stackent) {
1164 mode = get_ia32_ls_mode(node);
1165 if (is_ia32_is_reload(node))
1166 mode = get_spill_mode_mode(mode);
1168 align = get_mode_size_bytes(mode);
1172 case iro_ia32_vfild:
1174 case iro_ia32_xLoad: {
1175 mode = get_ia32_ls_mode(node);
1180 case iro_ia32_FldCW: {
1181 /* although 2 byte would be enough 4 byte performs best */
1189 panic("unexpected frame user while collection frame entity nodes");
1191 case iro_ia32_FnstCW:
1192 case iro_ia32_Store8Bit:
1193 case iro_ia32_Store:
1196 case iro_ia32_vfist:
1197 case iro_ia32_vfisttp:
1199 case iro_ia32_xStore:
1200 case iro_ia32_xStoreSimple:
1207 be_node_needs_frame_entity(env, node, mode, align);
1210 static int determine_ebp_input(ir_node *ret)
1212 const arch_register_t *bp = &ia32_registers[REG_EBP];
1213 int arity = get_irn_arity(ret);
1216 for (i = 0; i < arity; ++i) {
1217 ir_node *input = get_irn_n(ret, i);
1218 if (arch_get_irn_register(input) == bp)
1221 panic("no ebp input found at %+F", ret);
1224 static void introduce_epilog(ir_node *ret)
1226 const arch_register_t *sp = &ia32_registers[REG_ESP];
1227 const arch_register_t *bp = &ia32_registers[REG_EBP];
1228 ir_graph *irg = get_irn_irg(ret);
1229 ir_type *frame_type = get_irg_frame_type(irg);
1230 unsigned frame_size = get_type_size_bytes(frame_type);
1231 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1232 ir_node *block = get_nodes_block(ret);
1233 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1234 ir_node *curr_sp = first_sp;
1235 ir_mode *mode_gp = mode_Iu;
1237 if (!layout->sp_relative) {
1238 int n_ebp = determine_ebp_input(ret);
1239 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1240 if (ia32_cg_config.use_leave) {
1241 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1242 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1243 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1244 arch_set_irn_register(curr_bp, bp);
1245 arch_set_irn_register(curr_sp, sp);
1246 sched_add_before(ret, leave);
1249 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1250 /* copy ebp to esp */
1251 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1252 arch_set_irn_register(curr_sp, sp);
1253 sched_add_before(ret, curr_sp);
1256 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1257 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1258 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1259 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1260 arch_set_irn_register(curr_bp, bp);
1261 arch_set_irn_register(curr_sp, sp);
1262 sched_add_before(ret, pop);
1264 set_irn_n(ret, n_be_Return_mem, curr_mem);
1266 set_irn_n(ret, n_ebp, curr_bp);
1268 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1269 sched_add_before(ret, incsp);
1272 set_irn_n(ret, n_be_Return_sp, curr_sp);
1274 /* keep verifier happy... */
1275 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1276 kill_node(first_sp);
1281 * put the Prolog code at the beginning, epilog code before each return
1283 static void introduce_prolog_epilog(ir_graph *irg)
1285 const arch_register_t *sp = &ia32_registers[REG_ESP];
1286 const arch_register_t *bp = &ia32_registers[REG_EBP];
1287 ir_node *start = get_irg_start(irg);
1288 ir_node *block = get_nodes_block(start);
1289 ir_type *frame_type = get_irg_frame_type(irg);
1290 unsigned frame_size = get_type_size_bytes(frame_type);
1291 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1292 ir_node *initial_sp = ia32_get_initial_reg_value(irg, sp);
1293 ir_node *curr_sp = initial_sp;
1294 ir_mode *mode_gp = mode_Iu;
1296 if (!layout->sp_relative) {
1298 ir_node *mem = get_irg_initial_mem(irg);
1299 ir_node *noreg = ia32_new_NoReg_gp(irg);
1300 ir_node *initial_bp = ia32_get_initial_reg_value(irg, bp);
1301 ir_node *curr_bp = initial_bp;
1302 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
1305 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1306 mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
1307 arch_set_irn_register(curr_sp, sp);
1308 sched_add_after(start, push);
1310 /* move esp to ebp */
1311 curr_bp = be_new_Copy(bp->reg_class, block, curr_sp);
1312 sched_add_after(push, curr_bp);
1313 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1314 curr_sp = be_new_CopyKeep_single(sp->reg_class, block, curr_sp, curr_bp, mode_gp);
1315 sched_add_after(curr_bp, curr_sp);
1316 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1317 edges_reroute(initial_bp, curr_bp);
1318 set_irn_n(push, n_ia32_Push_val, initial_bp);
1320 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1321 edges_reroute(initial_sp, incsp);
1322 set_irn_n(push, n_ia32_Push_stack, initial_sp);
1323 sched_add_after(curr_sp, incsp);
1325 layout->initial_bias = -4;
1327 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1328 edges_reroute(initial_sp, incsp);
1329 be_set_IncSP_pred(incsp, curr_sp);
1330 sched_add_after(start, incsp);
1333 /* introduce epilog for every return node */
1335 ir_node *end_block = get_irg_end_block(irg);
1336 int arity = get_irn_arity(end_block);
1339 for (i = 0; i < arity; ++i) {
1340 ir_node *ret = get_irn_n(end_block, i);
1341 assert(be_is_Return(ret));
1342 introduce_epilog(ret);
1348 * We transform Spill and Reload here. This needs to be done before
1349 * stack biasing otherwise we would miss the corrected offset for these nodes.
1351 static void ia32_after_ra(ir_graph *irg)
1353 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1354 bool at_begin = stack_layout->sp_relative ? true : false;
1355 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1357 /* create and coalesce frame entities */
1358 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1359 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1360 be_free_frame_entity_coalescer(fec_env);
1362 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1364 introduce_prolog_epilog(irg);
1368 * Last touchups for the graph before emit: x87 simulation to replace the
1369 * virtual with real x87 instructions, creating a block schedule and peephole
1372 static void ia32_finish(ir_graph *irg)
1374 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1376 ia32_finish_irg(irg);
1378 /* we might have to rewrite x87 virtual registers */
1379 if (irg_data->do_x87_sim) {
1380 ia32_x87_simulate_graph(irg);
1383 /* do peephole optimisations */
1384 ia32_peephole_optimization(irg);
1386 /* create block schedule, this also removes empty blocks which might
1387 * produce critical edges */
1388 irg_data->blk_sched = be_create_block_schedule(irg);
1392 * Emits the code, closes the output file and frees
1393 * the code generator interface.
1395 static void ia32_emit(ir_graph *irg)
1397 if (ia32_cg_config.emit_machcode) {
1398 ia32_gen_binary_routine(irg);
1400 ia32_gen_routine(irg);
1405 * Returns the node representing the PIC base.
1407 static ir_node *ia32_get_pic_base(ir_graph *irg)
1409 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1411 ir_node *get_eip = irg_data->get_eip;
1412 if (get_eip != NULL)
1415 block = get_irg_start_block(irg);
1416 get_eip = new_bd_ia32_GetEIP(NULL, block);
1417 irg_data->get_eip = get_eip;
1423 * Initializes a IA32 code generator.
1425 static void ia32_init_graph(ir_graph *irg)
1427 struct obstack *obst = be_get_be_obst(irg);
1428 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1430 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1433 /* Linux gprof implementation needs base pointer */
1434 be_get_irg_options(irg)->omit_fp = 0;
1437 be_birg_from_irg(irg)->isa_link = irg_data;
1442 * Set output modes for GCC
1444 static const tarval_mode_info mo_integer = {
1451 * set the tarval output mode of all integer modes to decimal
1453 static void set_tarval_output_modes(void)
1457 for (i = get_irp_n_modes(); i > 0;) {
1458 ir_mode *mode = get_irp_mode(--i);
1460 if (mode_is_int(mode))
1461 set_tarval_mode_output_option(mode, &mo_integer);
1465 extern const arch_isa_if_t ia32_isa_if;
1468 * The template that generates a new ISA object.
1469 * Note that this template can be changed by command line
1472 static ia32_isa_t ia32_isa_template = {
1474 &ia32_isa_if, /* isa interface implementation */
1479 &ia32_registers[REG_ESP], /* stack pointer register */
1480 &ia32_registers[REG_EBP], /* base pointer register */
1481 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1482 2, /* power of two stack alignment, 2^2 == 4 */
1483 NULL, /* main environment */
1484 7, /* costs for a spill instruction */
1485 5, /* costs for a reload instruction */
1486 false, /* no custom abi handling */
1490 NULL, /* abstract machine */
1493 static void init_asm_constraints(void)
1495 be_init_default_asm_constraint_flags();
1497 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1498 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1499 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1500 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1501 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1502 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1503 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1504 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1505 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1506 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1507 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1508 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1509 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1510 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1511 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1512 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1513 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1514 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1515 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1516 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1518 /* no support for autodecrement/autoincrement */
1519 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1520 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1521 /* no float consts */
1522 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1523 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1524 /* makes no sense on x86 */
1525 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1526 /* no support for sse consts yet */
1527 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1528 /* no support for x87 consts yet */
1529 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1530 /* no support for mmx registers yet */
1531 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1532 /* not available in 32bit mode */
1533 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1534 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1536 /* no code yet to determine register class needed... */
1537 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1541 * Initializes the backend ISA.
1543 static arch_env_t *ia32_init(FILE *file_handle)
1545 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1547 set_tarval_output_modes();
1549 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1551 if (ia32_mode_fpcw == NULL) {
1552 ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1555 ia32_register_init();
1556 ia32_create_opcodes(&ia32_irn_ops);
1558 be_emit_init(file_handle);
1559 isa->types = pmap_create();
1560 isa->tv_ent = pmap_create();
1561 isa->cpu = ia32_init_machine_description();
1563 /* enter the ISA object into the intrinsic environment */
1564 intrinsic_env.isa = isa;
1572 * Closes the output file and frees the ISA structure.
1574 static void ia32_done(void *self)
1576 ia32_isa_t *isa = (ia32_isa_t*)self;
1578 /* emit now all global declarations */
1579 be_gas_emit_decls(isa->base.main_env);
1581 pmap_destroy(isa->tv_ent);
1582 pmap_destroy(isa->types);
1591 * Get the register class which shall be used to store a value of a given mode.
1592 * @param self The this pointer.
1593 * @param mode The mode in question.
1594 * @return A register class which can hold values of the given mode.
1596 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1598 if (mode_is_float(mode)) {
1599 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1602 return &ia32_reg_classes[CLASS_ia32_gp];
1606 * Returns the register for parameter nr.
1608 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1609 const ir_mode *mode)
1611 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1612 &ia32_registers[REG_ECX],
1613 &ia32_registers[REG_EDX],
1616 static const unsigned MAXNUM_GPREG_ARGS = 3;
1618 static const arch_register_t *gpreg_param_reg_regparam[] = {
1619 &ia32_registers[REG_EAX],
1620 &ia32_registers[REG_EDX],
1621 &ia32_registers[REG_ECX]
1624 static const arch_register_t *gpreg_param_reg_this[] = {
1625 &ia32_registers[REG_ECX],
1630 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1631 &ia32_registers[REG_XMM0],
1632 &ia32_registers[REG_XMM1],
1633 &ia32_registers[REG_XMM2],
1634 &ia32_registers[REG_XMM3],
1635 &ia32_registers[REG_XMM4],
1636 &ia32_registers[REG_XMM5],
1637 &ia32_registers[REG_XMM6],
1638 &ia32_registers[REG_XMM7]
1641 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1642 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1644 static const unsigned MAXNUM_SSE_ARGS = 8;
1646 if ((cc & cc_this_call) && nr == 0)
1647 return gpreg_param_reg_this[0];
1649 if (! (cc & cc_reg_param))
1652 if (mode_is_float(mode)) {
1653 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1655 if (nr >= MAXNUM_SSE_ARGS)
1658 if (cc & cc_this_call) {
1659 return fpreg_sse_param_reg_this[nr];
1661 return fpreg_sse_param_reg_std[nr];
1662 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1663 unsigned num_regparam;
1665 if (get_mode_size_bits(mode) > 32)
1668 if (nr >= MAXNUM_GPREG_ARGS)
1671 if (cc & cc_this_call) {
1672 return gpreg_param_reg_this[nr];
1674 num_regparam = cc & ~cc_bits;
1675 if (num_regparam == 0) {
1676 /* default fastcall */
1677 return gpreg_param_reg_fastcall[nr];
1679 if (nr < num_regparam)
1680 return gpreg_param_reg_regparam[nr];
1684 panic("unknown argument mode");
1688 * Get the ABI restrictions for procedure calls.
1689 * @param self The this pointer.
1690 * @param method_type The type of the method (procedure) in question.
1691 * @param abi The abi object to be modified
1693 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1701 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1705 /* set abi flags for calls */
1706 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1707 call_flags.bits.store_args_sequential = 0;
1708 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1709 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1710 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1712 /* set parameter passing style */
1713 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1715 cc = get_method_calling_convention(method_type);
1716 if (get_method_variadicity(method_type) == variadicity_variadic) {
1717 /* pass all parameters of a variadic function on the stack */
1718 cc = cc_cdecl_set | (cc & cc_this_call);
1720 if (get_method_additional_properties(method_type) & mtp_property_private &&
1721 ia32_cg_config.optimize_cc) {
1722 /* set the fast calling conventions (allowing up to 3) */
1723 cc = SET_FASTCALL(cc) | 3;
1727 /* we have to pop the shadow parameter ourself for compound calls */
1728 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1729 && !(cc & cc_reg_param)) {
1730 pop_amount += get_mode_size_bytes(mode_P_data);
1733 n = get_method_n_params(method_type);
1734 for (i = regnum = 0; i < n; i++) {
1736 const arch_register_t *reg = NULL;
1738 tp = get_method_param_type(method_type, i);
1739 mode = get_type_mode(tp);
1741 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1744 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1747 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1748 * movl has a shorter opcode than mov[sz][bw]l */
1749 ir_mode *load_mode = mode;
1752 unsigned size = get_mode_size_bytes(mode);
1754 if (cc & cc_callee_clear_stk) {
1755 pop_amount += (size + 3U) & ~3U;
1758 if (size < 4) load_mode = mode_Iu;
1761 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1765 be_abi_call_set_pop(abi, pop_amount);
1767 /* set return registers */
1768 n = get_method_n_ress(method_type);
1770 assert(n <= 2 && "more than two results not supported");
1772 /* In case of 64bit returns, we will have two 32bit values */
1774 tp = get_method_res_type(method_type, 0);
1775 mode = get_type_mode(tp);
1777 assert(!mode_is_float(mode) && "two FP results not supported");
1779 tp = get_method_res_type(method_type, 1);
1780 mode = get_type_mode(tp);
1782 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1784 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1785 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1788 const arch_register_t *reg;
1790 tp = get_method_res_type(method_type, 0);
1791 assert(is_atomic_type(tp));
1792 mode = get_type_mode(tp);
1794 reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
1796 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1801 * Returns the necessary byte alignment for storing a register of given class.
1803 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1805 ir_mode *mode = arch_register_class_mode(cls);
1806 int bytes = get_mode_size_bytes(mode);
1808 if (mode_is_float(mode) && bytes > 8)
1814 * Return irp irgs in the desired order.
1816 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
1823 static void ia32_mark_remat(ir_node *node)
1825 if (is_ia32_irn(node)) {
1826 set_ia32_is_remat(node);
1831 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1833 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1838 ir_relation relation;
1843 cmp_l = get_Cmp_left(sel);
1844 cmp_r = get_Cmp_right(sel);
1845 if (!mode_is_float(get_irn_mode(cmp_l)))
1848 /* check for min/max. They're defined as (C-Semantik):
1849 * min(a, b) = a < b ? a : b
1850 * or min(a, b) = a <= b ? a : b
1851 * max(a, b) = a > b ? a : b
1852 * or max(a, b) = a >= b ? a : b
1853 * (Note we only handle float min/max here)
1855 relation = get_Cmp_relation(sel);
1857 case ir_relation_greater_equal:
1858 case ir_relation_greater:
1860 if (cmp_l == mux_true && cmp_r == mux_false)
1863 case ir_relation_less_equal:
1864 case ir_relation_less:
1866 if (cmp_l == mux_true && cmp_r == mux_false)
1869 case ir_relation_unordered_greater_equal:
1870 case ir_relation_unordered_greater:
1872 if (cmp_l == mux_false && cmp_r == mux_true)
1875 case ir_relation_unordered_less_equal:
1876 case ir_relation_unordered_less:
1878 if (cmp_l == mux_false && cmp_r == mux_true)
1889 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1891 ir_mode *mode = get_irn_mode(mux_true);
1894 if (!mode_is_int(mode) && !mode_is_reference(mode)
1898 if (is_Const(mux_true) && is_Const(mux_false)) {
1899 /* we can create a set plus up two 3 instructions for any combination
1907 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1912 if (!mode_is_float(get_irn_mode(mux_true)))
1915 return is_Const(mux_true) && is_Const(mux_false);
1918 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1925 ir_relation relation;
1930 mode = get_irn_mode(mux_true);
1931 if (mode_is_signed(mode) || mode_is_float(mode))
1934 relation = get_Cmp_relation(sel);
1935 cmp_left = get_Cmp_left(sel);
1936 cmp_right = get_Cmp_right(sel);
1938 /* "move" zero constant to false input */
1939 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1940 ir_node *tmp = mux_false;
1941 mux_false = mux_true;
1943 relation = get_negated_relation(relation);
1945 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1947 if (!is_Sub(mux_true))
1949 sub_left = get_Sub_left(mux_true);
1950 sub_right = get_Sub_right(mux_true);
1952 /* Mux(a >=u b, 0, a-b) */
1953 if ((relation & ir_relation_greater)
1954 && sub_left == cmp_left && sub_right == cmp_right)
1956 /* Mux(a <=u b, 0, b-a) */
1957 if ((relation & ir_relation_less)
1958 && sub_left == cmp_right && sub_right == cmp_left)
1964 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1969 /* we can handle Set for all modes and compares */
1970 if (mux_is_set(sel, mux_true, mux_false))
1972 /* SSE has own min/max operations */
1973 if (ia32_cg_config.use_sse2
1974 && mux_is_float_min_max(sel, mux_true, mux_false))
1976 /* we can handle Mux(?, Const[f], Const[f]) */
1977 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1978 #ifdef FIRM_GRGEN_BE
1979 /* well, some code selectors can't handle it */
1980 if (be_transformer != TRANSFORMER_PBQP
1981 || be_transformer != TRANSFORMER_RAND)
1988 /* no support for 64bit inputs to cmov */
1989 mode = get_irn_mode(mux_true);
1990 if (get_mode_size_bits(mode) > 32)
1992 /* we can handle Abs for all modes and compares (except 64bit) */
1993 if (be_mux_is_abs(sel, mux_true, mux_false) != 0)
1995 /* we can't handle MuxF yet */
1996 if (mode_is_float(mode))
1999 if (mux_is_doz(sel, mux_true, mux_false))
2002 /* Check Cmp before the node */
2004 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
2006 /* we can't handle 64bit compares */
2007 if (get_mode_size_bits(cmp_mode) > 32)
2010 /* we can't handle float compares */
2011 if (mode_is_float(cmp_mode))
2015 /* did we disable cmov generation? */
2016 if (!ia32_cg_config.use_cmov)
2019 /* we can use a cmov */
2023 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2027 /* we already added all our simple flags to the flags modifier list in
2028 * init, so this flag we don't know. */
2029 return ASM_CONSTRAINT_FLAG_INVALID;
2032 static int ia32_is_valid_clobber(const char *clobber)
2034 return ia32_get_clobber_register(clobber) != NULL;
2037 static ir_node *ia32_create_set(ir_node *cond)
2039 /* ia32-set function produces 8-bit results which have to be converted */
2040 ir_node *set = ir_create_mux_set(cond, mode_Bu);
2041 ir_node *block = get_nodes_block(set);
2042 return new_r_Conv(block, set, mode_Iu);
2045 static void ia32_lower_for_target(void)
2047 size_t i, n_irgs = get_irp_n_irgs();
2048 lower_mode_b_config_t lower_mode_b_config = {
2049 mode_Iu, /* lowered mode */
2051 0, /* don't lower direct compares */
2053 lower_params_t params = {
2054 4, /* def_ptr_alignment */
2055 LF_COMPOUND_RETURN | LF_RETURN_HIDDEN, /* flags */
2056 ADD_HIDDEN_ALWAYS_IN_FRONT, /* hidden_params */
2057 NULL, /* find pointer type */
2058 NULL, /* ret_compound_in_regs */
2061 /* perform doubleword lowering */
2062 lwrdw_param_t lower_dw_params = {
2063 1, /* little endian */
2064 64, /* doubleword size */
2065 ia32_create_intrinsic_fkt,
2069 /* lower compound param handling */
2070 lower_calls_with_compounds(¶ms);
2072 lower_dw_ops(&lower_dw_params);
2074 for (i = 0; i < n_irgs; ++i) {
2075 ir_graph *irg = get_irp_irg(i);
2076 /* lower for mode_b stuff */
2077 ir_lower_mode_b(irg, &lower_mode_b_config);
2078 /* break up switches with wide ranges */
2079 lower_switch(irg, 256, true);
2084 * Create the trampoline code.
2086 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2088 ir_graph *irg = get_irn_irg(block);
2089 ir_node *p = trampoline;
2090 ir_mode *mode = get_irn_mode(p);
2094 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
2095 mem = new_r_Proj(st, mode_M, pn_Store_M);
2096 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
2097 st = new_r_Store(block, mem, p, env, cons_none);
2098 mem = new_r_Proj(st, mode_M, pn_Store_M);
2099 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
2101 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
2102 mem = new_r_Proj(st, mode_M, pn_Store_M);
2103 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
2104 st = new_r_Store(block, mem, p, callee, cons_none);
2105 mem = new_r_Proj(st, mode_M, pn_Store_M);
2106 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
2112 * Returns the libFirm configuration parameter for this backend.
2114 static const backend_params *ia32_get_libfirm_params(void)
2116 static const ir_settings_arch_dep_t ad = {
2117 1, /* also use subs */
2118 4, /* maximum shifts */
2119 63, /* maximum shift amount */
2120 ia32_evaluate_insn, /* evaluate the instruction sequence */
2122 1, /* allow Mulhs */
2123 1, /* allow Mulus */
2124 32, /* Mulh allowed up to 32 bit */
2126 static backend_params p = {
2127 1, /* support inline assembly */
2128 1, /* support Rotl nodes */
2129 0, /* little endian */
2130 NULL, /* will be set later */
2131 ia32_is_mux_allowed,
2132 NULL, /* float arithmetic mode, will be set below */
2133 12, /* size of trampoline code */
2134 4, /* alignment of trampoline code */
2135 ia32_create_trampoline_fkt,
2136 4 /* alignment of stack parameter */
2139 ia32_setup_cg_config();
2141 /* doesn't really belong here, but this is the earliest place the backend
2143 init_asm_constraints();
2146 if (! ia32_cg_config.use_sse2)
2147 p.mode_float_arithmetic = mode_E;
2151 static const lc_opt_enum_int_items_t gas_items[] = {
2152 { "elf", OBJECT_FILE_FORMAT_ELF },
2153 { "mingw", OBJECT_FILE_FORMAT_COFF },
2154 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2158 static lc_opt_enum_int_var_t gas_var = {
2159 (int*) &be_gas_object_file_format, gas_items
2162 #ifdef FIRM_GRGEN_BE
2163 static const lc_opt_enum_int_items_t transformer_items[] = {
2164 { "default", TRANSFORMER_DEFAULT },
2165 { "pbqp", TRANSFORMER_PBQP },
2166 { "random", TRANSFORMER_RAND },
2170 static lc_opt_enum_int_var_t transformer_var = {
2171 (int*)&be_transformer, transformer_items
2175 static const lc_opt_table_entry_t ia32_options[] = {
2176 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2177 #ifdef FIRM_GRGEN_BE
2178 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2180 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2181 &ia32_isa_template.base.stack_alignment),
2182 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2186 const arch_isa_if_t ia32_isa_if = {
2188 ia32_lower_for_target,
2190 ia32_handle_intrinsics,
2191 ia32_get_reg_class_for_mode,
2193 ia32_get_reg_class_alignment,
2194 ia32_get_libfirm_params,
2197 ia32_parse_asm_constraint,
2198 ia32_is_valid_clobber,
2201 ia32_get_pic_base, /* return node used as base in pic code addresses */
2202 ia32_before_abi, /* before abi introduce hook */
2204 ia32_before_ra, /* before register allocation hook */
2205 ia32_after_ra, /* after register allocation hook */
2206 ia32_finish, /* called before codegen */
2207 ia32_emit, /* emit && done */
2210 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
2211 void be_init_arch_ia32(void)
2213 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2214 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2216 lc_opt_add_table(ia32_grp, ia32_options);
2217 be_register_isa_if("ia32", &ia32_isa_if);
2219 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2221 ia32_init_emitter();
2223 ia32_init_optimize();
2224 ia32_init_transform();
2226 ia32_init_architecture();