2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
37 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
57 #include "../benode.h"
58 #include "../belower.h"
59 #include "../besched.h"
62 #include "../beirgmod.h"
63 #include "../be_dbgout.h"
64 #include "../beblocksched.h"
65 #include "../bemachine.h"
66 #include "../bespillslots.h"
67 #include "../bemodule.h"
68 #include "../begnuas.h"
69 #include "../bestate.h"
70 #include "../beflags.h"
71 #include "../betranshlp.h"
72 #include "../belistsched.h"
73 #include "../beabihelper.h"
75 #include "bearch_ia32_t.h"
77 #include "ia32_new_nodes.h"
78 #include "gen_ia32_regalloc_if.h"
79 #include "gen_ia32_machine.h"
80 #include "ia32_common_transform.h"
81 #include "ia32_transform.h"
82 #include "ia32_emitter.h"
83 #include "ia32_optimize.h"
85 #include "ia32_dbg_stat.h"
86 #include "ia32_finish.h"
87 #include "ia32_util.h"
89 #include "ia32_architecture.h"
92 #include "ia32_pbqp_transform.h"
94 transformer_t be_transformer = TRANSFORMER_DEFAULT;
97 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
99 ir_mode *ia32_mode_fpcw = NULL;
101 /** The current omit-fp state */
102 static unsigned ia32_curr_fp_ommitted = 0;
103 static ir_type *omit_fp_between_type = NULL;
104 static ir_type *between_type = NULL;
105 static ir_entity *old_bp_ent = NULL;
106 static ir_entity *ret_addr_ent = NULL;
107 static ir_entity *omit_fp_ret_addr_ent = NULL;
110 * The environment for the intrinsic mapping.
112 static ia32_intrinsic_env_t intrinsic_env = {
114 NULL, /* the irg, these entities belong to */
115 NULL, /* entity for __divdi3 library call */
116 NULL, /* entity for __moddi3 library call */
117 NULL, /* entity for __udivdi3 library call */
118 NULL, /* entity for __umoddi3 library call */
122 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
125 * Used to create per-graph unique pseudo nodes.
127 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
128 create_const_node_func func,
129 const arch_register_t* reg)
131 ir_node *block, *res;
136 block = get_irg_start_block(irg);
137 res = func(NULL, block);
138 arch_set_irn_register(res, reg);
144 /* Creates the unique per irg GP NoReg node. */
145 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
147 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
148 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
149 &ia32_registers[REG_GP_NOREG]);
152 ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
154 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
155 return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
156 &ia32_registers[REG_VFP_NOREG]);
159 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
161 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
162 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
163 &ia32_registers[REG_XMM_NOREG]);
166 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
168 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
169 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
170 &ia32_registers[REG_FPCW]);
175 * Returns the admissible noreg register node for input register pos of node irn.
177 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
179 ir_graph *irg = get_irn_irg(irn);
180 const arch_register_req_t *req = arch_get_register_req(irn, pos);
182 assert(req != NULL && "Missing register requirements");
183 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
184 return ia32_new_NoReg_gp(irg);
186 if (ia32_cg_config.use_sse2) {
187 return ia32_new_NoReg_xmm(irg);
189 return ia32_new_NoReg_vfp(irg);
193 static arch_irn_class_t ia32_classify(const ir_node *irn)
195 arch_irn_class_t classification = arch_irn_class_none;
197 assert(is_ia32_irn(irn));
199 if (is_ia32_is_reload(irn))
200 classification |= arch_irn_class_reload;
202 if (is_ia32_is_spill(irn))
203 classification |= arch_irn_class_spill;
205 if (is_ia32_is_remat(irn))
206 classification |= arch_irn_class_remat;
208 return classification;
212 * The IA32 ABI callback object.
215 be_abi_call_flags_bits_t flags; /**< The call flags. */
216 ir_graph *irg; /**< The associated graph. */
219 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
221 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
224 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
226 if (is_be_node(node))
227 be_node_set_frame_entity(node, entity);
229 set_ia32_frame_ent(node, entity);
232 static void ia32_set_frame_offset(ir_node *irn, int bias)
234 if (get_ia32_frame_ent(irn) == NULL)
237 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
238 ir_graph *irg = get_irn_irg(irn);
239 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
240 if (layout->sp_relative) {
241 /* Pop nodes modify the stack pointer before calculating the
242 * destination address, so fix this here
247 add_ia32_am_offs_int(irn, bias);
250 static int ia32_get_sp_bias(const ir_node *node)
252 if (is_ia32_Call(node))
253 return -(int)get_ia32_call_attr_const(node)->pop;
255 if (is_ia32_Push(node))
258 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
265 * Generate the routine prologue.
267 * @param self The callback object.
268 * @param mem A pointer to the mem node. Update this if you define new memory.
269 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
270 * @param stack_bias Points to the current stack bias, can be modified if needed.
272 * @return The register which shall be used as a stack frame base.
274 * All nodes which define registers in @p reg_map must keep @p reg_map current.
276 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
278 ia32_abi_env_t *env = (ia32_abi_env_t*)self;
279 ir_graph *irg = env->irg;
280 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
282 ia32_curr_fp_ommitted = env->flags.try_omit_fp;
283 if (! env->flags.try_omit_fp) {
284 ir_node *bl = get_irg_start_block(env->irg);
285 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
286 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
287 ir_node *noreg = ia32_new_NoReg_gp(irg);
290 /* mark bp register as ignore */
291 be_set_constr_single_reg_out(get_Proj_pred(curr_bp),
292 get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore);
295 push = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
296 arch_irn_add_flags(push, arch_irn_flags_prolog);
297 curr_sp = new_r_Proj(push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
298 *mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
300 /* the push must have SP out register */
301 arch_set_irn_register(curr_sp, arch_env->sp);
303 /* this modifies the stack bias, because we pushed 32bit */
306 /* move esp to ebp */
307 curr_bp = be_new_Copy(arch_env->bp->reg_class, bl, curr_sp);
308 arch_irn_add_flags(curr_bp, arch_irn_flags_prolog);
309 be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
310 arch_register_req_type_ignore);
312 /* beware: the copy must be done before any other sp use */
313 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
314 arch_irn_add_flags(curr_sp, arch_irn_flags_prolog);
315 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
316 arch_register_req_type_produces_sp);
318 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
319 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
328 * Generate the routine epilogue.
329 * @param self The callback object.
330 * @param bl The block for the epilog
331 * @param mem A pointer to the mem node. Update this if you define new memory.
332 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
333 * @return The register which shall be used as a stack frame base.
335 * All nodes which define registers in @p reg_map must keep @p reg_map current.
337 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
339 ia32_abi_env_t *env = (ia32_abi_env_t*)self;
340 const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
341 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
342 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
344 if (env->flags.try_omit_fp) {
345 /* simply remove the stack frame here */
346 curr_sp = be_new_IncSP(arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
347 arch_irn_add_flags(curr_sp, arch_irn_flags_epilog);
349 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
351 if (ia32_cg_config.use_leave) {
355 leave = new_bd_ia32_Leave(NULL, bl, curr_bp);
356 curr_bp = new_r_Proj(leave, mode_bp, pn_ia32_Leave_frame);
357 curr_sp = new_r_Proj(leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
358 arch_irn_add_flags(leave, arch_irn_flags_epilog);
362 /* copy ebp to esp */
363 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], bl, curr_bp);
364 arch_set_irn_register(curr_sp, arch_env->sp);
365 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
366 arch_register_req_type_ignore);
367 arch_irn_add_flags(curr_sp, arch_irn_flags_epilog);
370 pop = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
371 curr_bp = new_r_Proj(pop, mode_bp, pn_ia32_Pop_res);
372 curr_sp = new_r_Proj(pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
373 arch_irn_add_flags(pop, arch_irn_flags_epilog);
375 *mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
377 arch_set_irn_register(curr_sp, arch_env->sp);
378 arch_set_irn_register(curr_bp, arch_env->bp);
381 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
382 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
386 * Initialize the callback object.
387 * @param call The call object.
388 * @param irg The graph with the method.
389 * @return Some pointer. This pointer is passed to all other callback functions as self object.
391 static void *ia32_abi_init(const be_abi_call_t *call, ir_graph *irg)
393 ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
394 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
395 env->flags = fl.bits;
401 * Destroy the callback object.
402 * @param self The callback object.
404 static void ia32_abi_done(void *self)
410 * Build the between type and entities if not already build.
412 static void ia32_build_between_type(void)
414 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
415 if (! between_type) {
416 ir_type *old_bp_type = new_type_primitive(mode_Iu);
417 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
419 between_type = new_type_struct(IDENT("ia32_between_type"));
420 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
421 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
423 set_entity_offset(old_bp_ent, 0);
424 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
425 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
426 set_type_state(between_type, layout_fixed);
428 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
429 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
431 set_entity_offset(omit_fp_ret_addr_ent, 0);
432 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
433 set_type_state(omit_fp_between_type, layout_fixed);
439 * Produces the type which sits between the stack args and the locals on the stack.
440 * it will contain the return address and space to store the old base pointer.
441 * @return The Firm type modeling the ABI between type.
443 static ir_type *ia32_abi_get_between_type(void *self)
445 ia32_abi_env_t *env = (ia32_abi_env_t*)self;
447 ia32_build_between_type();
448 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
452 * Return the stack entity that contains the return address.
454 ir_entity *ia32_get_return_address_entity(void)
456 ia32_build_between_type();
457 return ia32_curr_fp_ommitted ? omit_fp_ret_addr_ent : ret_addr_ent;
461 * Return the stack entity that contains the frame address.
463 ir_entity *ia32_get_frame_address_entity(void)
465 ia32_build_between_type();
466 return ia32_curr_fp_ommitted ? NULL : old_bp_ent;
470 * Get the estimated cycle count for @p irn.
472 * @param self The this pointer.
473 * @param irn The node.
475 * @return The estimated cycle count for this operation
477 static int ia32_get_op_estimated_cost(const ir_node *irn)
480 ia32_op_type_t op_tp;
484 if (!is_ia32_irn(irn))
487 assert(is_ia32_irn(irn));
489 cost = get_ia32_latency(irn);
490 op_tp = get_ia32_op_type(irn);
492 if (is_ia32_CopyB(irn)) {
495 else if (is_ia32_CopyB_i(irn)) {
496 int size = get_ia32_copyb_size(irn);
497 cost = 20 + (int)ceil((4/3) * size);
499 /* in case of address mode operations add additional cycles */
500 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
502 In case of stack access and access to fixed addresses add 5 cycles
503 (we assume they are in cache), other memory operations cost 20
506 if (is_ia32_use_frame(irn) || (
507 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
508 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
520 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
522 * @param irn The original operation
523 * @param i Index of the argument we want the inverse operation to yield
524 * @param inverse struct to be filled with the resulting inverse op
525 * @param obstack The obstack to use for allocation of the returned nodes array
526 * @return The inverse operation or NULL if operation invertible
528 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
539 ir_node *block, *noreg, *nomem;
542 /* we cannot invert non-ia32 irns */
543 if (! is_ia32_irn(irn))
546 /* operand must always be a real operand (not base, index or mem) */
547 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
550 /* we don't invert address mode operations */
551 if (get_ia32_op_type(irn) != ia32_Normal)
554 /* TODO: adjust for new immediates... */
555 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
559 block = get_nodes_block(irn);
560 mode = get_irn_mode(irn);
561 irn_mode = get_irn_mode(irn);
562 noreg = get_irn_n(irn, 0);
563 nomem = new_r_NoMem(irg);
564 dbg = get_irn_dbg_info(irn);
566 /* initialize structure */
567 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
571 switch (get_ia32_irn_opcode(irn)) {
574 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
575 /* we have an add with a const here */
576 /* invers == add with negated const */
577 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
579 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
580 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
581 set_ia32_commutative(inverse->nodes[0]);
583 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
584 /* we have an add with a symconst here */
585 /* invers == sub with const */
586 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
588 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
591 /* normal add: inverse == sub */
592 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
599 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
600 /* we have a sub with a const/symconst here */
601 /* invers == add with this const */
602 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
603 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
604 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
608 if (i == n_ia32_binary_left) {
609 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
612 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
620 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
621 /* xor with const: inverse = xor */
622 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
623 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
624 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
628 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
634 inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
639 inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
644 /* inverse operation not supported */
652 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
654 if (mode_is_float(mode))
661 * Get the mode that should be used for spilling value node
663 static ir_mode *get_spill_mode(const ir_node *node)
665 ir_mode *mode = get_irn_mode(node);
666 return get_spill_mode_mode(mode);
670 * Checks whether an addressmode reload for a node with mode mode is compatible
671 * with a spillslot of mode spill_mode
673 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
675 return !mode_is_float(mode) || mode == spillmode;
679 * Check if irn can load its operand at position i from memory (source addressmode).
680 * @param irn The irn to be checked
681 * @param i The operands position
682 * @return Non-Zero if operand can be loaded
684 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
686 ir_node *op = get_irn_n(irn, i);
687 const ir_mode *mode = get_irn_mode(op);
688 const ir_mode *spillmode = get_spill_mode(op);
690 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
691 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
692 !ia32_is_spillmode_compatible(mode, spillmode) ||
693 is_ia32_use_frame(irn)) /* must not already use frame */
696 switch (get_ia32_am_support(irn)) {
701 if (i != n_ia32_unary_op)
707 case n_ia32_binary_left: {
708 const arch_register_req_t *req;
709 if (!is_ia32_commutative(irn))
712 /* we can't swap left/right for limited registers
713 * (As this (currently) breaks constraint handling copies)
715 req = arch_get_in_register_req(irn, n_ia32_binary_left);
716 if (req->type & arch_register_req_type_limited)
721 case n_ia32_binary_right:
730 panic("Unknown AM type");
733 /* HACK: must not already use "real" memory.
734 * This can happen for Call and Div */
735 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
741 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
745 ir_mode *dest_op_mode;
747 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
749 set_ia32_op_type(irn, ia32_AddrModeS);
751 load_mode = get_irn_mode(get_irn_n(irn, i));
752 dest_op_mode = get_ia32_ls_mode(irn);
753 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
754 set_ia32_ls_mode(irn, load_mode);
756 set_ia32_use_frame(irn);
757 set_ia32_need_stackent(irn);
759 if (i == n_ia32_binary_left &&
760 get_ia32_am_support(irn) == ia32_am_binary &&
761 /* immediates are only allowed on the right side */
762 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
763 ia32_swap_left_right(irn);
764 i = n_ia32_binary_right;
767 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
769 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
770 set_irn_n(irn, n_ia32_mem, spill);
771 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
772 set_ia32_is_reload(irn);
775 static const be_abi_callbacks_t ia32_abi_callbacks = {
778 ia32_abi_get_between_type,
783 /* register allocator interface */
784 static const arch_irn_ops_t ia32_irn_ops = {
786 ia32_get_frame_entity,
787 ia32_set_frame_offset,
790 ia32_get_op_estimated_cost,
791 ia32_possible_memory_operand,
792 ia32_perform_memory_operand,
795 static ir_entity *mcount = NULL;
796 static int gprof = 0;
798 static void ia32_before_abi(ir_graph *irg)
801 if (mcount == NULL) {
802 ir_type *tp = new_type_method(0, 0);
803 ident *id = new_id_from_str("mcount");
804 mcount = new_entity(get_glob_type(), id, tp);
805 /* FIXME: enter the right ld_ident here */
806 set_entity_ld_ident(mcount, get_entity_ident(mcount));
807 set_entity_visibility(mcount, ir_visibility_external);
809 instrument_initcall(irg, mcount);
814 * Transforms the standard firm graph into
817 static void ia32_prepare_graph(ir_graph *irg)
819 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
822 switch (be_transformer) {
823 case TRANSFORMER_DEFAULT:
824 /* transform remaining nodes into assembler instructions */
825 ia32_transform_graph(irg);
828 case TRANSFORMER_PBQP:
829 case TRANSFORMER_RAND:
830 /* transform nodes into assembler instructions by PBQP magic */
831 ia32_transform_graph_by_pbqp(irg);
835 panic("invalid transformer");
838 ia32_transform_graph(irg);
841 /* do local optimizations (mainly CSE) */
842 optimize_graph_df(irg);
845 dump_ir_graph(irg, "transformed");
847 /* optimize address mode */
848 ia32_optimize_graph(irg);
850 /* do code placement, to optimize the position of constants */
854 dump_ir_graph(irg, "place");
857 ir_node *ia32_turn_back_am(ir_node *node)
859 dbg_info *dbgi = get_irn_dbg_info(node);
860 ir_graph *irg = get_irn_irg(node);
861 ir_node *block = get_nodes_block(node);
862 ir_node *base = get_irn_n(node, n_ia32_base);
863 ir_node *index = get_irn_n(node, n_ia32_index);
864 ir_node *mem = get_irn_n(node, n_ia32_mem);
867 ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
868 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
870 ia32_copy_am_attrs(load, node);
871 if (is_ia32_is_reload(node))
872 set_ia32_is_reload(load);
873 set_irn_n(node, n_ia32_mem, new_r_NoMem(irg));
875 switch (get_ia32_am_support(node)) {
877 set_irn_n(node, n_ia32_unary_op, load_res);
881 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
882 set_irn_n(node, n_ia32_binary_left, load_res);
884 set_irn_n(node, n_ia32_binary_right, load_res);
889 panic("Unknown AM type");
891 noreg = ia32_new_NoReg_gp(current_ir_graph);
892 set_irn_n(node, n_ia32_base, noreg);
893 set_irn_n(node, n_ia32_index, noreg);
894 set_ia32_am_offs_int(node, 0);
895 set_ia32_am_sc(node, NULL);
896 set_ia32_am_scale(node, 0);
897 clear_ia32_am_sc_sign(node);
899 /* rewire mem-proj */
900 if (get_irn_mode(node) == mode_T) {
901 const ir_edge_t *edge;
902 foreach_out_edge(node, edge) {
903 ir_node *out = get_edge_src_irn(edge);
904 if (get_irn_mode(out) == mode_M) {
905 set_Proj_pred(out, load);
906 set_Proj_proj(out, pn_ia32_Load_M);
912 set_ia32_op_type(node, ia32_Normal);
913 if (sched_is_scheduled(node))
914 sched_add_before(node, load);
919 static ir_node *flags_remat(ir_node *node, ir_node *after)
921 /* we should turn back source address mode when rematerializing nodes */
926 if (is_Block(after)) {
929 block = get_nodes_block(after);
932 type = get_ia32_op_type(node);
935 ia32_turn_back_am(node);
939 /* TODO implement this later... */
940 panic("found DestAM with flag user %+F this should not happen", node);
943 default: assert(type == ia32_Normal); break;
946 copy = exact_copy(node);
947 set_nodes_block(copy, block);
948 sched_add_after(after, copy);
954 * Called before the register allocator.
956 static void ia32_before_ra(ir_graph *irg)
958 /* setup fpu rounding modes */
959 ia32_setup_fpu_mode(irg);
962 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
965 be_add_missing_keeps(irg);
970 * Transforms a be_Reload into a ia32 Load.
972 static void transform_to_Load(ir_node *node)
974 ir_graph *irg = get_irn_irg(node);
975 dbg_info *dbg = get_irn_dbg_info(node);
976 ir_node *block = get_nodes_block(node);
977 ir_entity *ent = be_get_frame_entity(node);
978 ir_mode *mode = get_irn_mode(node);
979 ir_mode *spillmode = get_spill_mode(node);
980 ir_node *noreg = ia32_new_NoReg_gp(irg);
981 ir_node *sched_point = NULL;
982 ir_node *ptr = get_irg_frame(irg);
983 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
984 ir_node *new_op, *proj;
985 const arch_register_t *reg;
987 if (sched_is_scheduled(node)) {
988 sched_point = sched_prev(node);
991 if (mode_is_float(spillmode)) {
992 if (ia32_cg_config.use_sse2)
993 new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
995 new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
997 else if (get_mode_size_bits(spillmode) == 128) {
998 /* Reload 128 bit SSE registers */
999 new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
1002 new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
1004 set_ia32_op_type(new_op, ia32_AddrModeS);
1005 set_ia32_ls_mode(new_op, spillmode);
1006 set_ia32_frame_ent(new_op, ent);
1007 set_ia32_use_frame(new_op);
1008 set_ia32_is_reload(new_op);
1010 DBG_OPT_RELOAD2LD(node, new_op);
1012 proj = new_rd_Proj(dbg, new_op, mode, pn_ia32_Load_res);
1015 sched_add_after(sched_point, new_op);
1019 /* copy the register from the old node to the new Load */
1020 reg = arch_get_irn_register(node);
1021 arch_set_irn_register(proj, reg);
1023 SET_IA32_ORIG_NODE(new_op, node);
1025 exchange(node, proj);
1029 * Transforms a be_Spill node into a ia32 Store.
1031 static void transform_to_Store(ir_node *node)
1033 ir_graph *irg = get_irn_irg(node);
1034 dbg_info *dbg = get_irn_dbg_info(node);
1035 ir_node *block = get_nodes_block(node);
1036 ir_entity *ent = be_get_frame_entity(node);
1037 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1038 ir_mode *mode = get_spill_mode(spillval);
1039 ir_node *noreg = ia32_new_NoReg_gp(irg);
1040 ir_node *nomem = new_r_NoMem(irg);
1041 ir_node *ptr = get_irg_frame(irg);
1042 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1044 ir_node *sched_point = NULL;
1046 if (sched_is_scheduled(node)) {
1047 sched_point = sched_prev(node);
1050 if (mode_is_float(mode)) {
1051 if (ia32_cg_config.use_sse2)
1052 store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
1054 store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
1055 } else if (get_mode_size_bits(mode) == 128) {
1056 /* Spill 128 bit SSE registers */
1057 store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
1058 } else if (get_mode_size_bits(mode) == 8) {
1059 store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
1061 store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
1064 set_ia32_op_type(store, ia32_AddrModeD);
1065 set_ia32_ls_mode(store, mode);
1066 set_ia32_frame_ent(store, ent);
1067 set_ia32_use_frame(store);
1068 set_ia32_is_spill(store);
1069 SET_IA32_ORIG_NODE(store, node);
1070 DBG_OPT_SPILL2ST(node, store);
1073 sched_add_after(sched_point, store);
1077 exchange(node, store);
1080 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
1082 dbg_info *dbg = get_irn_dbg_info(node);
1083 ir_node *block = get_nodes_block(node);
1084 ir_graph *irg = get_irn_irg(node);
1085 ir_node *noreg = ia32_new_NoReg_gp(irg);
1086 ir_node *frame = get_irg_frame(irg);
1088 ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
1090 set_ia32_frame_ent(push, ent);
1091 set_ia32_use_frame(push);
1092 set_ia32_op_type(push, ia32_AddrModeS);
1093 set_ia32_ls_mode(push, mode_Is);
1094 set_ia32_is_spill(push);
1096 sched_add_before(schedpoint, push);
1100 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
1102 dbg_info *dbg = get_irn_dbg_info(node);
1103 ir_node *block = get_nodes_block(node);
1104 ir_graph *irg = get_irn_irg(node);
1105 ir_node *noreg = ia32_new_NoReg_gp(irg);
1106 ir_node *frame = get_irg_frame(irg);
1108 ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_r_NoMem(irg), sp);
1110 set_ia32_frame_ent(pop, ent);
1111 set_ia32_use_frame(pop);
1112 set_ia32_op_type(pop, ia32_AddrModeD);
1113 set_ia32_ls_mode(pop, mode_Is);
1114 set_ia32_is_reload(pop);
1116 sched_add_before(schedpoint, pop);
1121 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1123 dbg_info *dbg = get_irn_dbg_info(node);
1124 ir_mode *spmode = mode_Iu;
1125 const arch_register_t *spreg = &ia32_registers[REG_ESP];
1128 sp = new_rd_Proj(dbg, pred, spmode, pos);
1129 arch_set_irn_register(sp, spreg);
1135 * Transform MemPerm, currently we do this the ugly way and produce
1136 * push/pop into/from memory cascades. This is possible without using
1139 static void transform_MemPerm(ir_node *node)
1141 ir_node *block = get_nodes_block(node);
1142 ir_graph *irg = get_irn_irg(node);
1143 ir_node *sp = be_abi_get_ignore_irn(be_get_irg_abi(irg), &ia32_registers[REG_ESP]);
1144 int arity = be_get_MemPerm_entity_arity(node);
1145 ir_node **pops = ALLOCAN(ir_node*, arity);
1149 const ir_edge_t *edge;
1150 const ir_edge_t *next;
1153 for (i = 0; i < arity; ++i) {
1154 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1155 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1156 ir_type *enttype = get_entity_type(inent);
1157 unsigned entsize = get_type_size_bytes(enttype);
1158 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1159 ir_node *mem = get_irn_n(node, i + 1);
1162 /* work around cases where entities have different sizes */
1163 if (entsize2 < entsize)
1165 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1167 push = create_push(node, node, sp, mem, inent);
1168 sp = create_spproj(node, push, pn_ia32_Push_stack);
1170 /* add another push after the first one */
1171 push = create_push(node, node, sp, mem, inent);
1172 add_ia32_am_offs_int(push, 4);
1173 sp = create_spproj(node, push, pn_ia32_Push_stack);
1176 set_irn_n(node, i, new_r_Bad(irg));
1180 for (i = arity - 1; i >= 0; --i) {
1181 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1182 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1183 ir_type *enttype = get_entity_type(outent);
1184 unsigned entsize = get_type_size_bytes(enttype);
1185 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1188 /* work around cases where entities have different sizes */
1189 if (entsize2 < entsize)
1191 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1193 pop = create_pop(node, node, sp, outent);
1194 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1196 add_ia32_am_offs_int(pop, 4);
1198 /* add another pop after the first one */
1199 pop = create_pop(node, node, sp, outent);
1200 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1207 keep = be_new_Keep(block, 1, in);
1208 sched_add_before(node, keep);
1210 /* exchange memprojs */
1211 foreach_out_edge_safe(node, edge, next) {
1212 ir_node *proj = get_edge_src_irn(edge);
1213 int p = get_Proj_proj(proj);
1217 set_Proj_pred(proj, pops[p]);
1218 set_Proj_proj(proj, pn_ia32_Pop_M);
1221 /* remove memperm */
1222 arity = get_irn_arity(node);
1223 for (i = 0; i < arity; ++i) {
1224 set_irn_n(node, i, new_r_Bad(irg));
1230 * Block-Walker: Calls the transform functions Spill and Reload.
1232 static void ia32_after_ra_walker(ir_node *block, void *env)
1234 ir_node *node, *prev;
1237 /* beware: the schedule is changed here */
1238 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1239 prev = sched_prev(node);
1241 if (be_is_Reload(node)) {
1242 transform_to_Load(node);
1243 } else if (be_is_Spill(node)) {
1244 transform_to_Store(node);
1245 } else if (be_is_MemPerm(node)) {
1246 transform_MemPerm(node);
1252 * Collects nodes that need frame entities assigned.
1254 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1256 be_fec_env_t *env = (be_fec_env_t*)data;
1257 const ir_mode *mode;
1260 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1261 mode = get_spill_mode_mode(get_irn_mode(node));
1262 align = get_mode_size_bytes(mode);
1263 } else if (is_ia32_irn(node) &&
1264 get_ia32_frame_ent(node) == NULL &&
1265 is_ia32_use_frame(node)) {
1266 if (is_ia32_need_stackent(node))
1269 switch (get_ia32_irn_opcode(node)) {
1271 case iro_ia32_Load: {
1272 const ia32_attr_t *attr = get_ia32_attr_const(node);
1274 if (attr->data.need_32bit_stackent) {
1276 } else if (attr->data.need_64bit_stackent) {
1279 mode = get_ia32_ls_mode(node);
1280 if (is_ia32_is_reload(node))
1281 mode = get_spill_mode_mode(mode);
1283 align = get_mode_size_bytes(mode);
1287 case iro_ia32_vfild:
1289 case iro_ia32_xLoad: {
1290 mode = get_ia32_ls_mode(node);
1295 case iro_ia32_FldCW: {
1296 /* although 2 byte would be enough 4 byte performs best */
1304 panic("unexpected frame user while collection frame entity nodes");
1306 case iro_ia32_FnstCW:
1307 case iro_ia32_Store8Bit:
1308 case iro_ia32_Store:
1311 case iro_ia32_vfist:
1312 case iro_ia32_vfisttp:
1314 case iro_ia32_xStore:
1315 case iro_ia32_xStoreSimple:
1322 be_node_needs_frame_entity(env, node, mode, align);
1326 * We transform Spill and Reload here. This needs to be done before
1327 * stack biasing otherwise we would miss the corrected offset for these nodes.
1329 static void ia32_after_ra(ir_graph *irg)
1331 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1333 /* create and coalesce frame entities */
1334 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1335 be_assign_entities(fec_env, ia32_set_frame_entity);
1336 be_free_frame_entity_coalescer(fec_env);
1338 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1342 * Last touchups for the graph before emit: x87 simulation to replace the
1343 * virtual with real x87 instructions, creating a block schedule and peephole
1346 static void ia32_finish(ir_graph *irg)
1348 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1350 ia32_finish_irg(irg);
1352 /* we might have to rewrite x87 virtual registers */
1353 if (irg_data->do_x87_sim) {
1354 ia32_x87_simulate_graph(irg);
1357 /* do peephole optimisations */
1358 ia32_peephole_optimization(irg);
1360 /* create block schedule, this also removes empty blocks which might
1361 * produce critical edges */
1362 irg_data->blk_sched = be_create_block_schedule(irg);
1366 * Emits the code, closes the output file and frees
1367 * the code generator interface.
1369 static void ia32_emit(ir_graph *irg)
1371 if (ia32_cg_config.emit_machcode) {
1372 ia32_gen_binary_routine(irg);
1374 ia32_gen_routine(irg);
1379 * Returns the node representing the PIC base.
1381 static ir_node *ia32_get_pic_base(ir_graph *irg)
1383 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1385 ir_node *get_eip = irg_data->get_eip;
1386 if (get_eip != NULL)
1389 block = get_irg_start_block(irg);
1390 get_eip = new_bd_ia32_GetEIP(NULL, block);
1391 irg_data->get_eip = get_eip;
1397 * Initializes a IA32 code generator.
1399 static void ia32_init_graph(ir_graph *irg)
1401 struct obstack *obst = be_get_be_obst(irg);
1402 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1404 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1407 /* Linux gprof implementation needs base pointer */
1408 be_get_irg_options(irg)->omit_fp = 0;
1411 be_birg_from_irg(irg)->isa_link = irg_data;
1416 * Set output modes for GCC
1418 static const tarval_mode_info mo_integer = {
1425 * set the tarval output mode of all integer modes to decimal
1427 static void set_tarval_output_modes(void)
1431 for (i = get_irp_n_modes(); i > 0;) {
1432 ir_mode *mode = get_irp_mode(--i);
1434 if (mode_is_int(mode))
1435 set_tarval_mode_output_option(mode, &mo_integer);
1439 extern const arch_isa_if_t ia32_isa_if;
1442 * The template that generates a new ISA object.
1443 * Note that this template can be changed by command line
1446 static ia32_isa_t ia32_isa_template = {
1448 &ia32_isa_if, /* isa interface implementation */
1453 &ia32_registers[REG_ESP], /* stack pointer register */
1454 &ia32_registers[REG_EBP], /* base pointer register */
1455 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1456 -1, /* stack direction */
1457 2, /* power of two stack alignment, 2^2 == 4 */
1458 NULL, /* main environment */
1459 7, /* costs for a spill instruction */
1460 5, /* costs for a reload instruction */
1461 false, /* no custom abi handling */
1465 NULL, /* abstract machine */
1468 static void init_asm_constraints(void)
1470 be_init_default_asm_constraint_flags();
1472 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1473 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1474 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1475 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1476 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1477 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1478 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1479 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1480 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1481 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1482 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1483 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1484 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1485 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1486 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1487 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1488 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1489 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1490 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1491 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1493 /* no support for autodecrement/autoincrement */
1494 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1495 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1496 /* no float consts */
1497 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1498 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1499 /* makes no sense on x86 */
1500 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1501 /* no support for sse consts yet */
1502 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1503 /* no support for x87 consts yet */
1504 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1505 /* no support for mmx registers yet */
1506 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1507 /* not available in 32bit mode */
1508 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1509 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1511 /* no code yet to determine register class needed... */
1512 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1516 * Initializes the backend ISA.
1518 static arch_env_t *ia32_init(FILE *file_handle)
1520 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1523 set_tarval_output_modes();
1525 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1527 if (ia32_mode_fpcw == NULL) {
1528 ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1531 ia32_register_init();
1532 ia32_create_opcodes(&ia32_irn_ops);
1534 be_emit_init(file_handle);
1535 isa->types = pmap_create();
1536 isa->tv_ent = pmap_create();
1537 isa->cpu = ia32_init_machine_description();
1539 /* enter the ISA object into the intrinsic environment */
1540 intrinsic_env.isa = isa;
1542 /* emit asm includes */
1543 n = get_irp_n_asms();
1544 for (i = 0; i < n; ++i) {
1545 be_emit_cstring("#APP\n");
1546 be_emit_ident(get_irp_asm(i));
1547 be_emit_cstring("\n#NO_APP\n");
1550 /* needed for the debug support */
1551 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1552 be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
1553 be_emit_write_line();
1561 * Closes the output file and frees the ISA structure.
1563 static void ia32_done(void *self)
1565 ia32_isa_t *isa = (ia32_isa_t*)self;
1567 /* emit now all global declarations */
1568 be_gas_emit_decls(isa->base.main_env);
1570 pmap_destroy(isa->tv_ent);
1571 pmap_destroy(isa->types);
1580 * Get the register class which shall be used to store a value of a given mode.
1581 * @param self The this pointer.
1582 * @param mode The mode in question.
1583 * @return A register class which can hold values of the given mode.
1585 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1587 if (mode_is_float(mode)) {
1588 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1591 return &ia32_reg_classes[CLASS_ia32_gp];
1595 * Returns the register for parameter nr.
1597 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1598 const ir_mode *mode)
1600 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1601 &ia32_registers[REG_ECX],
1602 &ia32_registers[REG_EDX],
1605 static const unsigned MAXNUM_GPREG_ARGS = 3;
1607 static const arch_register_t *gpreg_param_reg_regparam[] = {
1608 &ia32_registers[REG_EAX],
1609 &ia32_registers[REG_EDX],
1610 &ia32_registers[REG_ECX]
1613 static const arch_register_t *gpreg_param_reg_this[] = {
1614 &ia32_registers[REG_ECX],
1619 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1620 &ia32_registers[REG_XMM0],
1621 &ia32_registers[REG_XMM1],
1622 &ia32_registers[REG_XMM2],
1623 &ia32_registers[REG_XMM3],
1624 &ia32_registers[REG_XMM4],
1625 &ia32_registers[REG_XMM5],
1626 &ia32_registers[REG_XMM6],
1627 &ia32_registers[REG_XMM7]
1630 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1631 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1633 static const unsigned MAXNUM_SSE_ARGS = 8;
1635 if ((cc & cc_this_call) && nr == 0)
1636 return gpreg_param_reg_this[0];
1638 if (! (cc & cc_reg_param))
1641 if (mode_is_float(mode)) {
1642 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1644 if (nr >= MAXNUM_SSE_ARGS)
1647 if (cc & cc_this_call) {
1648 return fpreg_sse_param_reg_this[nr];
1650 return fpreg_sse_param_reg_std[nr];
1651 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1652 unsigned num_regparam;
1654 if (get_mode_size_bits(mode) > 32)
1657 if (nr >= MAXNUM_GPREG_ARGS)
1660 if (cc & cc_this_call) {
1661 return gpreg_param_reg_this[nr];
1663 num_regparam = cc & ~cc_bits;
1664 if (num_regparam == 0) {
1665 /* default fastcall */
1666 return gpreg_param_reg_fastcall[nr];
1668 if (nr < num_regparam)
1669 return gpreg_param_reg_regparam[nr];
1673 panic("unknown argument mode");
1677 * Get the ABI restrictions for procedure calls.
1678 * @param self The this pointer.
1679 * @param method_type The type of the method (procedure) in question.
1680 * @param abi The abi object to be modified
1682 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1690 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1694 /* set abi flags for calls */
1695 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1696 call_flags.bits.store_args_sequential = 0;
1697 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1698 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1699 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1701 /* set parameter passing style */
1702 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1704 cc = get_method_calling_convention(method_type);
1705 if (get_method_variadicity(method_type) == variadicity_variadic) {
1706 /* pass all parameters of a variadic function on the stack */
1707 cc = cc_cdecl_set | (cc & cc_this_call);
1709 if (get_method_additional_properties(method_type) & mtp_property_private &&
1710 ia32_cg_config.optimize_cc) {
1711 /* set the fast calling conventions (allowing up to 3) */
1712 cc = SET_FASTCALL(cc) | 3;
1716 /* we have to pop the shadow parameter ourself for compound calls */
1717 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1718 && !(cc & cc_reg_param)) {
1719 pop_amount += get_mode_size_bytes(mode_P_data);
1722 n = get_method_n_params(method_type);
1723 for (i = regnum = 0; i < n; i++) {
1725 const arch_register_t *reg = NULL;
1727 tp = get_method_param_type(method_type, i);
1728 mode = get_type_mode(tp);
1730 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1733 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1736 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1737 * movl has a shorter opcode than mov[sz][bw]l */
1738 ir_mode *load_mode = mode;
1741 unsigned size = get_mode_size_bytes(mode);
1743 if (cc & cc_callee_clear_stk) {
1744 pop_amount += (size + 3U) & ~3U;
1747 if (size < 4) load_mode = mode_Iu;
1750 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1754 be_abi_call_set_pop(abi, pop_amount);
1756 /* set return registers */
1757 n = get_method_n_ress(method_type);
1759 assert(n <= 2 && "more than two results not supported");
1761 /* In case of 64bit returns, we will have two 32bit values */
1763 tp = get_method_res_type(method_type, 0);
1764 mode = get_type_mode(tp);
1766 assert(!mode_is_float(mode) && "two FP results not supported");
1768 tp = get_method_res_type(method_type, 1);
1769 mode = get_type_mode(tp);
1771 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1773 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1774 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1777 const arch_register_t *reg;
1779 tp = get_method_res_type(method_type, 0);
1780 assert(is_atomic_type(tp));
1781 mode = get_type_mode(tp);
1783 reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
1785 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1790 * Returns the necessary byte alignment for storing a register of given class.
1792 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1794 ir_mode *mode = arch_register_class_mode(cls);
1795 int bytes = get_mode_size_bytes(mode);
1797 if (mode_is_float(mode) && bytes > 8)
1803 * Return irp irgs in the desired order.
1805 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
1812 static void ia32_mark_remat(ir_node *node)
1814 if (is_ia32_irn(node)) {
1815 set_ia32_is_remat(node);
1820 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1822 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1827 ir_relation relation;
1832 cmp_l = get_Cmp_left(sel);
1833 cmp_r = get_Cmp_right(sel);
1834 if (!mode_is_float(get_irn_mode(cmp_l)))
1837 /* check for min/max. They're defined as (C-Semantik):
1838 * min(a, b) = a < b ? a : b
1839 * or min(a, b) = a <= b ? a : b
1840 * max(a, b) = a > b ? a : b
1841 * or max(a, b) = a >= b ? a : b
1842 * (Note we only handle float min/max here)
1844 relation = get_Cmp_relation(sel);
1846 case ir_relation_greater_equal:
1847 case ir_relation_greater:
1849 if (cmp_l == mux_true && cmp_r == mux_false)
1852 case ir_relation_less_equal:
1853 case ir_relation_less:
1855 if (cmp_l == mux_true && cmp_r == mux_false)
1858 case ir_relation_unordered_greater_equal:
1859 case ir_relation_unordered_greater:
1861 if (cmp_l == mux_false && cmp_r == mux_true)
1864 case ir_relation_unordered_less_equal:
1865 case ir_relation_unordered_less:
1867 if (cmp_l == mux_false && cmp_r == mux_true)
1878 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1880 ir_mode *mode = get_irn_mode(mux_true);
1883 if (!mode_is_int(mode) && !mode_is_reference(mode)
1887 if (is_Const(mux_true) && is_Const(mux_false)) {
1888 /* we can create a set plus up two 3 instructions for any combination
1896 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1901 if (!mode_is_float(get_irn_mode(mux_true)))
1904 return is_Const(mux_true) && is_Const(mux_false);
1907 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1914 ir_relation relation;
1919 mode = get_irn_mode(mux_true);
1920 if (mode_is_signed(mode) || mode_is_float(mode))
1923 relation = get_Cmp_relation(sel);
1924 cmp_left = get_Cmp_left(sel);
1925 cmp_right = get_Cmp_right(sel);
1927 /* "move" zero constant to false input */
1928 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1929 ir_node *tmp = mux_false;
1930 mux_false = mux_true;
1932 relation = get_negated_relation(relation);
1934 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1936 if (!is_Sub(mux_true))
1938 sub_left = get_Sub_left(mux_true);
1939 sub_right = get_Sub_right(mux_true);
1941 /* Mux(a >=u b, 0, a-b) */
1942 if ((relation & ir_relation_greater)
1943 && sub_left == cmp_left && sub_right == cmp_right)
1945 /* Mux(a <=u b, 0, b-a) */
1946 if ((relation & ir_relation_less)
1947 && sub_left == cmp_right && sub_right == cmp_left)
1953 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1958 /* we can handle Set for all modes and compares */
1959 if (mux_is_set(sel, mux_true, mux_false))
1961 /* SSE has own min/max operations */
1962 if (ia32_cg_config.use_sse2
1963 && mux_is_float_min_max(sel, mux_true, mux_false))
1965 /* we can handle Mux(?, Const[f], Const[f]) */
1966 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1967 #ifdef FIRM_GRGEN_BE
1968 /* well, some code selectors can't handle it */
1969 if (be_transformer != TRANSFORMER_PBQP
1970 || be_transformer != TRANSFORMER_RAND)
1977 /* no support for 64bit inputs to cmov */
1978 mode = get_irn_mode(mux_true);
1979 if (get_mode_size_bits(mode) > 32)
1981 /* we can handle Abs for all modes and compares (except 64bit) */
1982 if (be_mux_is_abs(sel, mux_true, mux_false) != 0)
1984 /* we can't handle MuxF yet */
1985 if (mode_is_float(mode))
1988 if (mux_is_doz(sel, mux_true, mux_false))
1991 /* Check Cmp before the node */
1993 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1995 /* we can't handle 64bit compares */
1996 if (get_mode_size_bits(cmp_mode) > 32)
1999 /* we can't handle float compares */
2000 if (mode_is_float(cmp_mode))
2004 /* did we disable cmov generation? */
2005 if (!ia32_cg_config.use_cmov)
2008 /* we can use a cmov */
2012 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2016 /* we already added all our simple flags to the flags modifier list in
2017 * init, so this flag we don't know. */
2018 return ASM_CONSTRAINT_FLAG_INVALID;
2021 static int ia32_is_valid_clobber(const char *clobber)
2023 return ia32_get_clobber_register(clobber) != NULL;
2026 static ir_node *ia32_create_set(ir_node *cond)
2028 /* ia32-set function produces 8-bit results which have to be converted */
2029 ir_node *set = ir_create_mux_set(cond, mode_Bu);
2030 ir_node *block = get_nodes_block(set);
2031 return new_r_Conv(block, set, mode_Iu);
2034 static void ia32_lower_for_target(void)
2036 size_t i, n_irgs = get_irp_n_irgs();
2037 lower_mode_b_config_t lower_mode_b_config = {
2038 mode_Iu, /* lowered mode */
2040 0, /* don't lower direct compares */
2042 lower_params_t params = {
2043 4, /* def_ptr_alignment */
2044 LF_COMPOUND_RETURN | LF_RETURN_HIDDEN, /* flags */
2045 ADD_HIDDEN_ALWAYS_IN_FRONT, /* hidden_params */
2046 NULL, /* find pointer type */
2047 NULL, /* ret_compound_in_regs */
2050 /* perform doubleword lowering */
2051 lwrdw_param_t lower_dw_params = {
2052 1, /* little endian */
2053 64, /* doubleword size */
2054 ia32_create_intrinsic_fkt,
2058 /* lower compound param handling */
2059 lower_calls_with_compounds(¶ms);
2061 lower_dw_ops(&lower_dw_params);
2063 for (i = 0; i < n_irgs; ++i) {
2064 ir_graph *irg = get_irp_irg(i);
2065 /* lower for mode_b stuff */
2066 ir_lower_mode_b(irg, &lower_mode_b_config);
2067 /* break up switches with wide ranges */
2068 lower_switch(irg, 256, true);
2073 * Create the trampoline code.
2075 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2077 ir_graph *irg = get_irn_irg(block);
2078 ir_node *p = trampoline;
2079 ir_mode *mode = get_irn_mode(p);
2083 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
2084 mem = new_r_Proj(st, mode_M, pn_Store_M);
2085 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
2086 st = new_r_Store(block, mem, p, env, cons_none);
2087 mem = new_r_Proj(st, mode_M, pn_Store_M);
2088 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
2090 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
2091 mem = new_r_Proj(st, mode_M, pn_Store_M);
2092 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
2093 st = new_r_Store(block, mem, p, callee, cons_none);
2094 mem = new_r_Proj(st, mode_M, pn_Store_M);
2095 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
2101 * Returns the libFirm configuration parameter for this backend.
2103 static const backend_params *ia32_get_libfirm_params(void)
2105 static const ir_settings_arch_dep_t ad = {
2106 1, /* also use subs */
2107 4, /* maximum shifts */
2108 63, /* maximum shift amount */
2109 ia32_evaluate_insn, /* evaluate the instruction sequence */
2111 1, /* allow Mulhs */
2112 1, /* allow Mulus */
2113 32, /* Mulh allowed up to 32 bit */
2115 static backend_params p = {
2116 1, /* support inline assembly */
2117 1, /* support Rotl nodes */
2118 0, /* little endian */
2119 NULL, /* will be set later */
2120 ia32_is_mux_allowed,
2121 NULL, /* float arithmetic mode, will be set below */
2122 12, /* size of trampoline code */
2123 4, /* alignment of trampoline code */
2124 ia32_create_trampoline_fkt,
2125 4 /* alignment of stack parameter */
2128 ia32_setup_cg_config();
2130 /* doesn't really belong here, but this is the earliest place the backend
2132 init_asm_constraints();
2135 if (! ia32_cg_config.use_sse2)
2136 p.mode_float_arithmetic = mode_E;
2140 static const lc_opt_enum_int_items_t gas_items[] = {
2141 { "elf", OBJECT_FILE_FORMAT_ELF },
2142 { "mingw", OBJECT_FILE_FORMAT_COFF },
2143 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2147 static lc_opt_enum_int_var_t gas_var = {
2148 (int*) &be_gas_object_file_format, gas_items
2151 #ifdef FIRM_GRGEN_BE
2152 static const lc_opt_enum_int_items_t transformer_items[] = {
2153 { "default", TRANSFORMER_DEFAULT },
2154 { "pbqp", TRANSFORMER_PBQP },
2155 { "random", TRANSFORMER_RAND },
2159 static lc_opt_enum_int_var_t transformer_var = {
2160 (int*)&be_transformer, transformer_items
2164 static const lc_opt_table_entry_t ia32_options[] = {
2165 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2166 #ifdef FIRM_GRGEN_BE
2167 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2169 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2170 &ia32_isa_template.base.stack_alignment),
2171 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2175 const arch_isa_if_t ia32_isa_if = {
2177 ia32_lower_for_target,
2179 ia32_handle_intrinsics,
2180 ia32_get_reg_class_for_mode,
2182 ia32_get_reg_class_alignment,
2183 ia32_get_libfirm_params,
2186 ia32_parse_asm_constraint,
2187 ia32_is_valid_clobber,
2190 ia32_get_pic_base, /* return node used as base in pic code addresses */
2191 ia32_before_abi, /* before abi introduce hook */
2193 ia32_before_ra, /* before register allocation hook */
2194 ia32_after_ra, /* after register allocation hook */
2195 ia32_finish, /* called before codegen */
2196 ia32_emit, /* emit && done */
2199 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
2200 void be_init_arch_ia32(void)
2202 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2203 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2205 lc_opt_add_table(ia32_grp, ia32_options);
2206 be_register_isa_if("ia32", &ia32_isa_if);
2208 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2210 ia32_init_emitter();
2212 ia32_init_optimize();
2213 ia32_init_transform();
2215 ia32_init_architecture();