4 * @author Sebastian Hack
6 * Backend node support.
8 * This file provdies Perm, Copy, Spill and Reload nodes.
10 * Copyright (C) 2005 Universitaet Karlsruhe
11 * Released under the GPL
26 #include "bitfiddle.h"
36 #include "besched_t.h"
41 #define OUT_POS(x) (-((x) + 1))
43 /* Sometimes we want to put const nodes into get_irn_generic_attr ... */
44 #define get_irn_attr(irn) get_irn_generic_attr((ir_node *) (irn))
46 static unsigned be_node_tag = FOURCC('B', 'E', 'N', 'O');
49 typedef enum _node_kind_t {
60 be_req_kind_old_limited,
61 be_req_kind_negate_old_limited,
62 be_req_kind_single_reg
66 arch_register_req_t req;
68 arch_irn_flags_t flags;
71 void (*old_limited)(void *ptr, bitset_t *bs);
72 void *old_limited_env;
75 const arch_register_t *single_reg;
80 const arch_register_t *reg;
87 be_reg_data_t *reg_data;
91 be_node_attr_t node_attr;
92 int offset; /**< The offset by which the stack shall be increased/decreased. */
93 be_stack_dir_t dir; /**< The direction in which the stack shall be modified (along or in the other direction). */
97 be_node_attr_t node_attr;
103 be_frame_attr_t frame_attr;
104 ir_node *spill_ctx; /**< The node in whose context this spill was introduced. */
117 ir_op *op_be_RegParams;
118 ir_op *op_be_StackParam;
119 ir_op *op_be_FrameAddr;
120 ir_op *op_be_FrameLoad;
121 ir_op *op_be_FrameStore;
123 static int beo_base = -1;
125 static const ir_op_ops be_node_op_ops;
127 #define N irop_flag_none
128 #define L irop_flag_labeled
129 #define C irop_flag_commutative
130 #define X irop_flag_cfopcode
131 #define I irop_flag_ip_cfopcode
132 #define F irop_flag_fragile
133 #define Y irop_flag_forking
134 #define H irop_flag_highlevel
135 #define c irop_flag_constlike
136 #define K irop_flag_keep
138 void be_node_init(void) {
139 static int inited = 0;
146 /* Acquire all needed opcodes. */
147 beo_base = get_next_ir_opcodes(beo_Last - 1);
149 op_be_Spill = new_ir_op(beo_base + beo_Spill, "Spill", op_pin_state_mem_pinned, N, oparity_unary, 0, sizeof(be_spill_attr_t), &be_node_op_ops);
150 op_be_Reload = new_ir_op(beo_base + beo_Reload, "Reload", op_pin_state_mem_pinned, N, oparity_zero, 0, sizeof(be_node_attr_t), &be_node_op_ops);
151 op_be_Perm = new_ir_op(beo_base + beo_Perm, "Perm", op_pin_state_pinned, N, oparity_variable, 0, sizeof(be_node_attr_t), &be_node_op_ops);
152 op_be_Copy = new_ir_op(beo_base + beo_Copy, "Copy", op_pin_state_floats, N, oparity_unary, 0, sizeof(be_node_attr_t), &be_node_op_ops);
153 op_be_Keep = new_ir_op(beo_base + beo_Keep, "Keep", op_pin_state_pinned, K, oparity_variable, 0, sizeof(be_node_attr_t), &be_node_op_ops);
154 op_be_Call = new_ir_op(beo_base + beo_Call, "Call", op_pin_state_pinned, N, oparity_variable, 0, sizeof(be_node_attr_t), &be_node_op_ops);
155 op_be_Return = new_ir_op(beo_base + beo_Return, "Return", op_pin_state_pinned, X, oparity_variable, 0, sizeof(be_node_attr_t), &be_node_op_ops);
156 op_be_AddSP = new_ir_op(beo_base + beo_AddSP, "AddSP", op_pin_state_pinned, N, oparity_unary, 0, sizeof(be_stack_attr_t), &be_node_op_ops);
157 op_be_SetSP = new_ir_op(beo_base + beo_SetSP, "SetSP", op_pin_state_pinned, N, oparity_binary, 0, sizeof(be_stack_attr_t), &be_node_op_ops);
158 op_be_IncSP = new_ir_op(beo_base + beo_IncSP, "IncSP", op_pin_state_pinned, N, oparity_binary, 0, sizeof(be_stack_attr_t), &be_node_op_ops);
159 op_be_RegParams = new_ir_op(beo_base + beo_RegParams, "RegParams", op_pin_state_pinned, N, oparity_zero, 0, sizeof(be_node_attr_t), &be_node_op_ops);
160 op_be_StackParam = new_ir_op(beo_base + beo_StackParam, "StackParam", op_pin_state_pinned, N, oparity_unary, 0, sizeof(be_frame_attr_t), &be_node_op_ops);
161 op_be_FrameAddr = new_ir_op(beo_base + beo_FrameAddr, "FrameAddr", op_pin_state_pinned, N, oparity_binary, 0, sizeof(be_frame_attr_t), &be_node_op_ops);
162 op_be_FrameLoad = new_ir_op(beo_base + beo_FrameLoad, "FrameLoad", op_pin_state_pinned, N, oparity_any, 0, sizeof(be_frame_attr_t), &be_node_op_ops);
163 op_be_FrameStore = new_ir_op(beo_base + beo_FrameStore, "FrameStore", op_pin_state_pinned, N, oparity_any, 0, sizeof(be_frame_attr_t), &be_node_op_ops);
165 set_op_tag(op_be_Spill, &be_node_tag);
166 set_op_tag(op_be_Reload, &be_node_tag);
167 set_op_tag(op_be_Perm, &be_node_tag);
168 set_op_tag(op_be_Copy, &be_node_tag);
169 set_op_tag(op_be_Keep, &be_node_tag);
170 set_op_tag(op_be_Call, &be_node_tag);
171 set_op_tag(op_be_Return, &be_node_tag);
172 set_op_tag(op_be_AddSP, &be_node_tag);
173 set_op_tag(op_be_SetSP, &be_node_tag);
174 set_op_tag(op_be_IncSP, &be_node_tag);
175 set_op_tag(op_be_RegParams, &be_node_tag);
176 set_op_tag(op_be_StackParam, &be_node_tag);
177 set_op_tag(op_be_FrameLoad, &be_node_tag);
178 set_op_tag(op_be_FrameStore, &be_node_tag);
179 set_op_tag(op_be_FrameAddr, &be_node_tag);
182 static void *init_node_attr(ir_node* irn, int max_reg_data)
184 ir_graph *irg = get_irn_irg(irn);
185 be_node_attr_t *a = get_irn_attr(irn);
187 a->max_reg_data = max_reg_data;
190 if(max_reg_data > 0) {
193 a->reg_data = NEW_ARR_D(be_reg_data_t, get_irg_obstack(irg), max_reg_data);
194 memset(a->reg_data, 0, max_reg_data * sizeof(a->reg_data[0]));
195 for(i = 0; i < max_reg_data; ++i) {
196 a->reg_data[i].req.req.cls = NULL;
197 a->reg_data[i].req.req.type = arch_register_req_type_none;
204 static INLINE int is_be_node(const ir_node *irn)
206 return get_op_tag(get_irn_op(irn)) == &be_node_tag;
209 be_opcode_t be_get_irn_opcode(const ir_node *irn)
211 return is_be_node(irn) ? get_irn_opcode(irn) - beo_base : beo_NoBeOp;
214 static int redir_proj(const ir_node **node, int pos)
216 const ir_node *n = *node;
219 assert(pos == -1 && "Illegal pos for a Proj");
220 *node = get_Proj_pred(n);
221 return get_Proj_proj(n);
228 be_node_set_irn_reg(const void *_self, ir_node *irn, const arch_register_t *reg)
233 out_pos = redir_proj((const ir_node **) &irn, -1);
234 a = get_irn_attr(irn);
236 assert(is_be_node(irn));
237 assert(out_pos < a->max_reg_data && "position too high");
238 a->reg_data[out_pos].reg = reg;
242 ir_node *be_new_Spill(const arch_register_class_t *cls, const arch_register_class_t *cls_frame, ir_graph *irg, ir_node *bl, ir_node *frame, ir_node *to_spill, ir_node *ctx)
250 res = new_ir_node(NULL, irg, bl, op_be_Spill, mode_M, 2, in);
251 a = init_node_attr(res, 2);
252 a->frame_attr.ent = NULL;
253 a->frame_attr.offset = 0;
256 be_node_set_reg_class(res, 0, cls_frame);
257 be_node_set_reg_class(res, 1, cls);
261 ir_node *be_new_Reload(const arch_register_class_t *cls, const arch_register_class_t *cls_frame, ir_graph *irg, ir_node *bl, ir_node *frame, ir_node *mem, ir_mode *mode)
268 res = new_ir_node(NULL, irg, bl, op_be_Reload, mode, 2, in);
269 init_node_attr(res, 2);
270 be_node_set_reg_class(res, 0, cls_frame);
271 be_node_set_reg_class(res, -1, cls);
275 ir_node *(be_get_Reload_mem)(const ir_node *irn)
277 assert(be_is_Reload(irn));
278 return get_irn_n(irn, 1);
281 ir_node *be_new_Perm(const arch_register_class_t *cls, ir_graph *irg, ir_node *bl, int n, ir_node *in[])
284 ir_node *irn = new_ir_node(NULL, irg, bl, op_be_Perm, mode_T, n, in);
285 init_node_attr(irn, n);
286 for(i = 0; i < n; ++i) {
287 be_node_set_reg_class(irn, i, cls);
288 be_node_set_reg_class(irn, OUT_POS(i), cls);
294 ir_node *be_new_Copy(const arch_register_class_t *cls, ir_graph *irg, ir_node *bl, ir_node *op)
300 res = new_ir_node(NULL, irg, bl, op_be_Copy, get_irn_mode(op), 1, in);
301 init_node_attr(res, 1);
302 be_node_set_reg_class(res, 0, cls);
303 be_node_set_reg_class(res, OUT_POS(0), cls);
307 ir_node *be_new_Keep(const arch_register_class_t *cls, ir_graph *irg, ir_node *bl, int n, ir_node *in[])
312 irn = new_ir_node(NULL, irg, bl, op_be_Keep, mode_ANY, n, in);
313 init_node_attr(irn, n);
314 for(i = 0; i < n; ++i) {
315 be_node_set_reg_class(irn, i, cls);
321 ir_node *be_new_Call(ir_graph *irg, ir_node *bl, ir_node *mem, ir_node *sp, ir_node *ptr, int n_outs, int n, ir_node *in[])
327 real_in = malloc(sizeof(real_in[0]) * (real_n));
332 memcpy(&real_in[3], in, n * sizeof(in[0]));
334 irn = new_ir_node(NULL, irg, bl, op_be_Call, mode_T, real_n, real_in);
335 init_node_attr(irn, (n_outs > real_n ? n_outs : real_n));
339 ir_node *be_new_Return(ir_graph *irg, ir_node *bl, int n, ir_node *in[])
341 ir_node *irn = new_ir_node(NULL, irg, bl, op_be_Return, mode_X, n, in);
342 init_node_attr(irn, n);
347 ir_node *be_new_IncSP(const arch_register_t *sp, ir_graph *irg, ir_node *bl, ir_node *old_sp, ir_node *mem, unsigned offset, be_stack_dir_t dir)
355 irn = new_ir_node(NULL, irg, bl, op_be_IncSP, sp->reg_class->mode, 2, in);
356 a = init_node_attr(irn, 1);
360 be_node_set_flags(irn, -1, arch_irn_flags_ignore);
362 /* Set output constraint to stack register. */
363 be_node_set_reg_class(irn, 0, sp->reg_class);
364 be_set_constr_single_reg(irn, -1, sp);
365 be_node_set_irn_reg(NULL, irn, sp);
370 ir_node *be_new_AddSP(const arch_register_t *sp, ir_graph *irg, ir_node *bl, ir_node *old_sp, ir_node *op)
378 irn = new_ir_node(NULL, irg, bl, op_be_AddSP, sp->reg_class->mode, 2, in);
379 a = init_node_attr(irn, 1);
381 be_node_set_flags(irn, OUT_POS(0), arch_irn_flags_ignore);
383 /* Set output constraint to stack register. */
384 be_set_constr_single_reg(irn, OUT_POS(0), sp);
385 be_node_set_irn_reg(NULL, irn, sp);
390 ir_node *be_new_SetSP(const arch_register_t *sp, ir_graph *irg, ir_node *bl, ir_node *old_sp, ir_node *op, ir_node *mem)
399 irn = new_ir_node(NULL, irg, bl, op_be_SetSP, get_irn_mode(old_sp), 3, in);
400 a = init_node_attr(irn, 3);
402 be_node_set_flags(irn, OUT_POS(0), arch_irn_flags_ignore);
404 /* Set output constraint to stack register. */
405 be_set_constr_single_reg(irn, OUT_POS(0), sp);
406 be_node_set_reg_class(irn, 1, sp->reg_class);
407 be_node_set_reg_class(irn, 2, sp->reg_class);
408 be_node_set_irn_reg(NULL, irn, sp);
413 ir_node *be_new_StackParam(const arch_register_class_t *cls, const arch_register_class_t *cls_frame, ir_graph *irg, ir_node *bl, ir_mode *mode, ir_node *frame_pointer, entity *ent)
419 in[0] = frame_pointer;
420 irn = new_ir_node(NULL, irg, bl, op_be_StackParam, mode, 1, in);
421 a = init_node_attr(irn, 1);
424 be_node_set_reg_class(irn, 0, cls_frame);
425 be_node_set_reg_class(irn, OUT_POS(0), cls);
429 ir_node *be_new_RegParams(ir_graph *irg, ir_node *bl, int n_outs)
434 irn = new_ir_node(NULL, irg, bl, op_be_RegParams, mode_T, 0, in);
435 init_node_attr(irn, n_outs);
439 ir_node *be_new_FrameLoad(const arch_register_class_t *cls_frame, const arch_register_class_t *cls_data,
440 ir_graph *irg, ir_node *bl, ir_node *mem, ir_node *frame, entity *ent)
448 irn = new_ir_node(NULL, irg, bl, op_be_FrameLoad, mode_T, 2, in);
449 a = init_node_attr(irn, 3);
452 be_node_set_reg_class(irn, 1, cls_frame);
453 be_node_set_reg_class(irn, OUT_POS(pn_Load_res), cls_data);
457 ir_node *be_new_FrameStore(const arch_register_class_t *cls_frame, const arch_register_class_t *cls_data,
458 ir_graph *irg, ir_node *bl, ir_node *mem, ir_node *frame, ir_node *data, entity *ent)
467 irn = new_ir_node(NULL, irg, bl, op_be_FrameStore, mode_T, 3, in);
468 a = init_node_attr(irn, 3);
471 be_node_set_reg_class(irn, 1, cls_frame);
472 be_node_set_reg_class(irn, 2, cls_data);
476 ir_node *be_new_FrameAddr(const arch_register_class_t *cls_frame, ir_graph *irg, ir_node *bl, ir_node *frame, entity *ent)
483 irn = new_ir_node(NULL, irg, bl, op_be_FrameAddr, get_irn_mode(frame), 1, in);
484 a = init_node_attr(irn, 1);
487 be_node_set_reg_class(irn, 0, cls_frame);
488 be_node_set_reg_class(irn, OUT_POS(0), cls_frame);
492 int be_is_Spill (const ir_node *irn) { return be_get_irn_opcode(irn) == beo_Spill ; }
493 int be_is_Reload (const ir_node *irn) { return be_get_irn_opcode(irn) == beo_Reload ; }
494 int be_is_Copy (const ir_node *irn) { return be_get_irn_opcode(irn) == beo_Copy ; }
495 int be_is_Perm (const ir_node *irn) { return be_get_irn_opcode(irn) == beo_Perm ; }
496 int be_is_Keep (const ir_node *irn) { return be_get_irn_opcode(irn) == beo_Keep ; }
497 int be_is_Call (const ir_node *irn) { return be_get_irn_opcode(irn) == beo_Call ; }
498 int be_is_Return (const ir_node *irn) { return be_get_irn_opcode(irn) == beo_Return ; }
499 int be_is_IncSP (const ir_node *irn) { return be_get_irn_opcode(irn) == beo_IncSP ; }
500 int be_is_SetSP (const ir_node *irn) { return be_get_irn_opcode(irn) == beo_SetSP ; }
501 int be_is_AddSP (const ir_node *irn) { return be_get_irn_opcode(irn) == beo_AddSP ; }
502 int be_is_RegParams (const ir_node *irn) { return be_get_irn_opcode(irn) == beo_RegParams ; }
503 int be_is_StackParam (const ir_node *irn) { return be_get_irn_opcode(irn) == beo_StackParam ; }
504 int be_is_FrameAddr (const ir_node *irn) { return be_get_irn_opcode(irn) == beo_FrameAddr ; }
505 int be_is_FrameLoad (const ir_node *irn) { return be_get_irn_opcode(irn) == beo_FrameLoad ; }
506 int be_is_FrameStore (const ir_node *irn) { return be_get_irn_opcode(irn) == beo_FrameStore ; }
508 int be_has_frame_entity(const ir_node *irn)
510 switch(be_get_irn_opcode(irn)) {
522 entity *be_get_frame_entity(const ir_node *irn)
524 if(be_has_frame_entity(irn)) {
525 be_frame_attr_t *a = get_irn_attr(irn);
529 else if(be_get_irn_opcode(irn) == beo_Reload)
530 return be_get_spill_entity(irn);
535 static void be_limited(void *data, bitset_t *bs)
537 be_req_t *req = data;
540 case be_req_kind_negate_old_limited:
541 case be_req_kind_old_limited:
542 req->x.old_limited.old_limited(req->x.old_limited.old_limited_env, bs);
543 if(req->kind == be_req_kind_negate_old_limited)
546 case be_req_kind_single_reg:
547 bitset_clear_all(bs);
548 bitset_set(bs, req->x.single_reg->index);
553 static INLINE be_req_t *get_req(ir_node *irn, int pos)
555 int idx = pos < 0 ? -(pos + 1) : pos;
556 be_node_attr_t *a = get_irn_attr(irn);
557 be_reg_data_t *rd = &a->reg_data[idx];
558 be_req_t *r = pos < 0 ? &rd->req : &rd->in_req;
560 assert(is_be_node(irn));
561 assert(!(pos >= 0) || pos < get_irn_arity(irn));
562 assert(!(pos < 0) || -(pos + 1) <= a->max_reg_data);
567 void be_set_constr_single_reg(ir_node *irn, int pos, const arch_register_t *reg)
569 be_req_t *r = get_req(irn, pos);
571 r->kind = be_req_kind_single_reg;
572 r->x.single_reg = reg;
573 r->req.limited = be_limited;
574 r->req.limited_env = r;
575 r->req.type = arch_register_req_type_limited;
576 r->req.cls = reg->reg_class;
579 void be_set_constr_limited(ir_node *irn, int pos, const arch_register_req_t *req)
581 be_req_t *r = get_req(irn, pos);
583 assert(arch_register_req_is(req, limited));
585 r->kind = be_req_kind_old_limited;
586 r->req.limited = be_limited;
587 r->req.limited_env = r;
588 r->req.type = arch_register_req_type_limited;
589 r->req.cls = req->cls;
591 r->x.old_limited.old_limited = req->limited;
592 r->x.old_limited.old_limited_env = req->limited_env;
595 void be_node_set_flags(ir_node *irn, int pos, arch_irn_flags_t flags)
597 be_req_t *r = get_req(irn, pos);
601 void be_node_set_reg_class(ir_node *irn, int pos, const arch_register_class_t *cls)
603 be_req_t *r = get_req(irn, pos);
605 if(r->req.type == arch_register_req_type_none)
606 r->req.type = arch_register_req_type_normal;
609 void be_set_IncSP_offset(ir_node *irn, unsigned offset)
611 be_stack_attr_t *a = get_irn_attr(irn);
612 assert(be_is_IncSP(irn));
616 unsigned be_get_IncSP_offset(const ir_node *irn)
618 be_stack_attr_t *a = get_irn_attr(irn);
619 assert(be_is_IncSP(irn));
623 void be_set_IncSP_direction(ir_node *irn, be_stack_dir_t dir)
625 be_stack_attr_t *a = get_irn_attr(irn);
626 assert(be_is_IncSP(irn));
630 be_stack_dir_t be_get_IncSP_direction(const ir_node *irn)
632 be_stack_attr_t *a = get_irn_attr(irn);
633 assert(be_is_IncSP(irn));
637 void be_set_Spill_entity(ir_node *irn, entity *ent)
639 be_spill_attr_t *a = get_irn_attr(irn);
640 assert(be_is_Spill(irn));
641 a->frame_attr.ent = ent;
644 static ir_node *find_a_spill_walker(ir_node *irn, unsigned visited_nr)
646 if(get_irn_visited(irn) < visited_nr) {
647 set_irn_visited(irn, visited_nr);
651 for(i = 0, n = get_irn_arity(irn); i < n; ++i) {
652 ir_node *n = find_a_spill_walker(get_irn_n(irn, i), visited_nr);
658 else if(be_get_irn_opcode(irn) == beo_Spill)
665 ir_node *be_get_Spill_context(const ir_node *irn) {
666 const be_spill_attr_t *a = get_irn_attr(irn);
667 assert(be_is_Spill(irn));
672 * Finds a spill for a reload.
673 * If the reload is directly using the spill, this is simple,
674 * else we perform DFS from the reload (over all PhiMs) and return
675 * the first spill node we find.
677 static INLINE ir_node *find_a_spill(const ir_node *irn)
679 ir_graph *irg = get_irn_irg(irn);
680 unsigned visited_nr = get_irg_visited(irg) + 1;
682 assert(be_is_Reload(irn));
683 set_irg_visited(irg, visited_nr);
684 return find_a_spill_walker(be_get_Reload_mem(irn), visited_nr);
687 entity *be_get_spill_entity(const ir_node *irn)
689 int opc = get_irn_opcode(irn);
691 switch(be_get_irn_opcode(irn)) {
693 return be_get_spill_entity(find_a_spill(irn));
696 be_spill_attr_t *a = get_irn_attr(irn);
697 return a->frame_attr.ent;
700 assert(0 && "Must give spill/reload node");
706 ir_node *be_spill(const arch_env_t *arch_env, ir_node *irn, ir_node *ctx)
708 ir_node *bl = get_nodes_block(irn);
709 ir_graph *irg = get_irn_irg(bl);
710 ir_node *frame = get_irg_frame(irg);
714 const arch_register_class_t *cls = arch_get_irn_reg_class(arch_env, irn, -1);
715 const arch_register_class_t *cls_frame = arch_get_irn_reg_class(arch_env, frame, -1);
717 spill = be_new_Spill(cls, cls_frame, irg, bl, frame, irn, ctx);
720 * search the right insertion point. a spill of a phi cannot be put
721 * directly after the phi, if there are some phis behind the one which
722 * is spilled. Also, a spill of a Proj must be after all Projs of the
725 insert = sched_next(irn);
726 while((is_Phi(insert) || is_Proj(insert)) && !sched_is_end(insert))
727 insert = sched_next(insert);
730 * Here's one special case:
731 * If the spill is in the start block, the spill must be after the frame
732 * pointer is set up. This is checked here and fixed.
734 if(bl == get_irg_start_block(irg))
735 insert = sched_next(frame);
737 sched_add_before(insert, spill);
741 ir_node *be_reload(const arch_env_t *arch_env, const arch_register_class_t *cls, ir_node *reloader, ir_mode *mode, ir_node *spill)
745 ir_node *bl = is_Block(reloader) ? reloader : get_nodes_block(reloader);
746 ir_graph *irg = get_irn_irg(bl);
747 ir_node *frame = get_irg_frame(irg);
748 const arch_register_class_t *cls_frame = arch_get_irn_reg_class(arch_env, frame, -1);
750 assert(be_is_Spill(spill) || (is_Phi(spill) && get_irn_mode(spill) == mode_M));
752 reload = be_new_Reload(cls, cls_frame, irg, bl, frame, spill, mode);
754 sched_add_before(reloader, reload);
758 static void *put_out_reg_req(arch_register_req_t *req, const ir_node *irn, int out_pos)
760 const be_node_attr_t *a = get_irn_attr(irn);
762 if(out_pos < a->max_reg_data)
763 memcpy(req, &a->reg_data[out_pos].req, sizeof(req[0]));
765 req->type = arch_register_req_type_none;
772 static void *put_in_reg_req(arch_register_req_t *req, const ir_node *irn, int pos)
774 const be_node_attr_t *a = get_irn_attr(irn);
775 int n = get_irn_arity(irn);
777 if(pos < get_irn_arity(irn) && pos < a->max_reg_data)
778 memcpy(req, &a->reg_data[pos].in_req, sizeof(req[0]));
780 req->type = arch_register_req_type_none;
787 static const arch_register_req_t *
788 be_node_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos)
793 if(get_irn_mode(irn) == mode_T)
796 out_pos = redir_proj((const ir_node **) &irn, pos);
797 assert(is_be_node(irn));
798 return put_out_reg_req(req, irn, out_pos);
802 return is_be_node(irn) ? put_in_reg_req(req, irn, pos) : NULL;
808 const arch_register_t *
809 be_node_get_irn_reg(const void *_self, const ir_node *irn)
814 out_pos = redir_proj((const ir_node **) &irn, -1);
815 a = get_irn_attr(irn);
817 assert(is_be_node(irn));
818 assert(out_pos < a->max_reg_data && "position too high");
820 return a->reg_data[out_pos].reg;
823 static arch_irn_class_t be_node_classify(const void *_self, const ir_node *irn)
825 redir_proj((const ir_node **) &irn, -1);
827 switch(be_get_irn_opcode(irn)) {
828 #define XXX(a,b) case beo_ ## a: return arch_irn_class_ ## b;
841 static arch_irn_flags_t be_node_get_flags(const void *_self, const ir_node *irn)
846 out_pos = redir_proj((const ir_node **) &irn, -1);
847 a = get_irn_attr(irn);
849 assert(is_be_node(irn));
850 assert(out_pos < a->max_reg_data && "position too high");
852 return a->reg_data[out_pos].req.flags;
855 static entity *be_node_get_frame_entity(const void *self, const ir_node *irn)
857 return be_get_frame_entity(irn);
860 static void be_node_set_frame_offset(const void *self, ir_node *irn, int offset)
862 if(be_has_frame_entity(irn)) {
863 be_frame_attr_t *a = get_irn_attr(irn);
869 static const arch_irn_ops_if_t be_node_irn_ops_if = {
870 be_node_get_irn_reg_req,
875 be_node_get_frame_entity,
876 be_node_set_frame_offset
879 static const arch_irn_ops_t be_node_irn_ops = {
883 const void *be_node_get_arch_ops(const arch_irn_handler_t *self, const ir_node *irn)
885 redir_proj((const ir_node **) &irn, -1);
886 return is_be_node(irn) ? &be_node_irn_ops : NULL;
889 const arch_irn_handler_t be_node_irn_handler = {
894 static void dump_node_req(FILE *f, be_req_t *req)
897 int did_something = 0;
898 const char *suffix = "";
900 if(req->flags != arch_irn_flags_none) {
901 fprintf(f, "flags: ");
902 for(i = arch_irn_flags_none; i <= log2_ceil(arch_irn_flags_last); ++i) {
903 if(req->flags & (1 << i)) {
904 fprintf(f, "%s%s", suffix, arch_irn_flag_str(1 << i));
912 if(req->req.cls != 0) {
915 arch_register_req_format(tmp, sizeof(tmp), &req->req);
916 fprintf(f, "%s", tmp);
924 static void dump_node_reqs(FILE *f, ir_node *irn)
927 be_node_attr_t *a = get_irn_attr(irn);
929 fprintf(f, "registers: \n");
930 for(i = 0; i < a->max_reg_data; ++i) {
931 be_reg_data_t *rd = &a->reg_data[i];
933 fprintf(f, "#%d: %s\n", i, rd->reg->name);
936 fprintf(f, "in requirements\n");
937 for(i = 0; i < a->max_reg_data; ++i) {
938 dump_node_req(f, &a->reg_data[i].in_req);
941 fprintf(f, "\nout requirements\n");
942 for(i = 0; i < a->max_reg_data; ++i) {
943 dump_node_req(f, &a->reg_data[i].req);
947 static int dump_node(ir_node *irn, FILE *f, dump_reason_t reason)
949 be_node_attr_t *at = get_irn_attr(irn);
951 assert(is_be_node(irn));
954 case dump_node_opcode_txt:
955 fprintf(f, get_op_name(get_irn_op(irn)));
957 case dump_node_mode_txt:
958 fprintf(f, get_mode_name(get_irn_mode(irn)));
960 case dump_node_nodeattr_txt:
962 case dump_node_info_txt:
963 dump_node_reqs(f, irn);
965 if(be_has_frame_entity(irn)) {
966 be_frame_attr_t *a = (be_frame_attr_t *) at;
968 ir_fprintf(f, "frame entity: %+F offset %x (%d)\n", a->ent, a->offset, a->offset);
972 switch(be_get_irn_opcode(irn)) {
975 be_spill_attr_t *a = (be_spill_attr_t *) at;
976 ir_fprintf(f, "spill context: %+F\n", a->spill_ctx);
982 be_stack_attr_t *a = (be_stack_attr_t *) at;
983 fprintf(f, "offset: %u\n", a->offset);
984 fprintf(f, "direction: %s\n", a->dir == be_stack_dir_along ? "along" : "against");
995 * Copies the backend specific attributes from old node to new node.
997 static void copy_attr(const ir_node *old_node, ir_node *new_node)
999 be_node_attr_t *old_attr = get_irn_attr(old_node);
1000 be_node_attr_t *new_attr = get_irn_attr(new_node);
1003 assert(is_be_node(old_node));
1004 assert(is_be_node(new_node));
1006 memcpy(new_attr, old_attr, get_op_attr_size(get_irn_op(old_node)));
1007 new_attr->reg_data = NULL;
1009 if(new_attr->max_reg_data > 0) {
1010 new_attr->reg_data = NEW_ARR_D(be_reg_data_t, get_irg_obstack(get_irn_irg(new_node)), new_attr->max_reg_data);
1011 memcpy(new_attr->reg_data, old_attr->reg_data, new_attr->max_reg_data * sizeof(be_reg_data_t));
1013 for(i = 0; i < old_attr->max_reg_data; ++i) {
1016 r = &new_attr->reg_data[i].req;
1017 r->req.limited_env = r;
1019 r = &new_attr->reg_data[i].in_req;
1020 r->req.limited_env = r;
1025 static const ir_op_ops be_node_op_ops = {
1041 pset *nodes_live_at(const arch_env_t *arch_env, const arch_register_class_t *cls, const ir_node *pos, pset *live)
1043 firm_dbg_module_t *dbg = firm_dbg_register("firm.be.node");
1044 const ir_node *bl = is_Block(pos) ? pos : get_nodes_block(pos);
1048 live_foreach(bl, li) {
1049 ir_node *irn = (ir_node *) li->irn;
1050 if(live_is_end(li) && arch_irn_consider_in_reg_alloc(arch_env, cls, irn))
1051 pset_insert_ptr(live, irn);
1054 sched_foreach_reverse(bl, irn) {
1059 * If we encounter the node we want to insert the Perm after,
1060 * exit immediately, so that this node is still live
1065 DBG((dbg, LEVEL_1, "%+F\n", irn));
1066 for(x = pset_first(live); x; x = pset_next(live))
1067 DBG((dbg, LEVEL_1, "\tlive: %+F\n", x));
1069 if(arch_irn_consider_in_reg_alloc(arch_env, cls, irn))
1070 pset_remove_ptr(live, irn);
1072 for(i = 0, n = get_irn_arity(irn); i < n; ++i) {
1073 ir_node *op = get_irn_n(irn, i);
1075 if(arch_irn_consider_in_reg_alloc(arch_env, cls, op))
1076 pset_insert_ptr(live, op);
1083 ir_node *insert_Perm_after(const arch_env_t *arch_env,
1084 const arch_register_class_t *cls,
1085 dom_front_info_t *dom_front,
1088 ir_node *bl = is_Block(pos) ? pos : get_nodes_block(pos);
1089 ir_graph *irg = get_irn_irg(bl);
1090 pset *live = pset_new_ptr_default();
1091 firm_dbg_module_t *dbg = firm_dbg_register("be.node");
1093 ir_node *curr, *irn, *perm, **nodes;
1096 DBG((dbg, LEVEL_1, "Insert Perm after: %+F\n", pos));
1098 if(!nodes_live_at(arch_env, cls, pos, live));
1100 n = pset_count(live);
1105 nodes = malloc(n * sizeof(nodes[0]));
1107 DBG((dbg, LEVEL_1, "live:\n"));
1108 for(irn = pset_first(live), i = 0; irn; irn = pset_next(live), i++) {
1109 DBG((dbg, LEVEL_1, "\t%+F\n", irn));
1113 perm = be_new_Perm(cls, irg, bl, n, nodes);
1114 sched_add_after(pos, perm);
1118 for(i = 0; i < n; ++i) {
1120 ir_node *perm_op = get_irn_n(perm, i);
1121 const arch_register_t *reg = arch_get_irn_register(arch_env, perm_op);
1123 ir_mode *mode = get_irn_mode(perm_op);
1124 ir_node *proj = new_r_Proj(irg, bl, perm, mode, i);
1125 arch_set_irn_register(arch_env, proj, reg);
1127 sched_add_after(curr, proj);
1130 copies[0] = perm_op;
1132 be_ssa_constr(dom_front, 2, copies);