2 * Chordal register allocation.
3 * @author Sebastian Hack
6 * Copyright (C) Universitaet Karlsruhe
7 * Released under the GPL
29 #include "bipartite.h"
32 #include "irgraph_t.h"
33 #include "irprintf_t.h"
43 #include "besched_t.h"
49 #include "bechordal_t.h"
50 #include "bechordal_draw.h"
52 #define DBG_LEVEL SET_LEVEL_0
53 #define DBG_LEVEL_CHECK SET_LEVEL_0
57 #define MAX(x, y) ((x) > (y) ? (x) : (y))
58 #define MIN(x, y) ((x) < (y) ? (x) : (y))
60 #define DUMP_INTERVALS
62 typedef struct _be_chordal_alloc_env_t {
63 be_chordal_env_t *chordal_env;
65 firm_dbg_module_t *constr_dbg; /**< Debug output for the constraint handler. */
66 pset *pre_colored; /**< Set of precolored nodes. */
67 bitset_t *live; /**< A liveness bitset. */
68 bitset_t *colors; /**< The color mask. */
69 bitset_t *in_colors; /**< Colors used by live in values. */
70 bitset_t *ignore_regs; /**< A bitset of all ignore registers in the current class. */
71 int colors_n; /**< The number of colors. */
72 } be_chordal_alloc_env_t;
76 /* Make a fourcc for border checking. */
77 #define BORDER_FOURCC FOURCC('B', 'O', 'R', 'D')
79 static void check_border_list(struct list_head *head)
82 list_for_each_entry(border_t, x, head, list) {
83 assert(x->magic == BORDER_FOURCC);
87 static void check_heads(be_chordal_env_t *env)
90 for(ent = pmap_first(env->border_heads); ent; ent = pmap_next(env->border_heads)) {
91 /* ir_printf("checking border list of block %+F\n", ent->key); */
92 check_border_list(ent->value);
98 * Add an interval border to the list of a block's list
100 * @note You always have to create the use before the def.
101 * @param env The environment.
102 * @param head The list head to enqueue the borders.
103 * @param irn The node (value) the border belongs to.
104 * @param pressure The pressure at this point in time.
105 * @param step A time step for the border.
106 * @param is_def Is the border a use or a def.
107 * @return The created border.
109 static INLINE border_t *border_add(be_chordal_env_t *env, struct list_head *head,
110 ir_node *irn, unsigned step, unsigned pressure,
111 unsigned is_def, unsigned is_real)
118 b = obstack_alloc(&env->obst, sizeof(*b));
120 /* also allocate the def and tie it to the use. */
121 def = obstack_alloc(&env->obst, sizeof(*def));
122 memset(def, 0, sizeof(*def));
127 * Set the link field of the irn to the def.
128 * This strongly relies on the fact, that the use is always
129 * made before the def.
131 set_irn_link(irn, def);
133 b->magic = BORDER_FOURCC;
134 def->magic = BORDER_FOURCC;
138 * If the def is encountered, the use was made and so was the
139 * the def node (see the code above). It was placed into the
140 * link field of the irn, so we can get it there.
143 b = get_irn_link(irn);
145 assert(b && b->magic == BORDER_FOURCC && "Illegal border encountered");
148 b->pressure = pressure;
150 b->is_real = is_real;
153 list_add_tail(&b->list, head);
154 DBG((env->dbg, LEVEL_5, "\t\t%s adding %+F, step: %d\n", is_def ? "def" : "use", irn, step));
161 * Check, if an irn is of the register class currently under processing.
162 * @param env The chordal environment.
163 * @param irn The node.
164 * @return 1, if the node is of that register class, 0 if not.
166 static INLINE int has_reg_class(const be_chordal_env_t *env, const ir_node *irn)
168 // return arch_irn_has_reg_class(env->main_env->arch_env, irn, -1, env->cls);
169 return arch_irn_consider_in_reg_alloc(env->birg->main_env->arch_env, env->cls, irn);
172 #define has_limited_constr(req, irn) \
173 (arch_get_register_req(arch_env, (req), irn, -1) && (req)->type == arch_register_req_type_limited)
175 static int get_next_free_reg(const be_chordal_alloc_env_t *alloc_env, bitset_t *colors)
177 bitset_or(colors, alloc_env->ignore_regs);
178 return bitset_next_clear(colors, 0);
181 typedef struct _operand_t operand_t;
189 arch_register_req_t req;
190 unsigned has_constraints : 1;
199 unsigned in_constraints : 1;
200 unsigned out_constraints : 1;
201 unsigned has_constraints : 1;
202 unsigned pre_colored : 1;
205 #define insn_n_defs(insn) ((insn)->use_start)
206 #define insn_n_uses(insn) ((insn)->n_ops - (insn)->use_start)
208 static insn_t *scan_insn(be_chordal_env_t *env, ir_node *irn, struct obstack *obst)
210 const arch_env_t *arch_env = env->birg->main_env->arch_env;
216 insn = obstack_alloc(obst, sizeof(insn[0]));
217 memset(insn, 0, sizeof(insn[0]));
220 insn->next_insn = sched_next(irn);
221 if(get_irn_mode(irn) == mode_T) {
224 for(p = sched_next(irn); is_Proj(p); p = sched_next(p)) {
225 if(arch_irn_consider_in_reg_alloc(arch_env, env->cls, p)) {
226 arch_get_register_req(arch_env, &o.req, p, -1);
229 o.pos = -(get_Proj_proj(p) + 1);
231 o.has_constraints = arch_register_req_is(&o.req, limited);
232 obstack_grow(obst, &o, sizeof(o));
234 insn->out_constraints |= o.has_constraints;
235 pre_colored += arch_get_irn_register(arch_env, p) != NULL;
242 else if(arch_irn_consider_in_reg_alloc(arch_env, env->cls, irn)) {
243 arch_get_register_req(arch_env, &o.req, irn, -1);
248 o.has_constraints = arch_register_req_is(&o.req, limited);
249 obstack_grow(obst, &o, sizeof(o));
251 insn->out_constraints |= o.has_constraints;
252 pre_colored += arch_get_irn_register(arch_env, irn) != NULL;
255 insn->pre_colored = pre_colored == insn->n_ops && insn->n_ops > 0;
256 insn->use_start = insn->n_ops;
258 for(i = 0, n = get_irn_arity(irn); i < n; ++i) {
259 ir_node *op = get_irn_n(irn, i);
261 if(arch_irn_has_reg_class(arch_env, irn, i, env->cls)) {
262 arch_get_register_req(arch_env, &o.req, irn, i);
267 o.has_constraints = arch_register_req_is(&o.req, limited);
268 obstack_grow(obst, &o, sizeof(o));
270 insn->in_constraints |= o.has_constraints;
274 insn->has_constraints = insn->in_constraints | insn->out_constraints;
275 insn->ops = obstack_finish(obst);
277 /* Compute the admissible registers bitsets. */
278 for(i = 0; i < insn->n_ops; ++i) {
279 operand_t *op = &insn->ops[i];
281 assert(op->req.cls == env->cls);
282 op->regs = bitset_obstack_alloc(obst, env->cls->n_regs);
284 if(arch_register_req_is(&op->req, limited))
285 op->req.limited(op->req.limited_env, op->regs);
287 arch_put_non_ignore_regs(env->birg->main_env->arch_env, env->cls, op->regs);
293 static bitset_t *get_decisive_partner_regs(bitset_t *bs, const operand_t *o1, const operand_t *o2)
298 bitset_copy(bs, o2->regs);
303 bitset_copy(bs, o1->regs);
307 assert(o1->req.cls == o2->req.cls);
309 if(bitset_contains(o1->regs, o2->regs))
310 bitset_copy(bs, o1->regs);
311 else if(bitset_contains(o2->regs, o1->regs))
312 bitset_copy(bs, o2->regs);
319 static void pair_up_operands(const be_chordal_alloc_env_t *alloc_env, insn_t *insn)
321 const be_chordal_env_t *env = alloc_env->chordal_env;
322 const arch_env_t *aenv = env->birg->main_env->arch_env;
323 firm_dbg_module_t *dbg = alloc_env->constr_dbg;
325 int n_uses = insn_n_uses(insn);
326 int n_defs = insn_n_defs(insn);
327 int max_pairs = MIN(n_uses, n_defs);
328 bitset_t *bs = bitset_alloca(env->cls->n_regs);
329 bipartite_t *bp = bipartite_new(n_defs, n_uses);
330 int *pairing = alloca(MAX(n_defs, n_uses) * sizeof(pairing[0]));
335 For each out operand, try to find an in operand which can be assigned the
336 same register as the out operand.
338 for(j = 0; j < insn->use_start; ++j) {
339 operand_t *out_op = &insn->ops[j];
341 /* Try to find an in operand which has ... */
342 for(i = insn->use_start; i < insn->n_ops; ++i) {
343 const operand_t *op = &insn->ops[i];
346 The in operand can only be paired with a def, if the node defining the
347 operand's value does not interfere with the instruction itself. That
348 would mean, that it is live at the instruction, so no result of the instruction
349 can have the same register as the operand.
351 Furthermore, tow operands can be paired, if the admissible registers
352 of one are a subset of the other's. We record the operand whose constraints
353 count in the decisive array.
355 if(!values_interfere(op->irn, op->carrier)) {
356 if(get_decisive_partner_regs(bs, out_op, op))
357 bipartite_add(bp, j, i - insn->use_start);
362 /* Compute the pairing. */
363 bipartite_matching(bp, pairing);
364 for(i = 0; i < insn->use_start; ++i) {
365 int p = pairing[i] + insn->use_start;
367 if(p >= insn->use_start) {
368 insn->ops[i].partner = &insn->ops[p];
369 insn->ops[p].partner = &insn->ops[i];
377 static ir_node *pre_process_constraints(be_chordal_alloc_env_t *alloc_env, insn_t **the_insn)
379 be_chordal_env_t *env = alloc_env->chordal_env;
380 const arch_env_t *aenv = env->birg->main_env->arch_env;
381 firm_dbg_module_t *dbg = alloc_env->constr_dbg;
382 insn_t *insn = *the_insn;
383 ir_node *bl = get_nodes_block(insn->irn);
384 ir_node *copy = NULL;
385 ir_node *perm = NULL;
386 bitset_t *out_constr = bitset_alloca(env->cls->n_regs);
387 bitset_t *bs = bitset_alloca(env->cls->n_regs);
391 assert(insn->has_constraints && "only do this for constrained nodes");
394 Collect all registers that occur in output constraints.
395 This is necessary, since if the insn has one of these as an input constraint
396 and the corresponding operand interferes with the insn, the operand must
399 for(i = 0; i < insn->use_start; ++i) {
400 operand_t *op = &insn->ops[i];
401 if(op->has_constraints)
402 bitset_or(out_constr, op->regs);
406 Now, figure out which input operand must be copied since it has input
407 constraints which are also output constraints.
409 for(i = insn->use_start; i < insn->n_ops; ++i) {
410 operand_t *op = &insn->ops[i];
411 if(op->has_constraints && values_interfere(op->carrier, insn->irn)) {
412 bitset_copy(bs, op->regs);
413 bitset_and(bs, out_constr);
416 The operand (interfering with the node) has input constraints
417 which also occur as output constraints, so insert a copy.
419 if(bitset_popcnt(bs) > 0) {
420 copy = be_new_Copy(op->req.cls, env->irg, bl, op->carrier);
421 insn->ops[i].carrier = copy;
422 sched_add_before(insn->irn, copy);
424 DBG((dbg, LEVEL_2, "adding copy for interfering and constrained op %+F\n", op->carrier));
430 Make the Perm, recompute liveness and re-scan the insn since the
431 in operands are now the Projs of the Perm.
433 perm = insert_Perm_after(aenv, env->cls, env->dom_front, sched_prev(insn->irn));
435 /* Registers are propagated by insert_Perm_after(). Clean them here! */
437 const ir_edge_t *edge;
439 foreach_out_edge(perm, edge) {
440 ir_node *proj = get_edge_src_irn(edge);
441 arch_set_irn_register(aenv, proj, NULL);
445 We also have to re-build the insn since the input operands are now the Projs of
446 the Perm. Recomputing liveness is also a good idea if a Perm is inserted, since
447 the live sets may change.
449 be_liveness(env->irg);
450 obstack_free(&env->obst, insn);
451 *the_insn = insn = scan_insn(env, insn->irn, &env->obst);
454 Copy the input constraints of the insn to the Perm as output
455 constraints. Succeeding phases (coalescing will need that).
457 for(i = insn->use_start; i < insn->n_ops; ++i) {
458 ir_node *proj = insn->ops[i].carrier;
460 Note that the predecessor must not be a Proj of the Perm,
461 since ignore-nodes are not Perm'ed.
463 if(is_Proj(proj) && get_Proj_pred(proj) == perm) {
464 be_set_constr_limited(perm, BE_OUT_POS(get_Proj_proj(proj)), &insn->ops[i].req);
472 static ir_node *handle_constraints(be_chordal_alloc_env_t *alloc_env, ir_node *irn)
474 be_chordal_env_t *env = alloc_env->chordal_env;
475 void *base = obstack_base(&env->obst);
476 insn_t *insn = scan_insn(env, irn, &env->obst);
477 ir_node *res = insn->next_insn;
479 if(insn->pre_colored) {
481 for(i = 0; i < insn->use_start; ++i)
482 pset_insert_ptr(alloc_env->pre_colored, insn->ops[i].carrier);
485 if(be_is_Perm(irn) || be_is_RegParams(irn) || (be_is_Barrier(irn) && !insn->in_constraints))
489 Perms inserted before the constraint handling phase are considered to be
490 correctly precolored. These Perms arise during the ABI handling phase.
492 if(insn->has_constraints) {
493 firm_dbg_module_t *dbg = alloc_env->constr_dbg;
494 const arch_env_t *aenv = env->birg->main_env->arch_env;
495 int n_regs = env->cls->n_regs;
496 bitset_t *bs = bitset_alloca(n_regs);
497 bitset_t *non_ignore = bitset_alloca(n_regs);
498 ir_node **alloc_nodes = alloca(n_regs * sizeof(alloc_nodes[0]));
499 bipartite_t *bp = bipartite_new(n_regs, n_regs);
500 int *assignment = alloca(n_regs * sizeof(assignment[0]));
501 pmap *partners = pmap_create();
505 const ir_edge_t *edge;
506 ir_node *perm = NULL;
509 prepare the constraint handling of this node.
510 Perms are constructed and Copies are created for constrained values
511 interfering with the instruction.
513 perm = pre_process_constraints(alloc_env, &insn);
515 /* find suitable in operands to the out operands of the node. */
516 pair_up_operands(alloc_env, insn);
519 look at the in/out operands and add each operand (and its possible partner)
520 to a bipartite graph (left: nodes with partners, right: admissible colors).
522 for(i = 0, n_alloc = 0; i < insn->n_ops; ++i) {
523 operand_t *op = &insn->ops[i];
526 If the operand has no partner or the partner has not been marked
527 for allocation, determine the admissible registers and mark it
528 for allocation by associating the node and its partner with the
529 set of admissible registers via a bipartite graph.
531 if(!op->partner || !pmap_contains(partners, op->partner->carrier)) {
533 pmap_insert(partners, op->carrier, op->partner ? op->partner->carrier : NULL);
534 alloc_nodes[n_alloc] = op->carrier;
536 DBG((dbg, LEVEL_2, "\tassociating %+F and %+F\n", op->carrier, op->partner ? op->partner->carrier : NULL));
538 bitset_clear_all(bs);
539 get_decisive_partner_regs(bs, op, op->partner);
541 DBG((dbg, LEVEL_2, "\tallowed registers for %+F: %B\n", op->carrier, bs));
543 bitset_foreach(bs, col)
544 bipartite_add(bp, n_alloc, col);
551 Put all nodes which live by the constrained instruction also to the
552 allocation bipartite graph. They are considered unconstrained.
555 foreach_out_edge(perm, edge) {
556 ir_node *proj = get_edge_src_irn(edge);
558 assert(is_Proj(proj));
560 if(values_interfere(proj, irn)) {
561 assert(n_alloc < n_regs);
562 alloc_nodes[n_alloc] = proj;
563 pmap_insert(partners, proj, NULL);
565 bitset_clear_all(bs);
566 arch_put_non_ignore_regs(aenv, env->cls, bs);
567 bitset_foreach(bs, col)
568 bipartite_add(bp, n_alloc, col);
575 /* Compute a valid register allocation. */
576 bipartite_matching(bp, assignment);
578 /* Assign colors obtained from the matching. */
579 for(i = 0; i < n_alloc; ++i) {
580 const arch_register_t *reg;
584 assert(assignment[i] >= 0 && "there must have been a register assigned");
585 reg = arch_register_for_index(env->cls, assignment[i]);
587 nodes[0] = alloc_nodes[i];
588 nodes[1] = pmap_get(partners, alloc_nodes[i]);
590 for(j = 0; j < 2; ++j) {
594 arch_set_irn_register(aenv, nodes[j], reg);
595 pset_hinsert_ptr(alloc_env->pre_colored, nodes[j]);
596 DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", nodes[j], reg->name));
601 /* Allocate the non-constrained Projs of the Perm. */
604 bitset_clear_all(bs);
606 /* Put the colors of all Projs in a bitset. */
607 foreach_out_edge(perm, edge) {
608 ir_node *proj = get_edge_src_irn(edge);
609 const arch_register_t *reg = arch_get_irn_register(aenv, proj);
612 bitset_set(bs, reg->index);
615 /* Assign the not yet assigned Projs of the Perm a suitable color. */
616 foreach_out_edge(perm, edge) {
617 ir_node *proj = get_edge_src_irn(edge);
618 const arch_register_t *reg = arch_get_irn_register(aenv, proj);
620 DBG((dbg, LEVEL_2, "\tchecking reg of %+F: %s\n", proj, reg ? reg->name : "<none>"));
623 col = get_next_free_reg(alloc_env, bs);
624 reg = arch_register_for_index(env->cls, col);
625 bitset_set(bs, reg->index);
626 arch_set_irn_register(aenv, proj, reg);
627 pset_insert_ptr(alloc_env->pre_colored, proj);
628 DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", proj, reg->name));
633 pmap_destroy(partners);
637 obstack_free(&env->obst, base);
642 * Handle constraint nodes in each basic block.
643 * be_insert_constr_perms() inserts Perm nodes which perm
644 * over all values live at the constrained node right in front
645 * of the constrained node. These Perms signal a constrained node.
646 * For further comments, refer to handle_constraints_at_perm().
648 static void constraints(ir_node *bl, void *data)
650 firm_dbg_module_t *dbg = firm_dbg_register("firm.be.chordal.constr");
651 be_chordal_alloc_env_t *env = data;
652 arch_env_t *arch_env = env->chordal_env->birg->main_env->arch_env;
655 for(irn = sched_first(bl); !sched_is_end(irn);) {
656 irn = handle_constraints(env, irn);
661 * Annotate the register pressure to the nodes and compute
662 * the liveness intervals.
663 * @param block The block to do it for.
664 * @param env_ptr The environment.
666 static void pressure(ir_node *block, void *env_ptr)
668 /* Convenience macro for a def */
669 #define border_def(irn, step, real) \
670 border_add(env, head, irn, step, pressure--, 1, real)
672 /* Convenience macro for a use */
673 #define border_use(irn, step, real) \
674 border_add(env, head, irn, step, ++pressure, 0, real)
676 be_chordal_alloc_env_t *alloc_env = env_ptr;
677 be_chordal_env_t *env = alloc_env->chordal_env;
678 const arch_env_t *arch_env = env->birg->main_env->arch_env;
679 bitset_t *live = alloc_env->live;
680 firm_dbg_module_t *dbg = env->dbg;
685 unsigned pressure = 0;
686 struct list_head *head;
687 pset *live_in = put_live_in(block, pset_new_ptr_default());
688 pset *live_end = put_live_end(block, pset_new_ptr_default());
690 DBG((dbg, LEVEL_1, "Computing pressure in block %+F\n", block));
691 bitset_clear_all(live);
693 /* Set up the border list in the block info */
694 head = obstack_alloc(&env->obst, sizeof(*head));
695 INIT_LIST_HEAD(head);
696 assert(pmap_get(env->border_heads, block) == NULL);
697 pmap_insert(env->border_heads, block, head);
700 * Make final uses of all values live out of the block.
701 * They are necessary to build up real intervals.
703 for(irn = pset_first(live_end); irn; irn = pset_next(live_end)) {
704 if(has_reg_class(env, irn)) {
705 DBG((dbg, LEVEL_3, "\tMaking live: %+F/%d\n", irn, get_irn_graph_nr(irn)));
706 bitset_set(live, get_irn_graph_nr(irn));
707 border_use(irn, step, 0);
713 * Determine the last uses of a value inside the block, since they are
714 * relevant for the interval borders.
716 sched_foreach_reverse(block, irn) {
717 DBG((dbg, LEVEL_1, "\tinsn: %+F, pressure: %d\n", irn, pressure));
718 DBG((dbg, LEVEL_2, "\tlive: %b\n", live));
721 * If the node defines some value, which can put into a
722 * register of the current class, make a border for it.
724 if(has_reg_class(env, irn)) {
725 int nr = get_irn_graph_nr(irn);
727 bitset_clear(live, nr);
728 border_def(irn, step, 1);
732 * If the node is no phi node we can examine the uses.
735 for(i = 0, n = get_irn_arity(irn); i < n; ++i) {
736 ir_node *op = get_irn_n(irn, i);
738 if(has_reg_class(env, op)) {
739 int nr = get_irn_graph_nr(op);
741 DBG((dbg, LEVEL_4, "\t\tpos: %d, use: %+F\n", i, op));
743 if(!bitset_is_set(live, nr)) {
744 border_use(op, step, 1);
745 bitset_set(live, nr);
754 * Add initial defs for all values live in.
756 for(irn = pset_first(live_in); irn; irn = pset_next(live_in)) {
757 if(has_reg_class(env, irn)) {
759 /* Mark the value live in. */
760 bitset_set(live, get_irn_graph_nr(irn));
763 border_def(irn, step, 0);
772 static void assign(ir_node *block, void *env_ptr)
774 be_chordal_alloc_env_t *alloc_env = env_ptr;
775 be_chordal_env_t *env = alloc_env->chordal_env;
776 firm_dbg_module_t *dbg = env->dbg;
777 bitset_t *live = alloc_env->live;
778 bitset_t *colors = alloc_env->colors;
779 bitset_t *in_colors = alloc_env->in_colors;
780 const arch_env_t *arch_env = env->birg->main_env->arch_env;
784 struct list_head *head = get_block_border_head(env, block);
785 pset *live_in = put_live_in(block, pset_new_ptr_default());
787 bitset_clear_all(colors);
788 bitset_clear_all(live);
789 bitset_clear_all(in_colors);
791 DBG((dbg, LEVEL_4, "Assigning colors for block %+F\n", block));
792 DBG((dbg, LEVEL_4, "\tusedef chain for block\n"));
793 list_for_each_entry(border_t, b, head, list) {
794 DBG((dbg, LEVEL_4, "\t%s %+F/%d\n", b->is_def ? "def" : "use",
795 b->irn, get_irn_graph_nr(b->irn)));
799 * Add initial defs for all values live in.
800 * Since their colors have already been assigned (The dominators were
801 * allocated before), we have to mark their colors as used also.
803 for(irn = pset_first(live_in); irn; irn = pset_next(live_in)) {
804 if(has_reg_class(env, irn)) {
805 const arch_register_t *reg = arch_get_irn_register(arch_env, irn);
808 assert(reg && "Node must have been assigned a register");
809 col = arch_register_get_index(reg);
811 /* Mark the color of the live in value as used. */
812 bitset_set(colors, col);
813 bitset_set(in_colors, col);
815 /* Mark the value live in. */
816 bitset_set(live, get_irn_graph_nr(irn));
821 * Mind that the sequence
822 * of defs from back to front defines a perfect
823 * elimination order. So, coloring the definitions from first to last
826 list_for_each_entry_reverse(border_t, b, head, list) {
827 ir_node *irn = b->irn;
828 int nr = get_irn_graph_nr(irn);
831 * Assign a color, if it is a local def. Global defs already have a
834 if(b->is_def && !is_live_in(block, irn)) {
835 const arch_register_t *reg;
838 if(pset_find_ptr(alloc_env->pre_colored, irn)) {
839 reg = arch_get_irn_register(arch_env, irn);
841 assert(!bitset_is_set(colors, col) && "pre-colored register must be free");
845 col = get_next_free_reg(alloc_env, colors);
846 reg = arch_register_for_index(env->cls, col);
847 assert(arch_get_irn_register(arch_env, irn) == NULL && "This node must not have been assigned a register yet");
850 bitset_set(colors, col);
852 assert(!arch_register_type_is(reg, ignore) && "Must not assign ignore register");
853 arch_set_irn_register(arch_env, irn, reg);
855 DBG((dbg, LEVEL_1, "\tassigning register %s(%d) to %+F\n",
856 arch_register_get_name(reg), col, irn));
858 assert(!bitset_is_set(live, nr) && "Value's definition must not have been encountered");
859 bitset_set(live, nr);
862 /* Clear the color upon a use. */
863 else if(!b->is_def) {
864 const arch_register_t *reg = arch_get_irn_register(arch_env, irn);
867 assert(reg && "Register must have been assigned");
869 col = arch_register_get_index(reg);
870 assert(bitset_is_set(live, nr) && "Cannot have a non live use");
872 bitset_clear(colors, col);
873 bitset_clear(live, nr);
880 void be_ra_chordal_color(be_chordal_env_t *chordal_env)
882 be_chordal_alloc_env_t env;
886 int colors_n = arch_register_class_n_regs(chordal_env->cls);
887 ir_graph *irg = chordal_env->irg;
890 if(get_irg_dom_state(irg) != dom_consistent)
893 env.chordal_env = chordal_env;
894 env.colors_n = colors_n;
895 env.colors = bitset_malloc(colors_n);
896 env.in_colors = bitset_malloc(colors_n);
897 env.ignore_regs = bitset_malloc(colors_n);
898 env.pre_colored = pset_new_ptr_default();
899 env.constr_dbg = firm_dbg_register("firm.be.chordal.constr");
901 for(i = 0; i < colors_n; ++i)
902 if(arch_register_type_is(&chordal_env->cls->regs[i], ignore))
903 bitset_set(env.ignore_regs, i);
905 /* Handle register targeting constraints */
906 dom_tree_walk_irg(irg, constraints, NULL, &env);
908 if(chordal_env->opts->dump_flags & BE_CH_DUMP_CONSTR) {
909 snprintf(buf, sizeof(buf), "-%s-constr", chordal_env->cls->name);
910 be_dump(chordal_env->irg, buf, dump_ir_block_graph_sched);
914 env.live = bitset_malloc(get_graph_node_count(chordal_env->irg));
916 /* First, determine the pressure */
917 dom_tree_walk_irg(irg, pressure, NULL, &env);
919 /* Assign the colors */
920 dom_tree_walk_irg(irg, assign, NULL, &env);
922 be_numbering_done(irg);
924 if(chordal_env->opts->dump_flags & BE_CH_DUMP_TREE_INTV) {
926 ir_snprintf(buf, sizeof(buf), "ifg_%s_%F.eps", chordal_env->cls->name, irg);
927 plotter = new_plotter_ps(buf);
928 draw_interval_tree(&draw_chordal_def_opts, chordal_env, plotter);
929 plotter_free(plotter);
935 free(env.ignore_regs);
936 del_pset(env.pre_colored);