2 * Chordal register allocation.
3 * @author Sebastian Hack
6 * Copyright (C) Universitaet Karlsruhe
7 * Released under the GPL
29 #include "bipartite.h"
32 #include "irgraph_t.h"
33 #include "irprintf_t.h"
43 #include "besched_t.h"
49 #include "bechordal_t.h"
50 #include "bechordal_draw.h"
52 #define DBG_LEVEL SET_LEVEL_0
53 #define DBG_LEVEL_CHECK SET_LEVEL_0
57 #define DUMP_INTERVALS
59 typedef struct _be_chordal_alloc_env_t {
60 be_chordal_env_t *chordal_env;
62 pset *pre_colored; /**< Set of precolored nodes. */
63 bitset_t *live; /**< A liveness bitset. */
64 bitset_t *colors; /**< The color mask. */
65 bitset_t *in_colors; /**< Colors used by live in values. */
66 int colors_n; /**< The number of colors. */
67 } be_chordal_alloc_env_t;
71 /* Make a fourcc for border checking. */
72 #define BORDER_FOURCC FOURCC('B', 'O', 'R', 'D')
74 static void check_border_list(struct list_head *head)
77 list_for_each_entry(border_t, x, head, list) {
78 assert(x->magic == BORDER_FOURCC);
82 static void check_heads(be_chordal_env_t *env)
85 for(ent = pmap_first(env->border_heads); ent; ent = pmap_next(env->border_heads)) {
86 /* ir_printf("checking border list of block %+F\n", ent->key); */
87 check_border_list(ent->value);
93 * Add an interval border to the list of a block's list
95 * @note You always have to create the use before the def.
96 * @param env The environment.
97 * @param head The list head to enqueue the borders.
98 * @param irn The node (value) the border belongs to.
99 * @param pressure The pressure at this point in time.
100 * @param step A time step for the border.
101 * @param is_def Is the border a use or a def.
102 * @return The created border.
104 static INLINE border_t *border_add(be_chordal_env_t *env, struct list_head *head,
105 ir_node *irn, unsigned step, unsigned pressure,
106 unsigned is_def, unsigned is_real)
113 b = obstack_alloc(&env->obst, sizeof(*b));
115 /* also allocate the def and tie it to the use. */
116 def = obstack_alloc(&env->obst, sizeof(*def));
117 memset(def, 0, sizeof(*def));
122 * Set the link field of the irn to the def.
123 * This strongly relies on the fact, that the use is always
124 * made before the def.
126 set_irn_link(irn, def);
128 b->magic = BORDER_FOURCC;
129 def->magic = BORDER_FOURCC;
133 * If the def is encountered, the use was made and so was the
134 * the def node (see the code above). It was placed into the
135 * link field of the irn, so we can get it there.
138 b = get_irn_link(irn);
140 assert(b && b->magic == BORDER_FOURCC && "Illegal border encountered");
143 b->pressure = pressure;
145 b->is_real = is_real;
148 list_add_tail(&b->list, head);
149 DBG((env->dbg, LEVEL_5, "\t\t%s adding %+F, step: %d\n", is_def ? "def" : "use", irn, step));
156 * Check, if an irn is of the register class currently under processing.
157 * @param env The chordal environment.
158 * @param irn The node.
159 * @return 1, if the node is of that register class, 0 if not.
161 static INLINE int has_reg_class(const be_chordal_env_t *env, const ir_node *irn)
163 // return arch_irn_has_reg_class(env->main_env->arch_env, irn, -1, env->cls);
164 return arch_irn_consider_in_reg_alloc(env->birg->main_env->arch_env, env->cls, irn);
167 #define has_limited_constr(req, irn) \
168 (arch_get_register_req(arch_env, (req), irn, -1) && (req)->type == arch_register_req_type_limited)
170 typedef struct _operand_t operand_t;
177 arch_register_req_t req;
185 unsigned has_constraints : 1;
188 static insn_t *scan_insn(be_chordal_env_t *env, ir_node *irn, struct obstack *obst)
190 const arch_env_t *arch_env = env->birg->main_env->arch_env;
195 insn = obstack_alloc(obst, sizeof(insn[0]));
196 memset(insn, 0, sizeof(insn[0]));
198 insn->next_insn = sched_next(irn);
199 if(get_irn_mode(irn) == mode_T) {
202 for(p = sched_next(irn); is_Proj(p); p = sched_next(p)) {
203 if(arch_irn_consider_in_reg_alloc(arch_env, env->cls, p)) {
206 o.pos = -(get_Proj_proj(p) + 1);
208 arch_get_register_req(arch_env, &o.req, p, -1);
209 obstack_grow(obst, &o, sizeof(o));
211 insn->has_constraints |= arch_register_req_is(&o.req, limited);
218 else if(arch_irn_consider_in_reg_alloc(arch_env, env->cls, irn)) {
223 arch_get_register_req(arch_env, &o.req, irn, -1);
224 obstack_grow(obst, &o, sizeof(o));
226 insn->has_constraints |= arch_register_req_is(&o.req, limited);
229 insn->use_start = insn->n_ops;
231 for(i = 0, n = get_irn_arity(irn); i < n; ++i) {
232 ir_node *op = get_irn_n(irn, i);
234 if(arch_irn_consider_in_reg_alloc(arch_env, env->cls, op)) {
239 arch_get_register_req(arch_env, &o.req, irn, i);
240 obstack_grow(obst, &o, sizeof(o));
242 insn->has_constraints |= arch_register_req_is(&o.req, limited);
246 insn->ops = obstack_finish(obst);
250 static operand_t *find_unpaired_use(insn_t *insn, const operand_t *op, int can_be_constrained)
253 operand_t *res = NULL;
255 for(i = insn->use_start; i < insn->n_ops; ++i) {
256 operand_t *op = &insn->ops[i];
257 int has_constraint = arch_register_req_is(&op->req, limited);
259 if(!values_interfere(op->carrier, op->irn) && !op->partner && (!has_constraint || can_be_constrained)) {
260 if(arch_register_req_is(&op->req, should_be_same) && op->req.other_same == op->carrier)
270 static void pair_up_operands(insn_t *insn)
272 firm_dbg_module_t *dbg = firm_dbg_register("firm.be.chordal.constr");
275 for(i = 0; i < insn->use_start; ++i) {
276 operand_t *op = &insn->ops[i];
277 int has_constraint = arch_register_req_is(&op->req, limited);
278 operand_t *partner = find_unpaired_use(insn, op, !has_constraint);
281 op->partner = partner;
282 partner->partner = op;
287 static ir_node *handle_constraints(be_chordal_alloc_env_t *alloc_env, ir_node *irn)
289 be_chordal_env_t *env = alloc_env->chordal_env;
290 void *base = obstack_base(&env->obst);
291 insn_t *insn = scan_insn(env, irn, &env->obst);
292 ir_node *res = insn->next_insn;
294 if(insn->has_constraints) {
295 firm_dbg_module_t *dbg = firm_dbg_register("firm.be.chordal.constr");
296 const arch_env_t *aenv = env->birg->main_env->arch_env;
297 int n_regs = env->cls->n_regs;
298 bitset_t *bs = bitset_alloca(n_regs);
299 bitset_t *non_ignore = bitset_alloca(n_regs);
300 ir_node **alloc_nodes = alloca(n_regs * sizeof(alloc_nodes[0]));
301 bipartite_t *bp = bipartite_new(n_regs, n_regs);
302 int *assignment = alloca(n_regs * sizeof(assignment[0]));
303 pmap *partners = pmap_create();
307 const ir_edge_t *edge;
308 ir_node *perm = insert_Perm_after(aenv, env->cls, env->dom_front, sched_prev(irn));
310 arch_put_non_ignore_regs(aenv, env->cls, non_ignore);
312 /* Registers are propagated by insert_Perm_after(). Clean them here! */
314 foreach_out_edge(perm, edge) {
315 ir_node *proj = get_edge_src_irn(edge);
316 arch_set_irn_register(aenv, proj, NULL);
321 be_liveness(env->irg);
322 insn = scan_insn(env, irn, &env->obst);
324 DBG((dbg, LEVEL_1, "handling constraints for %+F\n", irn));
327 * If there was no Perm made, nothing was alive in this register class.
328 * This means, that the node has no operands, thus no input constraints.
329 * so it had output constraints. The other results then can be assigned freely.
332 pair_up_operands(insn);
334 for(i = 0, n_alloc = 0; i < insn->n_ops; ++i) {
335 operand_t *op = &insn->ops[i];
336 if(arch_register_req_is(&op->req, limited) && arch_irn_consider_in_reg_alloc(aenv, env->cls, op->carrier)) {
337 const arch_register_t *reg = arch_get_irn_register(aenv, op->carrier);
339 pmap_insert(partners, op->carrier, op->partner ? op->partner->carrier : NULL);
340 alloc_nodes[n_alloc] = op->carrier;
342 DBG((dbg, LEVEL_2, "\tassociating %+F and %+F\n", op->carrier, pmap_get(partners, op->carrier)));
344 bitset_clear_all(bs);
345 op->req.limited(op->req.limited_env, bs);
346 assert((!reg || bitset_is_set(bs, reg->index)) && "color of pre-colored node is not in its allowed colors");
347 bitset_and(bs, non_ignore);
349 /* if the node is pre-colored, explicitly allow the color with which it is pre-colored. */
351 bitset_set(bs, reg->index);
354 DBG((dbg, LEVEL_2, "\tallowed registers for %+F: %B\n", op->carrier, bs));
356 bitset_foreach(bs, col)
357 bipartite_add(bp, n_alloc, col);
364 /* Make the input constraints of the node to output constraints of the Perm's Projs */
365 for(i = insn->use_start; i < insn->n_ops; ++i) {
366 operand_t *op = &insn->ops[i];
369 If the operand is an "in" operand, constrained and the carrier is a Proj to the Perm,
370 then copy the in constraint to the Perm's out constraint
372 if(arch_register_req_is(&op->req, limited) && is_Proj(op->carrier) && perm == get_Proj_pred(op->carrier))
373 be_set_constr_limited(perm, BE_OUT_POS(get_Proj_proj(op->carrier)), &op->req);
376 foreach_out_edge(perm, edge) {
377 ir_node *proj = get_edge_src_irn(edge);
379 assert(is_Proj(proj));
381 if(values_interfere(proj, irn)) {
382 assert(n_alloc < n_regs);
383 alloc_nodes[n_alloc] = proj;
384 pmap_insert(partners, proj, NULL);
386 bitset_clear_all(bs);
387 arch_get_allocatable_regs(aenv, proj, -1, bs);
388 bitset_and(bs, non_ignore);
389 bitset_foreach(bs, col)
390 bipartite_add(bp, n_alloc, col);
397 bipartite_matching(bp, assignment);
399 /* Assign colors obtained from the matching. */
400 for(i = 0; i < n_alloc; ++i) {
403 const arch_register_t *reg;
405 assert(assignment[i] >= 0 && "there must have been a register assigned");
406 reg = arch_register_for_index(env->cls, assignment[i]);
408 nodes[0] = alloc_nodes[i];
409 nodes[1] = pmap_get(partners, alloc_nodes[i]);
411 for(j = 0; j < 2; ++j) {
415 arch_set_irn_register(aenv, nodes[j], reg);
416 pset_hinsert_ptr(alloc_env->pre_colored, nodes[j]);
417 DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", nodes[j], reg->name));
422 /* Allocate the non-constrained Projs of the Perm. */
424 bitset_clear_all(bs);
426 /* Put the colors of all Projs in a bitset. */
427 foreach_out_edge(perm, edge) {
428 ir_node *proj = get_edge_src_irn(edge);
429 const arch_register_t *reg = arch_get_irn_register(aenv, proj);
432 bitset_set(bs, reg->index);
435 /* Assign the not yet assigned Projs of the Perm a suitable color. */
436 foreach_out_edge(perm, edge) {
437 ir_node *proj = get_edge_src_irn(edge);
438 const arch_register_t *reg = arch_get_irn_register(aenv, proj);
440 DBG((dbg, LEVEL_2, "\tchecking reg of %+F: %s\n", proj, reg ? reg->name : "<none>"));
443 col = bitset_next_clear(bs, 0);
444 reg = arch_register_for_index(env->cls, col);
445 bitset_set(bs, reg->index);
446 arch_set_irn_register(aenv, proj, reg);
447 pset_insert_ptr(alloc_env->pre_colored, proj);
448 DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", proj, reg->name));
453 pmap_destroy(partners);
456 obstack_free(&env->obst, base);
461 * Handle constraint nodes in each basic block.
462 * be_insert_constr_perms() inserts Perm nodes which perm
463 * over all values live at the constrained node right in front
464 * of the constrained node. These Perms signal a constrained node.
465 * For further comments, refer to handle_constraints_at_perm().
467 static void constraints(ir_node *bl, void *data)
469 firm_dbg_module_t *dbg = firm_dbg_register("firm.be.chordal.constr");
470 be_chordal_alloc_env_t *env = data;
471 arch_env_t *arch_env = env->chordal_env->birg->main_env->arch_env;
474 for(irn = sched_first(bl); !sched_is_end(irn);) {
475 irn = handle_constraints(env, irn);
480 * Annotate the register pressure to the nodes and compute
481 * the liveness intervals.
482 * @param block The block to do it for.
483 * @param env_ptr The environment.
485 static void pressure(ir_node *block, void *env_ptr)
487 /* Convenience macro for a def */
488 #define border_def(irn, step, real) \
489 border_add(env, head, irn, step, pressure--, 1, real)
491 /* Convenience macro for a use */
492 #define border_use(irn, step, real) \
493 border_add(env, head, irn, step, ++pressure, 0, real)
495 be_chordal_alloc_env_t *alloc_env = env_ptr;
496 be_chordal_env_t *env = alloc_env->chordal_env;
497 const arch_env_t *arch_env = env->birg->main_env->arch_env;
498 bitset_t *live = alloc_env->live;
499 firm_dbg_module_t *dbg = env->dbg;
504 unsigned pressure = 0;
505 struct list_head *head;
506 pset *live_in = put_live_in(block, pset_new_ptr_default());
507 pset *live_end = put_live_end(block, pset_new_ptr_default());
509 DBG((dbg, LEVEL_1, "Computing pressure in block %+F\n", block));
510 bitset_clear_all(live);
512 /* Set up the border list in the block info */
513 head = obstack_alloc(&env->obst, sizeof(*head));
514 INIT_LIST_HEAD(head);
515 assert(pmap_get(env->border_heads, block) == NULL);
516 pmap_insert(env->border_heads, block, head);
519 * Make final uses of all values live out of the block.
520 * They are necessary to build up real intervals.
522 for(irn = pset_first(live_end); irn; irn = pset_next(live_end)) {
523 if(has_reg_class(env, irn)) {
524 DBG((dbg, LEVEL_3, "\tMaking live: %+F/%d\n", irn, get_irn_graph_nr(irn)));
525 bitset_set(live, get_irn_graph_nr(irn));
526 border_use(irn, step, 0);
532 * Determine the last uses of a value inside the block, since they are
533 * relevant for the interval borders.
535 sched_foreach_reverse(block, irn) {
536 DBG((dbg, LEVEL_1, "\tinsn: %+F, pressure: %d\n", irn, pressure));
537 DBG((dbg, LEVEL_2, "\tlive: %b\n", live));
540 * If the node defines some value, which can put into a
541 * register of the current class, make a border for it.
543 if(has_reg_class(env, irn)) {
544 int nr = get_irn_graph_nr(irn);
546 bitset_clear(live, nr);
547 border_def(irn, step, 1);
551 * If the node is no phi node we can examine the uses.
554 for(i = 0, n = get_irn_arity(irn); i < n; ++i) {
555 ir_node *op = get_irn_n(irn, i);
557 if(has_reg_class(env, op)) {
558 int nr = get_irn_graph_nr(op);
560 DBG((dbg, LEVEL_4, "\t\tpos: %d, use: %+F\n", i, op));
562 if(!bitset_is_set(live, nr)) {
563 border_use(op, step, 1);
564 bitset_set(live, nr);
573 * Add initial defs for all values live in.
575 for(irn = pset_first(live_in); irn; irn = pset_next(live_in)) {
576 if(has_reg_class(env, irn)) {
578 /* Mark the value live in. */
579 bitset_set(live, get_irn_graph_nr(irn));
582 border_def(irn, step, 0);
591 static void assign(ir_node *block, void *env_ptr)
593 be_chordal_alloc_env_t *alloc_env = env_ptr;
594 be_chordal_env_t *env = alloc_env->chordal_env;
595 firm_dbg_module_t *dbg = env->dbg;
596 bitset_t *live = alloc_env->live;
597 bitset_t *colors = alloc_env->colors;
598 bitset_t *in_colors = alloc_env->in_colors;
599 const arch_env_t *arch_env = env->birg->main_env->arch_env;
603 struct list_head *head = get_block_border_head(env, block);
604 pset *live_in = put_live_in(block, pset_new_ptr_default());
606 bitset_clear_all(colors);
607 bitset_clear_all(live);
608 bitset_clear_all(in_colors);
610 DBG((dbg, LEVEL_4, "Assigning colors for block %+F\n", block));
611 DBG((dbg, LEVEL_4, "\tusedef chain for block\n"));
612 list_for_each_entry(border_t, b, head, list) {
613 DBG((dbg, LEVEL_4, "\t%s %+F/%d\n", b->is_def ? "def" : "use",
614 b->irn, get_irn_graph_nr(b->irn)));
618 * Add initial defs for all values live in.
619 * Since their colors have already been assigned (The dominators were
620 * allocated before), we have to mark their colors as used also.
622 for(irn = pset_first(live_in); irn; irn = pset_next(live_in)) {
623 if(has_reg_class(env, irn)) {
624 const arch_register_t *reg = arch_get_irn_register(arch_env, irn);
627 assert(reg && "Node must have been assigned a register");
628 col = arch_register_get_index(reg);
630 /* Mark the color of the live in value as used. */
631 bitset_set(colors, col);
632 bitset_set(in_colors, col);
634 /* Mark the value live in. */
635 bitset_set(live, get_irn_graph_nr(irn));
640 * Mind that the sequence
641 * of defs from back to front defines a perfect
642 * elimination order. So, coloring the definitions from first to last
645 list_for_each_entry_reverse(border_t, b, head, list) {
646 ir_node *irn = b->irn;
647 int nr = get_irn_graph_nr(irn);
650 * Assign a color, if it is a local def. Global defs already have a
653 if(b->is_def && !is_live_in(block, irn)) {
654 const arch_register_t *reg;
657 if(pset_find_ptr(alloc_env->pre_colored, irn)) {
658 reg = arch_get_irn_register(arch_env, irn);
660 assert(!bitset_is_set(colors, col) && "pre-colored register must be free");
664 col = bitset_next_clear(colors, 0);
665 reg = arch_register_for_index(env->cls, col);
666 assert(arch_get_irn_register(arch_env, irn) == NULL && "This node must not have been assigned a register yet");
669 bitset_set(colors, col);
670 arch_set_irn_register(arch_env, irn, reg);
672 DBG((dbg, LEVEL_1, "\tassigning register %s(%d) to %+F\n",
673 arch_register_get_name(reg), col, irn));
675 assert(!bitset_is_set(live, nr) && "Value's definition must not have been encountered");
676 bitset_set(live, nr);
679 /* Clear the color upon a use. */
680 else if(!b->is_def) {
681 const arch_register_t *reg = arch_get_irn_register(arch_env, irn);
684 assert(reg && "Register must have been assigned");
686 col = arch_register_get_index(reg);
687 assert(bitset_is_set(live, nr) && "Cannot have a non live use");
689 bitset_clear(colors, col);
690 bitset_clear(live, nr);
697 void be_ra_chordal_color(be_chordal_env_t *chordal_env)
699 be_chordal_alloc_env_t env;
702 int colors_n = arch_register_class_n_regs(chordal_env->cls);
703 ir_graph *irg = chordal_env->irg;
706 if(get_irg_dom_state(irg) != dom_consistent)
709 env.chordal_env = chordal_env;
710 env.colors_n = colors_n;
711 env.colors = bitset_malloc(colors_n);
712 env.in_colors = bitset_malloc(colors_n);
713 env.pre_colored = pset_new_ptr_default();
715 /* Handle register targeting constraints */
716 dom_tree_walk_irg(irg, constraints, NULL, &env);
718 if(chordal_env->opts->dump_flags & BE_CH_DUMP_CONSTR) {
719 snprintf(buf, sizeof(buf), "-%s-constr", chordal_env->cls->name);
720 dump_ir_block_graph_sched(chordal_env->irg, buf);
724 env.live = bitset_malloc(get_graph_node_count(chordal_env->irg));
726 /* First, determine the pressure */
727 dom_tree_walk_irg(irg, pressure, NULL, &env);
729 /* Assign the colors */
730 dom_tree_walk_irg(irg, assign, NULL, &env);
732 be_numbering_done(irg);
734 if(chordal_env->opts->dump_flags & BE_CH_DUMP_TREE_INTV) {
736 ir_snprintf(buf, sizeof(buf), "ifg_%s_%F.eps", chordal_env->cls->name, irg);
737 plotter = new_plotter_ps(buf);
738 draw_interval_tree(&draw_chordal_def_opts, chordal_env, plotter);
739 plotter_free(plotter);
745 del_pset(env.pre_colored);