2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Chordal register allocation.
23 * @author Sebastian Hack
35 #include "raw_bitset.h"
37 #include "bipartite.h"
38 #include "hungarian.h"
41 #include "irgraph_t.h"
42 #include "irprintf_t.h"
53 #include "besched_t.h"
60 #include "bestatevent.h"
62 #include "beintlive_t.h"
64 #include "bechordal_t.h"
65 #include "bechordal_draw.h"
68 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
72 #define DUMP_INTERVALS
74 typedef struct _be_chordal_alloc_env_t {
75 be_chordal_env_t *chordal_env;
77 pset *pre_colored; /**< Set of precolored nodes. */
78 bitset_t *live; /**< A liveness bitset. */
79 bitset_t *tmp_colors; /**< An auxiliary bitset which is as long as the number of colors in the class. */
80 bitset_t *colors; /**< The color mask. */
81 bitset_t *in_colors; /**< Colors used by live in values. */
82 int colors_n; /**< The number of colors. */
83 } be_chordal_alloc_env_t;
87 /* Make a fourcc for border checking. */
88 #define BORDER_FOURCC FOURCC('B', 'O', 'R', 'D')
91 static void check_border_list(struct list_head *head)
94 list_for_each_entry(border_t, x, head, list) {
95 assert(x->magic == BORDER_FOURCC);
99 static void check_heads(be_chordal_env_t *env)
102 for (ent = pmap_first(env->border_heads); ent; ent = pmap_next(env->border_heads)) {
103 /* ir_printf("checking border list of block %+F\n", ent->key); */
104 check_border_list(ent->value);
110 * Add an interval border to the list of a block's list
111 * of interval border.
112 * @note You always have to create the use before the def.
113 * @param env The environment.
114 * @param head The list head to enqueue the borders.
115 * @param irn The node (value) the border belongs to.
116 * @param pressure The pressure at this point in time.
117 * @param step A time step for the border.
118 * @param is_def Is the border a use or a def.
119 * @return The created border.
121 static inline border_t *border_add(be_chordal_env_t *env, struct list_head *head,
122 ir_node *irn, unsigned step, unsigned pressure,
123 unsigned is_def, unsigned is_real)
130 b = obstack_alloc(env->obst, sizeof(*b));
132 /* also allocate the def and tie it to the use. */
133 def = obstack_alloc(env->obst, sizeof(*def));
134 memset(def, 0, sizeof(*def));
139 * Set the link field of the irn to the def.
140 * This strongly relies on the fact, that the use is always
141 * made before the def.
143 set_irn_link(irn, def);
145 DEBUG_ONLY(b->magic = BORDER_FOURCC);
146 DEBUG_ONLY(def->magic = BORDER_FOURCC);
149 * If the def is encountered, the use was made and so was the
150 * the def node (see the code above). It was placed into the
151 * link field of the irn, so we can get it there.
153 b = get_irn_link(irn);
155 DEBUG_ONLY(assert(b && b->magic == BORDER_FOURCC && "Illegal border encountered"));
158 b->pressure = pressure;
160 b->is_real = is_real;
163 list_add_tail(&b->list, head);
164 DBG((dbg, LEVEL_5, "\t\t%s adding %+F, step: %d\n", is_def ? "def" : "use", irn, step));
171 * Check, if an irn is of the register class currently under processing.
172 * @param env The chordal environment.
173 * @param irn The node.
174 * @return 1, if the node is of that register class, 0 if not.
176 static inline int has_reg_class(const be_chordal_env_t *env, const ir_node *irn)
178 return arch_irn_consider_in_reg_alloc(env->cls, irn);
181 static int get_next_free_reg(const be_chordal_alloc_env_t *alloc_env, bitset_t *colors)
183 bitset_t *tmp = alloc_env->tmp_colors;
184 bitset_copy(tmp, colors);
185 bitset_or(tmp, alloc_env->chordal_env->ignore_colors);
186 return bitset_next_clear(tmp, 0);
189 static bitset_t *get_decisive_partner_regs(bitset_t *bs, const be_operand_t *o1, const be_operand_t *o2)
194 bitset_copy(bs, o2->regs);
199 bitset_copy(bs, o1->regs);
203 assert(o1->req->cls == o2->req->cls || ! o1->req->cls || ! o2->req->cls);
205 if (bitset_contains(o1->regs, o2->regs)) {
206 bitset_copy(bs, o1->regs);
207 } else if (bitset_contains(o2->regs, o1->regs)) {
208 bitset_copy(bs, o2->regs);
216 static be_insn_t *chordal_scan_insn(be_chordal_env_t *env, ir_node *irn)
220 ie.ignore_colors = env->ignore_colors;
223 return be_scan_insn(&ie, irn);
226 static void pair_up_operands(const be_chordal_alloc_env_t *alloc_env, be_insn_t *insn)
228 const be_chordal_env_t *env = alloc_env->chordal_env;
229 bitset_t *bs = bitset_alloca(env->cls->n_regs);
234 * For each out operand, try to find an in operand which can be assigned the
235 * same register as the out operand.
237 for (j = 0; j < insn->use_start; ++j) {
239 int smallest_n_regs = 2 * env->cls->n_regs + 1;
240 be_operand_t *out_op = &insn->ops[j];
242 /* Try to find an in operand which has ... */
243 for (i = insn->use_start; i < insn->n_ops; ++i) {
245 const be_operand_t *op = &insn->ops[i];
247 if (op->partner != NULL)
249 if (be_values_interfere(env->birg->lv, op->irn, op->carrier))
252 bitset_clear_all(bs);
253 bitset_copy(bs, op->regs);
254 bitset_and(bs, out_op->regs);
255 n_total = bitset_popcnt(op->regs) + bitset_popcnt(out_op->regs);
257 if (!bitset_is_empty(bs) && n_total < smallest_n_regs) {
259 smallest_n_regs = n_total;
264 be_operand_t *partner = &insn->ops[smallest];
265 for (i = insn->use_start; i < insn->n_ops; ++i) {
266 if (insn->ops[i].carrier == partner->carrier)
267 insn->ops[i].partner = out_op;
270 out_op->partner = partner;
271 partner->partner = out_op;
277 static ir_node *pre_process_constraints(be_chordal_alloc_env_t *alloc_env,
278 be_insn_t **the_insn)
280 be_chordal_env_t *env = alloc_env->chordal_env;
281 be_insn_t *insn = *the_insn;
282 ir_node *perm = NULL;
283 bitset_t *out_constr = bitset_alloca(env->cls->n_regs);
284 const ir_edge_t *edge;
287 assert(insn->has_constraints && "only do this for constrained nodes");
290 * Collect all registers that occur in output constraints.
291 * This is necessary, since if the insn has one of these as an input constraint
292 * and the corresponding operand interferes with the insn, the operand must
295 for (i = 0; i < insn->use_start; ++i) {
296 be_operand_t *op = &insn->ops[i];
297 if (op->has_constraints)
298 bitset_or(out_constr, op->regs);
302 * Make the Perm, recompute liveness and re-scan the insn since the
303 * in operands are now the Projs of the Perm.
305 perm = insert_Perm_after(env->birg, env->cls, sched_prev(insn->irn));
307 /* Registers are propagated by insert_Perm_after(). Clean them here! */
311 be_stat_ev("constr_perm", get_irn_arity(perm));
312 foreach_out_edge(perm, edge) {
313 ir_node *proj = get_edge_src_irn(edge);
314 arch_set_irn_register(proj, NULL);
318 * We also have to re-build the insn since the input operands are now the Projs of
319 * the Perm. Recomputing liveness is also a good idea if a Perm is inserted, since
320 * the live sets may change.
322 obstack_free(env->obst, insn);
323 *the_insn = insn = chordal_scan_insn(env, insn->irn);
326 * Copy the input constraints of the insn to the Perm as output
327 * constraints. Succeeding phases (coalescing) will need that.
329 for (i = insn->use_start; i < insn->n_ops; ++i) {
330 be_operand_t *op = &insn->ops[i];
331 ir_node *proj = op->carrier;
333 * Note that the predecessor must not be a Proj of the Perm,
334 * since ignore-nodes are not Perm'ed.
336 if (op->has_constraints && is_Proj(proj) && get_Proj_pred(proj) == perm) {
337 be_set_constr_limited(perm, BE_OUT_POS(get_Proj_proj(proj)), op->req);
344 static ir_node *handle_constraints(be_chordal_alloc_env_t *alloc_env,
345 ir_node *irn, int *silent)
349 ir_node **alloc_nodes;
350 //hungarian_problem_t *bp;
355 const ir_edge_t *edge;
356 ir_node *perm = NULL;
357 //int match_res, cost;
358 be_chordal_env_t *env = alloc_env->chordal_env;
359 void *base = obstack_base(env->obst);
360 be_insn_t *insn = chordal_scan_insn(env, irn);
361 ir_node *res = insn->next_insn;
362 int be_silent = *silent;
365 if (insn->pre_colored) {
367 for (i = 0; i < insn->use_start; ++i)
368 pset_insert_ptr(alloc_env->pre_colored, insn->ops[i].carrier);
372 * If the current node is a barrier toggle the silent flag.
373 * If we are in the start block, we are ought to be silent at the beginning,
374 * so the toggling activates the constraint handling but skips the barrier.
375 * If we are in the end block we handle the in requirements of the barrier
376 * and set the rest to silent.
378 if (be_is_Barrier(irn))
385 * Perms inserted before the constraint handling phase are considered to be
386 * correctly precolored. These Perms arise during the ABI handling phase.
388 if (!insn->has_constraints)
391 n_regs = env->cls->n_regs;
392 bs = bitset_alloca(n_regs);
393 alloc_nodes = ALLOCAN(ir_node*, n_regs);
394 //bp = hungarian_new(n_regs, n_regs, 2, HUNGARIAN_MATCH_PERFECT);
395 bp = bipartite_new(n_regs, n_regs);
396 assignment = ALLOCAN(int, n_regs);
397 partners = pmap_create();
400 * prepare the constraint handling of this node.
401 * Perms are constructed and Copies are created for constrained values
402 * interfering with the instruction.
404 perm = pre_process_constraints(alloc_env, &insn);
406 /* find suitable in operands to the out operands of the node. */
407 pair_up_operands(alloc_env, insn);
410 * look at the in/out operands and add each operand (and its possible partner)
411 * to a bipartite graph (left: nodes with partners, right: admissible colors).
413 for (i = 0, n_alloc = 0; i < insn->n_ops; ++i) {
414 be_operand_t *op = &insn->ops[i];
417 * If the operand has no partner or the partner has not been marked
418 * for allocation, determine the admissible registers and mark it
419 * for allocation by associating the node and its partner with the
420 * set of admissible registers via a bipartite graph.
422 if (!op->partner || !pmap_contains(partners, op->partner->carrier)) {
423 ir_node *partner = op->partner ? op->partner->carrier : NULL;
426 pmap_insert(partners, op->carrier, partner);
428 pmap_insert(partners, partner, op->carrier);
430 /* don't insert a node twice */
431 for (i = 0; i < n_alloc; ++i) {
432 if (alloc_nodes[i] == op->carrier) {
439 alloc_nodes[n_alloc] = op->carrier;
441 DBG((dbg, LEVEL_2, "\tassociating %+F and %+F\n", op->carrier,
444 bitset_clear_all(bs);
445 get_decisive_partner_regs(bs, op, op->partner);
447 DBG((dbg, LEVEL_2, "\tallowed registers for %+F: %B\n", op->carrier,
450 bitset_foreach(bs, col) {
451 //hungarian_add(bp, n_alloc, col, 1);
452 bipartite_add(bp, n_alloc, col);
460 * Put all nodes which live through the constrained instruction also to the
461 * allocation bipartite graph. They are considered unconstrained.
464 foreach_out_edge(perm, edge) {
466 ir_node *proj = get_edge_src_irn(edge);
468 assert(is_Proj(proj));
470 if (!be_values_interfere(env->birg->lv, proj, irn)
471 || pmap_contains(partners, proj))
474 /* don't insert a node twice */
475 for (i = 0; i < n_alloc; ++i) {
476 if (alloc_nodes[i] == proj) {
484 assert(n_alloc < n_regs);
486 alloc_nodes[n_alloc] = proj;
487 pmap_insert(partners, proj, NULL);
489 bitset_clear_all(bs);
490 arch_put_non_ignore_regs(env->cls, bs);
491 bitset_andnot(bs, env->ignore_colors);
492 bitset_foreach(bs, col) {
493 //hungarian_add(bp, n_alloc, col, 1);
494 bipartite_add(bp, n_alloc, col);
501 /* Compute a valid register allocation. */
503 hungarian_prepare_cost_matrix(bp, HUNGARIAN_MODE_MAXIMIZE_UTIL);
504 match_res = hungarian_solve(bp, assignment, &cost, 1);
505 assert(match_res == 0 && "matching failed");
507 bipartite_matching(bp, assignment);
510 /* Assign colors obtained from the matching. */
511 for (i = 0; i < n_alloc; ++i) {
512 const arch_register_t *reg;
515 assert(assignment[i] >= 0 && "there must have been a register assigned");
516 reg = arch_register_for_index(env->cls, assignment[i]);
517 assert(! (reg->type & arch_register_type_ignore));
519 irn = alloc_nodes[i];
521 arch_set_irn_register(irn, reg);
522 (void) pset_hinsert_ptr(alloc_env->pre_colored, irn);
523 DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", irn, reg->name));
526 irn = pmap_get(partners, alloc_nodes[i]);
528 arch_set_irn_register(irn, reg);
529 (void) pset_hinsert_ptr(alloc_env->pre_colored, irn);
530 DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", irn, reg->name));
534 /* Allocate the non-constrained Projs of the Perm. */
536 bitset_clear_all(bs);
538 /* Put the colors of all Projs in a bitset. */
539 foreach_out_edge(perm, edge) {
540 ir_node *proj = get_edge_src_irn(edge);
541 const arch_register_t *reg = arch_get_irn_register(proj);
544 bitset_set(bs, reg->index);
547 /* Assign the not yet assigned Projs of the Perm a suitable color. */
548 foreach_out_edge(perm, edge) {
549 ir_node *proj = get_edge_src_irn(edge);
550 const arch_register_t *reg = arch_get_irn_register(proj);
552 DBG((dbg, LEVEL_2, "\tchecking reg of %+F: %s\n", proj, reg ? reg->name : "<none>"));
555 col = get_next_free_reg(alloc_env, bs);
556 reg = arch_register_for_index(env->cls, col);
557 bitset_set(bs, reg->index);
558 arch_set_irn_register(proj, reg);
559 pset_insert_ptr(alloc_env->pre_colored, proj);
560 DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", proj, reg->name));
566 //hungarian_free(bp);
567 pmap_destroy(partners);
570 obstack_free(env->obst, base);
575 * Handle constraint nodes in each basic block.
576 * handle_constraints() inserts Perm nodes which perm
577 * over all values live at the constrained node right in front
578 * of the constrained node. These Perms signal a constrained node.
579 * For further comments, refer to handle_constraints().
581 static void constraints(ir_node *bl, void *data)
584 * Start silent in the start block.
585 * The silence remains until the first barrier is seen.
586 * Each other block is begun loud.
588 int silent = bl == get_irg_start_block(get_irn_irg(bl));
589 be_chordal_alloc_env_t *env = data;
593 * If the block is the start block search the barrier and
594 * start handling constraints from there.
596 for (irn = sched_first(bl); !sched_is_end(irn);) {
597 irn = handle_constraints(env, irn, &silent);
602 * Annotate the register pressure to the nodes and compute
603 * the liveness intervals.
604 * @param block The block to do it for.
605 * @param env_ptr The environment.
607 static void pressure(ir_node *block, void *env_ptr)
609 /* Convenience macro for a def */
610 #define border_def(irn, step, real) \
611 border_add(env, head, irn, step, pressure--, 1, real)
613 /* Convenience macro for a use */
614 #define border_use(irn, step, real) \
615 border_add(env, head, irn, step, ++pressure, 0, real)
617 be_chordal_alloc_env_t *alloc_env = env_ptr;
618 be_chordal_env_t *env = alloc_env->chordal_env;
619 bitset_t *live = alloc_env->live;
621 be_lv_t *lv = env->birg->lv;
626 unsigned pressure = 0;
627 struct list_head *head;
629 DBG((dbg, LEVEL_1, "Computing pressure in block %+F\n", block));
630 bitset_clear_all(live);
632 /* Set up the border list in the block info */
633 head = obstack_alloc(env->obst, sizeof(*head));
634 INIT_LIST_HEAD(head);
635 assert(pmap_get(env->border_heads, block) == NULL);
636 pmap_insert(env->border_heads, block, head);
639 * Make final uses of all values live out of the block.
640 * They are necessary to build up real intervals.
642 be_lv_foreach(lv, block, be_lv_state_end, i) {
643 ir_node *irn = be_lv_get_irn(lv, block, i);
644 if (has_reg_class(env, irn)) {
645 DBG((dbg, LEVEL_3, "\tMaking live: %+F/%d\n", irn, get_irn_idx(irn)));
646 bitset_set(live, get_irn_idx(irn));
647 border_use(irn, step, 0);
653 * Determine the last uses of a value inside the block, since they are
654 * relevant for the interval borders.
656 sched_foreach_reverse(block, irn) {
657 DBG((dbg, LEVEL_1, "\tinsn: %+F, pressure: %d\n", irn, pressure));
658 DBG((dbg, LEVEL_2, "\tlive: %B\n", live));
660 if (get_irn_mode(irn) == mode_T) {
661 const ir_edge_t *edge;
663 foreach_out_edge(irn, edge) {
664 ir_node *proj = get_edge_src_irn(edge);
667 * If the node defines some value, which can put into a
668 * register of the current class, make a border for it.
670 if (has_reg_class(env, proj)) {
671 int nr = get_irn_idx(proj);
673 bitset_clear(live, nr);
674 border_def(proj, step, 1);
680 * If the node defines some value, which can put into a
681 * register of the current class, make a border for it.
683 if (has_reg_class(env, irn)) {
684 int nr = get_irn_idx(irn);
686 bitset_clear(live, nr);
687 border_def(irn, step, 1);
691 * If the node is no phi node we can examine the uses.
694 for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
695 ir_node *op = get_irn_n(irn, i);
697 if (has_reg_class(env, op)) {
698 int nr = get_irn_idx(op);
699 const char *msg = "-";
701 if (!bitset_is_set(live, nr)) {
702 border_use(op, step, 1);
703 bitset_set(live, nr);
707 DBG((dbg, LEVEL_4, "\t\t%s pos: %d, use: %+F\n", msg, i, op));
714 bitset_foreach(live, elm) {
715 ir_node *irn = get_idx_irn(env->irg, elm);
716 if (be_is_live_in(lv, block, irn))
717 border_def(irn, step, 0);
721 static void assign(ir_node *block, void *env_ptr)
723 be_chordal_alloc_env_t *alloc_env = env_ptr;
724 be_chordal_env_t *env = alloc_env->chordal_env;
725 bitset_t *live = alloc_env->live;
726 bitset_t *colors = alloc_env->colors;
727 bitset_t *in_colors = alloc_env->in_colors;
728 struct list_head *head = get_block_border_head(env, block);
729 be_lv_t *lv = env->birg->lv;
735 bitset_clear_all(colors);
736 bitset_clear_all(live);
737 bitset_clear_all(in_colors);
739 DBG((dbg, LEVEL_4, "Assigning colors for block %+F\n", block));
740 DBG((dbg, LEVEL_4, "\tusedef chain for block\n"));
741 list_for_each_entry(border_t, b, head, list) {
742 DBG((dbg, LEVEL_4, "\t%s %+F/%d\n", b->is_def ? "def" : "use",
743 b->irn, get_irn_idx(b->irn)));
747 * Add initial defs for all values live in.
748 * Since their colors have already been assigned (The dominators were
749 * allocated before), we have to mark their colors as used also.
751 be_lv_foreach(lv, block, be_lv_state_in, idx) {
752 irn = be_lv_get_irn(lv, block, idx);
753 if (has_reg_class(env, irn)) {
754 const arch_register_t *reg = arch_get_irn_register(irn);
757 assert(reg && "Node must have been assigned a register");
758 col = arch_register_get_index(reg);
760 DBG((dbg, LEVEL_4, "%+F has reg %s\n", irn, reg->name));
762 /* Mark the color of the live in value as used. */
763 bitset_set(colors, col);
764 bitset_set(in_colors, col);
766 /* Mark the value live in. */
767 bitset_set(live, get_irn_idx(irn));
772 * Mind that the sequence of defs from back to front defines a perfect
773 * elimination order. So, coloring the definitions from first to last
776 list_for_each_entry_reverse(border_t, b, head, list) {
777 ir_node *irn = b->irn;
778 int nr = get_irn_idx(irn);
779 int ignore = arch_irn_is_ignore(irn);
782 * Assign a color, if it is a local def. Global defs already have a
785 if (b->is_def && !be_is_live_in(lv, block, irn)) {
786 const arch_register_t *reg;
789 if (ignore || pset_find_ptr(alloc_env->pre_colored, irn)) {
790 reg = arch_get_irn_register(irn);
792 assert(!bitset_is_set(colors, col) && "pre-colored register must be free");
794 col = get_next_free_reg(alloc_env, colors);
795 reg = arch_register_for_index(env->cls, col);
796 assert(arch_get_irn_register(irn) == NULL && "This node must not have been assigned a register yet");
797 assert(!arch_register_type_is(reg, ignore) && "Must not assign ignore register");
800 bitset_set(colors, col);
801 arch_set_irn_register(irn, reg);
803 DBG((dbg, LEVEL_1, "\tassigning register %s(%d) to %+F\n", arch_register_get_name(reg), col, irn));
805 assert(!bitset_is_set(live, nr) && "Value's definition must not have been encountered");
806 bitset_set(live, nr);
807 } else if (!b->is_def) {
808 /* Clear the color upon a use. */
809 const arch_register_t *reg = arch_get_irn_register(irn);
812 assert(reg && "Register must have been assigned");
814 col = arch_register_get_index(reg);
816 if (!arch_register_type_is(reg, ignore)) {
817 assert(bitset_is_set(live, nr) && "Cannot have a non live use");
821 bitset_clear(colors, col);
822 bitset_clear(live, nr);
827 void be_ra_chordal_color(be_chordal_env_t *chordal_env)
829 be_chordal_alloc_env_t env;
832 be_irg_t *birg = chordal_env->birg;
833 const arch_register_class_t *cls = chordal_env->cls;
835 int colors_n = arch_register_class_n_regs(cls);
836 ir_graph *irg = chordal_env->irg;
838 lv = be_assure_liveness(birg);
839 be_liveness_assure_sets(lv);
840 be_liveness_assure_chk(lv);
844 env.chordal_env = chordal_env;
845 env.colors_n = colors_n;
846 env.colors = bitset_alloca(colors_n);
847 env.tmp_colors = bitset_alloca(colors_n);
848 env.in_colors = bitset_alloca(colors_n);
849 env.pre_colored = pset_new_ptr_default();
851 BE_TIMER_PUSH(t_constr);
853 /* Handle register targeting constraints */
854 dom_tree_walk_irg(irg, constraints, NULL, &env);
856 if (chordal_env->opts->dump_flags & BE_CH_DUMP_CONSTR) {
857 snprintf(buf, sizeof(buf), "-%s-constr", chordal_env->cls->name);
858 be_dump(chordal_env->irg, buf, dump_ir_block_graph_sched);
861 BE_TIMER_POP(t_constr);
863 env.live = bitset_malloc(get_irg_last_idx(chordal_env->irg));
865 /* First, determine the pressure */
866 dom_tree_walk_irg(irg, pressure, NULL, &env);
868 /* Assign the colors */
869 dom_tree_walk_irg(irg, assign, NULL, &env);
871 if (chordal_env->opts->dump_flags & BE_CH_DUMP_TREE_INTV) {
873 ir_snprintf(buf, sizeof(buf), "ifg_%s_%F.eps", chordal_env->cls->name, irg);
874 plotter = new_plotter_ps(buf);
875 draw_interval_tree(&draw_chordal_def_opts, chordal_env, plotter);
876 plotter_free(plotter);
879 bitset_free(env.live);
880 del_pset(env.pre_colored);
883 void be_init_chordal(void)
885 FIRM_DBG_REGISTER(dbg, "firm.be.chordal");
888 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_chordal);