2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Processor architecture specification.
23 * @author Sebastian Hack
26 #ifndef FIRM_BE_BEARCH_H
27 #define FIRM_BE_BEARCH_H
31 #include "firm_types.h"
34 #include "raw_bitset.h"
43 typedef enum arch_register_class_flags_t {
44 arch_register_class_flag_none = 0,
45 /** don't do automatic register allocation for this class */
46 arch_register_class_flag_manual_ra = 1U << 0,
47 /** the register models an abstract state (example: fpu rounding mode) */
48 arch_register_class_flag_state = 1U << 1
49 } arch_register_class_flags_t;
51 typedef enum arch_register_type_t {
52 arch_register_type_none = 0,
53 /** The register must be saved by the caller upon a function call. It thus
54 * can be overwritten in the called function. */
55 arch_register_type_caller_save = 1U << 0,
56 /** The register must be saved by the caller upon a function call. It thus
57 * can be overwritten in the called function. */
58 arch_register_type_callee_save = 1U << 1,
59 /** Do not consider this register when allocating. */
60 arch_register_type_ignore = 1U << 2,
61 /** The emitter can choose an arbitrary register. The register fulfills any
62 * register constraints as long as the register class matches */
63 arch_register_type_joker = 1U << 3,
64 /** This is just a virtual register. Virtual registers fulfill any register
65 * constraints as long as the register class matches. It is a allowed to
66 * have multiple definitions for the same virtual register at a point */
67 arch_register_type_virtual = 1U << 4,
68 /** The register represents a state that should be handled by bestate
70 arch_register_type_state = 1U << 5,
71 } arch_register_type_t;
74 * Different types of register allocation requirements.
76 typedef enum arch_register_req_type_t {
77 /** No register requirement. */
78 arch_register_req_type_none = 0,
79 /** All registers in the class are allowed. */
80 arch_register_req_type_normal = 1U << 0,
81 /** Only a real subset of the class is allowed. */
82 arch_register_req_type_limited = 1U << 1,
83 /** The register should be equal to another one at the node. */
84 arch_register_req_type_should_be_same = 1U << 2,
85 /** The register must be unequal from some other at the node. */
86 arch_register_req_type_must_be_different = 1U << 3,
87 /** The registernumber should be aligned (in case of multiregister values)*/
88 arch_register_req_type_aligned = 1U << 4,
89 /** ignore while allocating registers */
90 arch_register_req_type_ignore = 1U << 5,
91 /** the output produces a new value for the stack pointer
92 * (this is not really a constraint but a marker to guide the stackpointer
94 arch_register_req_type_produces_sp = 1U << 6,
95 } arch_register_req_type_t;
97 extern const arch_register_req_t *arch_no_register_req;
100 * Print information about a register requirement in human readable form
101 * @param F output stream/file
102 * @param req The requirements structure to format.
104 void arch_dump_register_req(FILE *F, const arch_register_req_t *req,
105 const ir_node *node);
107 void arch_dump_register_reqs(FILE *F, const ir_node *node);
108 void arch_dump_reqs_and_registers(FILE *F, const ir_node *node);
111 * Node classification. Used for statistics and for detecting reload nodes.
113 typedef enum arch_irn_class_t {
114 arch_irn_class_spill = 1 << 0,
115 arch_irn_class_reload = 1 << 1,
116 arch_irn_class_remat = 1 << 2,
117 arch_irn_class_copy = 1 << 3,
118 arch_irn_class_perm = 1 << 4
121 void arch_set_frame_offset(ir_node *irn, int bias);
123 ir_entity *arch_get_frame_entity(const ir_node *irn);
124 int arch_get_sp_bias(ir_node *irn);
126 int arch_get_op_estimated_cost(const ir_node *irn);
127 arch_inverse_t *arch_get_inverse(const ir_node *irn, int i,
128 arch_inverse_t *inverse,
129 struct obstack *obstack);
130 int arch_possible_memory_operand(const ir_node *irn,
132 void arch_perform_memory_operand(ir_node *irn, ir_node *spill,
136 * Get the register requirements for a node.
137 * @note Deprecated API! Preferably use
138 * arch_get_in_register_req and
139 * arch_get_out_register_req.
141 * @param irn The node.
142 * @param pos The position of the operand you're interested in.
143 * @return A pointer to the register requirements. If NULL is returned, the
144 * operand was no register operand.
146 const arch_register_req_t *arch_get_register_req(const ir_node *irn, int pos);
149 * Put all registers which shall not be ignored by the register
150 * allocator in a bit set.
151 * @param cls The register class to consider.
152 * @param bs The bit set to put the registers to.
154 extern void arch_put_non_ignore_regs(const arch_register_class_t *cls,
158 * Check, if a register is assignable to an operand of a node.
159 * @param irn The node.
160 * @param pos The position of the operand.
161 * @param reg The register.
162 * @return 1, if the register might be allocated to the operand 0 if not.
164 int arch_reg_is_allocatable(const ir_node *irn, int pos,
165 const arch_register_t *reg);
167 #define arch_reg_out_is_allocatable(irn, reg) arch_reg_is_allocatable(irn, -1, reg)
170 * Get the register class of an operand of a node.
171 * @param irn The node.
172 * @param pos The position of the operand, -1 for the output.
173 * @return The register class of the operand or NULL, if
174 * operand is a non-register operand.
176 const arch_register_class_t *arch_get_irn_reg_class(const ir_node *irn,
179 #define arch_get_irn_reg_class_out(irn) arch_get_irn_reg_class(irn, -1)
182 * Get the register allocated at a certain output operand of a node.
183 * @param irn The node.
184 * @return The register allocated for this operand
186 const arch_register_t *arch_get_irn_register(const ir_node *irn);
187 const arch_register_t *arch_irn_get_register(const ir_node *irn, int pos);
190 * Set the register for a certain output operand.
191 * @param irn The node.
192 * @param reg The register.
194 void arch_set_irn_register(ir_node *irn, const arch_register_t *reg);
195 void arch_irn_set_register(ir_node *irn, int pos, const arch_register_t *reg);
199 * @param irn The node.
200 * @return A classification of the node.
202 arch_irn_class_t arch_irn_classify(const ir_node *irn);
205 * Get the flags of a node.
206 * @param irn The node.
209 arch_irn_flags_t arch_irn_get_flags(const ir_node *irn);
211 void arch_irn_set_flags(ir_node *node, arch_irn_flags_t flags);
212 void arch_irn_add_flags(ir_node *node, arch_irn_flags_t flags);
214 #define arch_irn_is(irn, flag) ((arch_irn_get_flags(irn) & arch_irn_flags_ ## flag) != 0)
217 * Get the operations of an irn.
218 * @param self The handler from which the method is invoked.
219 * @param irn Some node.
220 * @return Operations for that irn.
222 typedef const void *(arch_get_irn_ops_t)(const ir_node *irn);
225 * Initialize the architecture environment struct.
226 * @param isa The isa which shall be put into the environment.
227 * @param file_handle The file handle
228 * @return The environment.
230 extern arch_env_t *arch_env_init(const arch_isa_if_t *isa,
231 FILE *file_handle, be_main_env_t *main_env);
234 * Register an instruction set architecture
236 void be_register_isa_if(const char *name, const arch_isa_if_t *isa);
241 struct arch_register_t {
242 const char *name; /**< The name of the register. */
243 const arch_register_class_t *reg_class; /**< The class of the register */
244 unsigned index; /**< The index of the register in
246 arch_register_type_t type; /**< The type of the register. */
247 /** register constraint allowing just this register */
248 const arch_register_req_t *single_req;
251 static inline const arch_register_class_t *arch_register_get_class(
252 const arch_register_t *reg)
254 return reg->reg_class;
257 static inline unsigned arch_register_get_index(const arch_register_t *reg)
262 static inline const char *arch_register_get_name(const arch_register_t *reg)
268 * Convenience macro to check for register type.
269 * @param req A pointer to register.
270 * @param kind The kind of type to check for (see arch_register_type_t).
271 * @return 1, If register is of given kind, 0 if not.
273 #define arch_register_type_is(reg, kind) \
274 (((reg)->type & arch_register_type_ ## kind) != 0)
277 * A class of registers.
278 * Like general purpose or floating point.
280 struct arch_register_class_t {
281 unsigned index; /**< index of this register class */
282 const char *name; /**< The name of the register class.*/
283 unsigned n_regs; /**< Number of registers in this
285 ir_mode *mode; /**< The mode of the register class.*/
286 const arch_register_t *regs; /**< The array of registers. */
287 arch_register_class_flags_t flags; /**< register class flags. */
288 const arch_register_req_t *class_req;
291 /** return the number of registers in this register class */
292 #define arch_register_class_n_regs(cls) ((cls)->n_regs)
294 /** return the largest mode of this register class */
295 #define arch_register_class_mode(cls) ((cls)->mode)
297 /** return the name of this register class */
298 #define arch_register_class_name(cls) ((cls)->name)
300 /** return the index of this register class */
301 #define arch_register_class_index(cls) ((cls)->index)
303 /** return the register class flags */
304 #define arch_register_class_flags(cls) ((cls)->flags)
306 static inline const arch_register_t *arch_register_for_index(
307 const arch_register_class_t *cls, unsigned idx)
309 assert(idx < cls->n_regs);
310 return &cls->regs[idx];
314 * Convenience macro to check for set constraints.
315 * @param req A pointer to register requirements.
316 * @param kind The kind of constraint to check for
317 * (see arch_register_req_type_t).
318 * @return 1, If the kind of constraint is present, 0 if not.
320 #define arch_register_req_is(req, kind) \
321 (((req)->type & (arch_register_req_type_ ## kind)) != 0)
324 * Expresses requirements to register allocation for an operand.
326 struct arch_register_req_t {
327 arch_register_req_type_t type; /**< The type of the constraint. */
328 const arch_register_class_t *cls; /**< The register class this constraint
330 const unsigned *limited; /**< allowed register bitset */
331 unsigned other_same; /**< Bitmask of ins which should use the
332 same register (should_be_same). */
333 unsigned other_different; /**< Bitmask of ins which shall use a
335 (must_be_different) */
336 unsigned char width; /**< specifies how many sequential
337 registers are required */
340 static inline int reg_reqs_equal(const arch_register_req_t *req1,
341 const arch_register_req_t *req2)
346 if (req1->type != req2->type
347 || req1->cls != req2->cls
348 || req1->other_same != req2->other_same
349 || req1->other_different != req2->other_different)
352 if (req1->limited != NULL) {
355 if (req2->limited == NULL)
358 n_regs = arch_register_class_n_regs(req1->cls);
359 if (!rbitsets_equal(req1->limited, req2->limited, n_regs))
367 * An inverse operation returned by the backend
369 struct arch_inverse_t {
370 int n; /**< count of nodes returned in nodes array */
371 int costs; /**< costs of this remat */
373 /** nodes for this inverse operation. shall be in schedule order.
374 * last element is the target value */
378 struct arch_irn_ops_t {
382 * @param irn The node.
383 * @return A classification.
385 arch_irn_class_t (*classify)(const ir_node *irn);
388 * Get the entity on the stack frame this node depends on.
389 * @param irn The node in question.
390 * @return The entity on the stack frame or NULL, if the node does not have
391 * a stack frame entity.
393 ir_entity *(*get_frame_entity)(const ir_node *irn);
396 * Set the offset of a node carrying an entity on the stack frame.
397 * @param irn The node.
398 * @param offset The offset of the node's stack frame entity.
400 void (*set_frame_offset)(ir_node *irn, int offset);
403 * Returns the delta of the stackpointer for nodes that increment or
404 * decrement the stackpointer with a constant value. (push, pop
405 * nodes on most architectures).
406 * A positive value stands for an expanding stack area, a negative value for
409 * @param irn The node
410 * @return 0 if the stackpointer is not modified with a constant
411 * value, otherwise the increment/decrement value
413 int (*get_sp_bias)(const ir_node *irn);
416 * Returns an inverse operation which yields the i-th argument
417 * of the given node as result.
419 * @param irn The original operation
420 * @param i Index of the argument we want the inverse operation to
422 * @param inverse struct to be filled with the resulting inverse op
423 * @param obstack The obstack to use for allocation of the returned nodes
425 * @return The inverse operation or NULL if operation invertible
427 arch_inverse_t *(*get_inverse)(const ir_node *irn, int i,
428 arch_inverse_t *inverse,
429 struct obstack *obstack);
432 * Get the estimated cycle count for @p irn.
434 * @param irn The node.
435 * @return The estimated cycle count for this operation
437 int (*get_op_estimated_cost)(const ir_node *irn);
440 * Asks the backend whether operand @p i of @p irn can be loaded form memory
443 * @param irn The node.
444 * @param i Index of the argument we would like to know whether @p irn
445 * can load it form memory internally
446 * @return nonzero if argument can be loaded or zero otherwise
448 int (*possible_memory_operand)(const ir_node *irn, unsigned int i);
451 * Ask the backend to assimilate @p reload of operand @p i into @p irn.
453 * @param irn The node.
454 * @param spill The spill.
455 * @param i The position of the reload.
457 void (*perform_memory_operand)(ir_node *irn, ir_node *spill,
462 * The code generator interface.
464 struct arch_code_generator_if_t {
466 * Initialize the code generator.
468 * @return A newly created code generator.
470 void *(*init)(ir_graph *irg);
473 * return node used as base in pic code addresses
475 ir_node* (*get_pic_base)(void *self);
478 * Called before abi introduce.
480 void (*before_abi)(void *self);
483 * Called, when the graph is being normalized.
485 void (*prepare_graph)(void *self);
488 * Backend may provide an own spiller.
489 * This spiller needs to spill all register classes.
491 void (*spill)(void *self, ir_graph *irg);
494 * Called before register allocation.
496 void (*before_ra)(void *self);
499 * Called after register allocation.
501 void (*after_ra)(void *self);
504 * Called directly before done is called. This should be the last place
505 * where the irg is modified.
507 void (*finish)(void *self);
510 * Called after everything happened. This call should emit the final
511 * assembly code but avoid changing the irg.
512 * The code generator must also be de-allocated here.
514 void (*done)(void *self);
518 * helper macro: call function func from the code generator
519 * if it's implemented.
521 #define _arch_cg_call(cg, func) \
523 if((cg)->impl->func) \
524 (cg)->impl->func(cg); \
527 #define _arch_cg_call_env(cg, env, func) \
529 if((cg)->impl->func) \
530 (cg)->impl->func(cg, env); \
533 #define arch_code_generator_before_abi(cg) _arch_cg_call(cg, before_abi)
534 #define arch_code_generator_prepare_graph(cg) _arch_cg_call(cg, prepare_graph)
535 #define arch_code_generator_before_ra(cg) _arch_cg_call(cg, before_ra)
536 #define arch_code_generator_after_ra(cg) _arch_cg_call(cg, after_ra)
537 #define arch_code_generator_finish(cg) _arch_cg_call(cg, finish)
538 #define arch_code_generator_done(cg) _arch_cg_call(cg, done)
539 #define arch_code_generator_spill(cg, irg) _arch_cg_call_env(cg, irg, spill)
540 #define arch_code_generator_has_spiller(cg) ((cg)->impl->spill != NULL)
541 #define arch_code_generator_get_pic_base(cg) \
542 ((cg)->impl->get_pic_base != NULL ? (cg)->impl->get_pic_base(cg) : NULL)
545 * Code generator base class.
547 struct arch_code_generator_t {
548 const arch_code_generator_if_t *impl;
552 * Architecture interface.
554 struct arch_isa_if_t {
556 * Initialize the isa interface.
557 * @param file_handle the file handle to write the output to
558 * @return a new isa instance
560 arch_env_t *(*init)(FILE *file_handle);
563 * Free the isa instance.
565 void (*done)(void *self);
568 * Called directly after initialization. Backend should handle all
571 void (*handle_intrinsics)(void);
574 * Get the the number of register classes in the isa.
575 * @return The number of register classes.
577 unsigned (*get_n_reg_class)(void);
580 * Get the i-th register class.
581 * @param i The number of the register class.
582 * @return The register class.
584 const arch_register_class_t *(*get_reg_class)(unsigned i);
587 * Get the register class which shall be used to store a value of a given
589 * @param self The this pointer.
590 * @param mode The mode in question.
591 * @return A register class which can hold values of the given mode.
593 const arch_register_class_t *(*get_reg_class_for_mode)(const ir_mode *mode);
596 * Get the ABI restrictions for procedure calls.
597 * @param self The this pointer.
598 * @param call_type The call type of the method (procedure) in question.
599 * @param p The array of parameter locations to be filled.
601 void (*get_call_abi)(const void *self, ir_type *call_type,
605 * Get the code generator interface.
606 * @param self The this pointer.
607 * @return Some code generator interface.
609 const arch_code_generator_if_t *(*get_code_generator_if)(void *self);
612 * Get the list scheduler to use. There is already a selector given, the
613 * backend is free to modify and/or ignore it.
615 * @param self The isa object.
616 * @param selector The selector given by options.
617 * @return The list scheduler selector.
619 const list_sched_selector_t *(*get_list_sched_selector)(const void *self,
620 list_sched_selector_t *selector);
623 * Get the ILP scheduler to use.
624 * @param self The isa object.
625 * @return The ILP scheduler selector
627 const ilp_sched_selector_t *(*get_ilp_sched_selector)(const void *self);
630 * Get the necessary alignment for storing a register of given class.
631 * @param self The isa object.
632 * @param cls The register class.
633 * @return The alignment in bytes.
635 int (*get_reg_class_alignment)(const arch_register_class_t *cls);
638 * A "static" function, returns the frontend settings
639 * needed for this backend.
641 const backend_params *(*get_params)(void);
644 * Returns an 2-dim array of execution units, @p irn can be executed on.
645 * The first dimension is the type, the second the allowed units of this
647 * Each dimension is a NULL terminated list.
648 * @param self The isa object.
649 * @param irn The node.
650 * @return An array of allowed execution units.
652 * { unit1_of_tp1, ..., unitX1_of_tp1, NULL },
654 * { unit1_of_tpY, ..., unitXn_of_tpY, NULL },
658 const be_execution_unit_t ***(*get_allowed_execution_units)(
662 * Return the abstract machine for this isa.
663 * @param self The isa object.
665 const be_machine_t *(*get_machine)(const void *self);
668 * Return an ordered list of irgs where code should be generated for.
669 * If NULL is returned, all irg will be taken into account and they will be
670 * generated in an arbitrary order.
671 * @param self The isa object.
672 * @param irgs A flexible array ARR_F of length 0 where the backend can
673 * append the desired irgs.
674 * @return A flexible array ARR_F containing all desired irgs in the
677 ir_graph **(*get_backend_irg_list)(const void *self, ir_graph ***irgs);
680 * mark node as rematerialized
682 void (*mark_remat)(ir_node *node);
685 * parse an assembler constraint part and set flags according to its nature
686 * advances the *c pointer to point to the last parsed character (so if you
687 * parse a single character don't advance c)
689 asm_constraint_flags_t (*parse_asm_constraint)(const char **c);
692 * returns true if the string is a valid clobbered (register) in this
695 int (*is_valid_clobber)(const char *clobber);
698 #define arch_env_done(env) ((env)->impl->done(env))
699 #define arch_env_handle_intrinsics(env) \
700 do { if((env)->impl->handle_intrinsics != NULL) (env)->impl->handle_intrinsics(); } while(0)
701 #define arch_env_get_n_reg_class(env) ((env)->impl->get_n_reg_class())
702 #define arch_env_get_reg_class(env,i) ((env)->impl->get_reg_class(i))
703 #define arch_env_get_reg_class_for_mode(env,mode) ((env)->impl->get_reg_class_for_mode((mode)))
704 #define arch_env_get_call_abi(env,tp,abi) ((env)->impl->get_call_abi((env), (tp), (abi)))
705 #define arch_env_get_code_generator_if(env) ((env)->impl->get_code_generator_if((env)))
706 #define arch_env_get_list_sched_selector(env,selector) ((env)->impl->get_list_sched_selector((env), (selector)))
707 #define arch_env_get_ilp_sched_selector(env) ((env)->impl->get_ilp_sched_selector(env))
708 #define arch_env_get_reg_class_alignment(env,cls) ((env)->impl->get_reg_class_alignment((cls)))
709 #define arch_env_get_params(env) ((env)->impl->get_params())
710 #define arch_env_get_allowed_execution_units(env,irn) ((env)->impl->get_allowed_execution_units((irn)))
711 #define arch_env_get_machine(env) ((env)->impl->get_machine(env))
712 #define arch_env_get_backend_irg_list(env,irgs) ((env)->impl->get_backend_irg_list((env), (irgs)))
713 #define arch_env_parse_asm_constraint(env,c) ((env)->impl->parse_asm_constraint((c))
714 #define arch_env_is_valid_clobber(env,clobber) ((env)->impl->is_valid_clobber((clobber))
715 #define arch_env_mark_remat(env,node) \
716 do { if ((env)->impl->mark_remat != NULL) (env)->impl->mark_remat((node)); } while(0)
722 const arch_isa_if_t *impl;
723 const arch_register_t *sp; /**< The stack pointer register. */
724 const arch_register_t *bp; /**< The base pointer register. */
725 const arch_register_class_t *link_class; /**< The static link pointer
727 int stack_dir; /**< -1 for decreasing, 1 for
729 int stack_alignment; /**< power of 2 stack alignment */
730 const be_main_env_t *main_env; /**< the be main environment */
731 int spill_cost; /**< cost for a be_Spill node */
732 int reload_cost; /**< cost for a be_Reload node */
733 bool custom_abi : 1; /**< backend does all abi handling
734 and does not need the generic stuff
738 static inline unsigned arch_irn_get_n_outs(const ir_node *node)
740 backend_info_t *info = be_get_info(node);
741 if (info->out_infos == NULL)
744 return ARR_LEN(info->out_infos);
747 static inline const arch_irn_ops_t *get_irn_ops_simple(const ir_node *node)
749 const ir_op *ops = get_irn_op(node);
750 const arch_irn_ops_t *be_ops = get_op_ops(ops)->be_ops;
751 assert(!is_Proj(node));
755 static inline const arch_register_req_t *arch_get_register_req_out(
759 backend_info_t *info;
761 /* you have to query the Proj nodes for the constraints (or use
762 * arch_get_out_register_req. Querying a mode_T node and expecting
763 * arch_no_register_req is a bug in your code! */
764 assert(get_irn_mode(irn) != mode_T);
767 pos = get_Proj_proj(irn);
768 irn = get_Proj_pred(irn);
771 info = be_get_info(irn);
772 if (info->out_infos == NULL)
773 return arch_no_register_req;
775 return info->out_infos[pos].req;
778 static inline bool arch_irn_is_ignore(const ir_node *irn)
780 const arch_register_req_t *req = arch_get_register_req_out(irn);
781 return !!(req->type & arch_register_req_type_ignore);
784 static inline bool arch_irn_consider_in_reg_alloc(
785 const arch_register_class_t *cls, const ir_node *node)
787 const arch_register_req_t *req = arch_get_register_req_out(node);
790 !(req->type & arch_register_req_type_ignore);
794 * Get register constraints for an operand at position @p
796 static inline const arch_register_req_t *arch_get_in_register_req(
797 const ir_node *node, int pos)
799 const backend_info_t *info = be_get_info(node);
800 if (info->in_reqs == NULL)
801 return arch_no_register_req;
802 return info->in_reqs[pos];
806 * Get register constraint for a produced result (the @p pos result)
808 static inline const arch_register_req_t *arch_get_out_register_req(
809 const ir_node *node, int pos)
811 const backend_info_t *info = be_get_info(node);
812 if (info->out_infos == NULL)
813 return arch_no_register_req;
814 return info->out_infos[pos].req;
817 static inline void arch_set_out_register_req(ir_node *node, int pos,
818 const arch_register_req_t *req)
820 backend_info_t *info = be_get_info(node);
821 assert(pos < (int) arch_irn_get_n_outs(node));
822 info->out_infos[pos].req = req;
825 static inline void arch_set_in_register_reqs(ir_node *node,
826 const arch_register_req_t **in_reqs)
828 backend_info_t *info = be_get_info(node);
829 info->in_reqs = in_reqs;
832 static inline const arch_register_req_t **arch_get_in_register_reqs(
835 backend_info_t *info = be_get_info(node);
836 return info->in_reqs;
840 * Iterate over all values defined by an instruction.
841 * Only looks at values in a certain register class where the requirements
842 * are not marked as ignore.
843 * Executes @p code for each definition.
845 #define be_foreach_definition_(node, cls, value, code) \
847 if (get_irn_mode(node) == mode_T) { \
848 const ir_edge_t *edge_; \
849 foreach_out_edge(node, edge_) { \
850 const arch_register_req_t *req_; \
851 value = get_edge_src_irn(edge_); \
852 req_ = arch_get_register_req_out(value); \
853 if (req_->cls != cls) \
858 const arch_register_req_t *req_ = arch_get_register_req_out(node); \
860 if (req_->cls == cls) { \
866 #define be_foreach_definition(node, cls, value, code) \
867 be_foreach_definition_(node, cls, value, \
868 if (req_->type & arch_register_req_type_ignore) \