2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Processor architecture specification.
23 * @author Sebastian Hack
25 #ifndef FIRM_BE_BEARCH_H
26 #define FIRM_BE_BEARCH_H
30 #include "firm_types.h"
31 #include "raw_bitset.h"
38 * this constant is returned by the get_sp_bias functions if the stack
39 * is reset (usually because the frame pointer is copied to the stack
42 #define SP_BIAS_RESET INT_MIN
44 typedef enum arch_register_class_flags_t {
45 arch_register_class_flag_none = 0,
46 /** don't do automatic register allocation for this class */
47 arch_register_class_flag_manual_ra = 1U << 0,
48 /** the register models an abstract state (example: fpu rounding mode) */
49 arch_register_class_flag_state = 1U << 1
50 } arch_register_class_flags_t;
51 ENUM_BITSET(arch_register_class_flags_t)
53 typedef enum arch_register_type_t {
54 arch_register_type_none = 0,
55 /** Do not consider this register when allocating. */
56 arch_register_type_ignore = 1U << 0,
57 /** This is just a virtual register. Virtual registers fulfill any register
58 * constraints as long as the register class matches. It is a allowed to
59 * have multiple definitions for the same virtual register at a point */
60 arch_register_type_virtual = 1U << 1,
61 /** The register represents a state that should be handled by bestate
63 arch_register_type_state = 1U << 2,
64 } arch_register_type_t;
65 ENUM_BITSET(arch_register_type_t)
68 * Different types of register allocation requirements.
70 typedef enum arch_register_req_type_t {
71 /** No register requirement. */
72 arch_register_req_type_none = 0,
73 /** All registers in the class are allowed. */
74 arch_register_req_type_normal = 1U << 0,
75 /** Only a real subset of the class is allowed. */
76 arch_register_req_type_limited = 1U << 1,
77 /** The register should be equal to another one at the node. */
78 arch_register_req_type_should_be_same = 1U << 2,
79 /** The register must be unequal from some other at the node. */
80 arch_register_req_type_must_be_different = 1U << 3,
81 /** The registernumber should be aligned (in case of multiregister values)*/
82 arch_register_req_type_aligned = 1U << 4,
83 /** ignore while allocating registers */
84 arch_register_req_type_ignore = 1U << 5,
85 /** the output produces a new value for the stack pointer
86 * (this is not really a constraint but a marker to guide the stackpointer
88 arch_register_req_type_produces_sp = 1U << 6,
89 } arch_register_req_type_t;
90 ENUM_BITSET(arch_register_req_type_t)
92 extern arch_register_req_t const arch_no_requirement;
93 #define arch_no_register_req (&arch_no_requirement)
96 * Print information about a register requirement in human readable form
97 * @param F output stream/file
98 * @param req The requirements structure to format.
100 void arch_dump_register_req(FILE *F, const arch_register_req_t *req,
101 const ir_node *node);
103 void arch_dump_register_reqs(FILE *F, const ir_node *node);
104 void arch_dump_reqs_and_registers(FILE *F, const ir_node *node);
106 void arch_set_frame_offset(ir_node *irn, int bias);
108 ir_entity *arch_get_frame_entity(const ir_node *irn);
109 int arch_get_sp_bias(ir_node *irn);
111 int arch_get_op_estimated_cost(const ir_node *irn);
112 int arch_possible_memory_operand(const ir_node *irn,
114 void arch_perform_memory_operand(ir_node *irn, ir_node *spill,
118 * Get the register allocated for a value.
120 const arch_register_t *arch_get_irn_register(const ir_node *irn);
123 * Assign register to a value
125 void arch_set_irn_register(ir_node *irn, const arch_register_t *reg);
128 * Set the register for a certain output operand.
130 void arch_set_irn_register_out(ir_node *irn, unsigned pos, const arch_register_t *r);
132 const arch_register_t *arch_get_irn_register_out(const ir_node *irn, unsigned pos);
133 const arch_register_t *arch_get_irn_register_in(const ir_node *irn, int pos);
136 * Get register constraints for an operand at position @p
138 static inline const arch_register_req_t *arch_get_irn_register_req_in(
139 const ir_node *node, int pos)
141 const backend_info_t *info = be_get_info(node);
142 return info->in_reqs[pos];
146 * Get register constraint for a produced result (the @p pos result)
148 static inline const arch_register_req_t *arch_get_irn_register_req_out(
149 const ir_node *node, unsigned pos)
151 const backend_info_t *info = be_get_info(node);
152 return info->out_infos[pos].req;
155 static inline void arch_set_irn_register_req_out(ir_node *node, unsigned pos,
156 const arch_register_req_t *req)
158 backend_info_t *info = be_get_info(node);
159 assert(pos < (unsigned)ARR_LEN(info->out_infos));
160 info->out_infos[pos].req = req;
163 static inline void arch_set_irn_register_reqs_in(ir_node *node,
164 const arch_register_req_t **reqs)
166 backend_info_t *info = be_get_info(node);
167 info->in_reqs = reqs;
170 static inline const arch_register_req_t **arch_get_irn_register_reqs_in(
173 backend_info_t *info = be_get_info(node);
174 return info->in_reqs;
177 static inline reg_out_info_t *get_out_info(const ir_node *node)
180 const backend_info_t *info;
181 assert(get_irn_mode(node) != mode_T);
183 pos = get_Proj_proj(node);
184 node = get_Proj_pred(node);
187 info = be_get_info(node);
188 assert(pos < ARR_LEN(info->out_infos));
189 return &info->out_infos[pos];
192 static inline const arch_register_req_t *arch_get_irn_register_req(const ir_node *node)
194 reg_out_info_t *out = get_out_info(node);
199 * Get the flags of a node.
200 * @param irn The node.
203 static inline arch_irn_flags_t arch_get_irn_flags(const ir_node *node)
205 backend_info_t *info;
207 return arch_irn_flags_not_scheduled;
209 info = be_get_info(node);
213 void arch_set_irn_flags(ir_node *node, arch_irn_flags_t flags);
214 void arch_add_irn_flags(ir_node *node, arch_irn_flags_t flags);
216 #define arch_irn_is(irn, flag) ((arch_get_irn_flags(irn) & arch_irn_flags_ ## flag) != 0)
218 static inline unsigned arch_get_irn_n_outs(const ir_node *node)
220 backend_info_t *info = be_get_info(node);
221 if (info->out_infos == NULL)
224 return (unsigned)ARR_LEN(info->out_infos);
228 * Start codegeneration
230 arch_env_t *arch_env_begin_codegeneration(const arch_isa_if_t *isa,
231 be_main_env_t *main_env);
234 * Register an instruction set architecture
236 void be_register_isa_if(const char *name, const arch_isa_if_t *isa);
241 struct arch_register_t {
242 const char *name; /**< The name of the register. */
243 const arch_register_class_t *reg_class; /**< The class of the register */
244 unsigned short index; /**< The index of the register in
246 unsigned short global_index; /**< The global index this
247 register in the architecture. */
248 arch_register_type_t type; /**< The type of the register. */
249 /** register constraint allowing just this register */
250 const arch_register_req_t *single_req;
251 /** register number in dwarf debugging format */
252 unsigned short dwarf_number;
256 * A class of registers.
257 * Like general purpose or floating point.
259 struct arch_register_class_t {
260 unsigned index; /**< index of this register class */
261 const char *name; /**< The name of the register class.*/
262 unsigned n_regs; /**< Number of registers in this
264 ir_mode *mode; /**< The mode of the register class.*/
265 const arch_register_t *regs; /**< The array of registers. */
266 arch_register_class_flags_t flags; /**< register class flags. */
267 const arch_register_req_t *class_req;
270 /** return the number of registers in this register class */
271 #define arch_register_class_n_regs(cls) ((cls)->n_regs)
273 /** return the largest mode of this register class */
274 #define arch_register_class_mode(cls) ((cls)->mode)
276 /** return the name of this register class */
277 #define arch_register_class_name(cls) ((cls)->name)
279 /** return the index of this register class */
280 #define arch_register_class_index(cls) ((cls)->index)
282 /** return the register class flags */
283 #define arch_register_class_flags(cls) ((cls)->flags)
285 static inline const arch_register_t *arch_register_for_index(
286 const arch_register_class_t *cls, unsigned idx)
288 assert(idx < cls->n_regs);
289 return &cls->regs[idx];
293 * Convenience macro to check for set constraints.
294 * @param req A pointer to register requirements.
295 * @param kind The kind of constraint to check for
296 * (see arch_register_req_type_t).
297 * @return 1, If the kind of constraint is present, 0 if not.
299 #define arch_register_req_is(req, kind) \
300 (((req)->type & (arch_register_req_type_ ## kind)) != 0)
303 * Expresses requirements to register allocation for an operand.
305 struct arch_register_req_t {
306 arch_register_req_type_t type; /**< The type of the constraint. */
307 const arch_register_class_t *cls; /**< The register class this constraint
309 const unsigned *limited; /**< allowed register bitset
310 (in case of wide-values this is
311 only about the first register) */
312 unsigned other_same; /**< Bitmask of ins which should use the
313 same register (should_be_same). */
314 unsigned other_different; /**< Bitmask of ins which shall use a
316 (must_be_different) */
317 unsigned char width; /**< specifies how many sequential
318 registers are required */
321 static inline bool reg_reqs_equal(const arch_register_req_t *req1,
322 const arch_register_req_t *req2)
327 if (req1->type != req2->type ||
328 req1->cls != req2->cls ||
329 req1->other_same != req2->other_same ||
330 req1->other_different != req2->other_different ||
331 (req1->limited != NULL) != (req2->limited != NULL))
334 if (req1->limited != NULL) {
335 size_t const n_regs = arch_register_class_n_regs(req1->cls);
336 if (!rbitsets_equal(req1->limited, req2->limited, n_regs))
343 struct arch_irn_ops_t {
346 * Get the entity on the stack frame this node depends on.
347 * @param irn The node in question.
348 * @return The entity on the stack frame or NULL, if the node does not have
349 * a stack frame entity.
351 ir_entity *(*get_frame_entity)(const ir_node *irn);
354 * Set the offset of a node carrying an entity on the stack frame.
355 * @param irn The node.
356 * @param offset The offset of the node's stack frame entity.
358 void (*set_frame_offset)(ir_node *irn, int offset);
361 * Returns the delta of the stackpointer for nodes that increment or
362 * decrement the stackpointer with a constant value. (push, pop
363 * nodes on most architectures).
364 * A positive value stands for an expanding stack area, a negative value for
367 * @param irn The node
368 * @return 0 if the stackpointer is not modified with a constant
369 * value, otherwise the increment/decrement value
371 int (*get_sp_bias)(const ir_node *irn);
374 * Get the estimated cycle count for @p irn.
376 * @param irn The node.
377 * @return The estimated cycle count for this operation
379 int (*get_op_estimated_cost)(const ir_node *irn);
382 * Asks the backend whether operand @p i of @p irn can be loaded form memory
385 * @param irn The node.
386 * @param i Index of the argument we would like to know whether @p irn
387 * can load it form memory internally
388 * @return nonzero if argument can be loaded or zero otherwise
390 int (*possible_memory_operand)(const ir_node *irn, unsigned int i);
393 * Ask the backend to assimilate @p reload of operand @p i into @p irn.
395 * @param irn The node.
396 * @param spill The spill.
397 * @param i The position of the reload.
399 void (*perform_memory_operand)(ir_node *irn, ir_node *spill,
404 * Architecture interface.
406 struct arch_isa_if_t {
408 * Initializes the isa interface. This is necessary before calling any
409 * other functions from this interface.
414 * Fress resources allocated by this isa interface.
416 void (*finish)(void);
419 * Returns the frontend settings needed for this backend.
421 const backend_params *(*get_params)(void);
424 * lowers current program for target. See the documentation for
425 * be_lower_for_target() for details.
427 void (*lower_for_target)(void);
430 * parse an assembler constraint part and set flags according to its nature
431 * advances the *c pointer to point to the last parsed character (so if you
432 * parse a single character don't advance c)
434 asm_constraint_flags_t (*parse_asm_constraint)(const char **c);
437 * returns true if the string is a valid clobbered (register) in this
440 int (*is_valid_clobber)(const char *clobber);
443 * Start codegeneration
444 * @return a new isa instance
446 arch_env_t *(*begin_codegeneration)(const be_main_env_t *env);
449 * Free the isa instance.
451 void (*end_codegeneration)(void *self);
454 * Initialize the code generator for a graph
457 void (*init_graph)(ir_graph *irg);
460 * Get the ABI restrictions for procedure calls.
461 * @param call_type The call type of the method (procedure) in question.
462 * @param p The array of parameter locations to be filled.
464 void (*get_call_abi)(ir_type *call_type, be_abi_call_t *abi);
467 * mark node as rematerialized
469 void (*mark_remat)(ir_node *node);
472 * return node used as base in pic code addresses
474 ir_node* (*get_pic_base)(ir_graph *irg);
477 * Create a spill instruction. We assume that spill instructions
478 * do not need any additional registers and do not affect cpu-flags in any
480 * Construct a sequence of instructions after @p after (the resulting nodes
481 * are already scheduled).
482 * Returns a mode_M value which is used as input for a reload instruction.
484 ir_node *(*new_spill)(ir_node *value, ir_node *after);
487 * Create a reload instruction. We assume that reload instructions do not
488 * need any additional registers and do not affect cpu-flags in any way.
489 * Constructs a sequence of instruction before @p before (the resulting
490 * nodes are already scheduled). A rewiring of users is not performed in
492 * Returns a value representing the restored value.
494 ir_node *(*new_reload)(ir_node *value, ir_node *spilled_value,
498 * Checks if the given register is callee/caller saved.
499 * @deprecated, only necessary if backend still uses beabi functions
501 int (*register_saved_by)(const arch_register_t *reg, int callee);
504 * Called directly after initialization. Backend should handle all
507 void (*handle_intrinsics)(void);
510 * Called before abi introduce.
512 void (*before_abi)(ir_graph *irg);
515 * Called, when the graph is being normalized.
517 void (*prepare_graph)(ir_graph *irg);
520 * Called before register allocation.
522 void (*before_ra)(ir_graph *irg);
525 * Called directly before done is called. This should be the last place
526 * where the irg is modified.
528 void (*finish_graph)(ir_graph *irg);
531 * Called after everything happened. This call should emit the final
532 * assembly code but avoid changing the irg.
534 void (*emit)(ir_graph *irg);
537 #define arch_env_end_codegeneration(env) ((env)->impl->end_codegeneration(env))
538 #define arch_env_handle_intrinsics(env) \
539 do { if((env)->impl->handle_intrinsics != NULL) (env)->impl->handle_intrinsics(); } while(0)
540 #define arch_env_get_call_abi(env,tp,abi) ((env)->impl->get_call_abi((tp), (abi)))
541 #define arch_env_get_params(env) ((env)->impl->get_params())
542 #define arch_env_parse_asm_constraint(env,c) ((env)->impl->parse_asm_constraint((c))
543 #define arch_env_is_valid_clobber(env,clobber) ((env)->impl->is_valid_clobber((clobber))
544 #define arch_env_mark_remat(env,node) \
545 do { if ((env)->impl->mark_remat != NULL) (env)->impl->mark_remat((node)); } while(0)
547 #define arch_env_new_spill(env,value,after) ((env)->impl->new_spill(value, after))
548 #define arch_env_new_reload(env,value,spilled,before) ((env)->impl->new_reload(value, spilled, before))
554 const arch_isa_if_t *impl;
555 unsigned n_registers; /**< number of registers */
556 const arch_register_t *registers; /**< register array */
557 unsigned n_register_classes; /**< number of register classes*/
558 const arch_register_class_t *register_classes; /**< register classes */
559 const arch_register_t *sp; /**< The stack pointer register. */
560 const arch_register_t *bp; /**< The base pointer register. */
561 int stack_alignment; /**< power of 2 stack alignment */
562 const be_main_env_t *main_env; /**< the be main environment */
563 int spill_cost; /**< cost for a be_Spill node */
564 int reload_cost; /**< cost for a be_Reload node */
565 bool custom_abi : 1; /**< backend does all abi handling
566 and does not need the generic
567 stuff from beabi.h/.c */
570 static inline bool arch_irn_is_ignore(const ir_node *irn)
572 const arch_register_req_t *req = arch_get_irn_register_req(irn);
573 return arch_register_req_is(req, ignore);
576 static inline bool arch_irn_consider_in_reg_alloc(
577 const arch_register_class_t *cls, const ir_node *node)
579 const arch_register_req_t *req = arch_get_irn_register_req(node);
580 return req->cls == cls && !arch_register_req_is(req, ignore);
584 * Iterate over all values defined by an instruction.
585 * Only looks at values in a certain register class where the requirements
586 * are not marked as ignore.
587 * Executes @p code for each definition.
589 #define be_foreach_definition_(node, ccls, value, code) \
591 if (get_irn_mode(node) == mode_T) { \
592 foreach_out_edge(node, edge_) { \
593 ir_node *const value = get_edge_src_irn(edge_); \
594 arch_register_req_t const *const req_ = arch_get_irn_register_req(value); \
595 if (req_->cls != ccls) \
600 arch_register_req_t const *const req_ = arch_get_irn_register_req(node); \
601 ir_node *const value = node; \
602 if (req_->cls == ccls) { \
608 #define be_foreach_definition(node, ccls, value, code) \
609 be_foreach_definition_(node, ccls, value, \
610 if (arch_register_req_is(req_, ignore)) \
615 static inline const arch_register_class_t *arch_get_irn_reg_class(
618 const arch_register_req_t *req = arch_get_irn_register_req(node);
622 bool arch_reg_is_allocatable(const arch_register_req_t *req,
623 const arch_register_t *reg);