2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Processor architecture specification.
23 * @author Sebastian Hack
25 #ifndef FIRM_BE_BEARCH_H
26 #define FIRM_BE_BEARCH_H
30 #include "firm_types.h"
33 #include "raw_bitset.h"
43 * this constant is returned by the get_sp_bias functions if the stack
44 * is reset (usually because the frame pointer is copied to the stack
47 #define SP_BIAS_RESET INT_MIN
49 typedef enum arch_register_class_flags_t {
50 arch_register_class_flag_none = 0,
51 /** don't do automatic register allocation for this class */
52 arch_register_class_flag_manual_ra = 1U << 0,
53 /** the register models an abstract state (example: fpu rounding mode) */
54 arch_register_class_flag_state = 1U << 1
55 } arch_register_class_flags_t;
56 ENUM_BITSET(arch_register_class_flags_t)
58 typedef enum arch_register_type_t {
59 arch_register_type_none = 0,
60 /** Do not consider this register when allocating. */
61 arch_register_type_ignore = 1U << 0,
62 /** The emitter can choose an arbitrary register. The register fulfills any
63 * register constraints as long as the register class matches */
64 arch_register_type_joker = 1U << 1,
65 /** This is just a virtual register. Virtual registers fulfill any register
66 * constraints as long as the register class matches. It is a allowed to
67 * have multiple definitions for the same virtual register at a point */
68 arch_register_type_virtual = 1U << 2,
69 /** The register represents a state that should be handled by bestate
71 arch_register_type_state = 1U << 3,
72 } arch_register_type_t;
73 ENUM_BITSET(arch_register_type_t)
76 * Different types of register allocation requirements.
78 typedef enum arch_register_req_type_t {
79 /** No register requirement. */
80 arch_register_req_type_none = 0,
81 /** All registers in the class are allowed. */
82 arch_register_req_type_normal = 1U << 0,
83 /** Only a real subset of the class is allowed. */
84 arch_register_req_type_limited = 1U << 1,
85 /** The register should be equal to another one at the node. */
86 arch_register_req_type_should_be_same = 1U << 2,
87 /** The register must be unequal from some other at the node. */
88 arch_register_req_type_must_be_different = 1U << 3,
89 /** The registernumber should be aligned (in case of multiregister values)*/
90 arch_register_req_type_aligned = 1U << 4,
91 /** ignore while allocating registers */
92 arch_register_req_type_ignore = 1U << 5,
93 /** the output produces a new value for the stack pointer
94 * (this is not really a constraint but a marker to guide the stackpointer
96 arch_register_req_type_produces_sp = 1U << 6,
97 } arch_register_req_type_t;
98 ENUM_BITSET(arch_register_req_type_t)
100 extern const arch_register_req_t *arch_no_register_req;
103 * Print information about a register requirement in human readable form
104 * @param F output stream/file
105 * @param req The requirements structure to format.
107 void arch_dump_register_req(FILE *F, const arch_register_req_t *req,
108 const ir_node *node);
110 void arch_dump_register_reqs(FILE *F, const ir_node *node);
111 void arch_dump_reqs_and_registers(FILE *F, const ir_node *node);
113 void arch_set_frame_offset(ir_node *irn, int bias);
115 ir_entity *arch_get_frame_entity(const ir_node *irn);
116 int arch_get_sp_bias(ir_node *irn);
118 int arch_get_op_estimated_cost(const ir_node *irn);
119 arch_inverse_t *arch_get_inverse(const ir_node *irn, int i,
120 arch_inverse_t *inverse,
121 struct obstack *obstack);
122 int arch_possible_memory_operand(const ir_node *irn,
124 void arch_perform_memory_operand(ir_node *irn, ir_node *spill,
128 * Get the register allocated for a value.
130 const arch_register_t *arch_get_irn_register(const ir_node *irn);
133 * Assign register to a value
135 void arch_set_irn_register(ir_node *irn, const arch_register_t *reg);
138 * Set the register for a certain output operand.
140 void arch_set_irn_register_out(ir_node *irn, int pos, const arch_register_t *r);
142 const arch_register_t *arch_get_irn_register_out(const ir_node *irn, int pos);
143 const arch_register_t *arch_get_irn_register_in(const ir_node *irn, int pos);
146 * Get register constraints for an operand at position @p
148 static inline const arch_register_req_t *arch_get_irn_register_req_in(
149 const ir_node *node, int pos)
151 const backend_info_t *info = be_get_info(node);
152 if (info->in_reqs == NULL)
153 return arch_no_register_req;
154 return info->in_reqs[pos];
158 * Get register constraint for a produced result (the @p pos result)
160 static inline const arch_register_req_t *arch_get_irn_register_req_out(
161 const ir_node *node, int pos)
163 const backend_info_t *info = be_get_info(node);
164 if (info->out_infos == NULL)
165 return arch_no_register_req;
166 return info->out_infos[pos].req;
169 static inline void arch_set_irn_register_req_out(ir_node *node, int pos,
170 const arch_register_req_t *req)
172 backend_info_t *info = be_get_info(node);
173 assert(pos < (int)ARR_LEN(info->out_infos));
174 info->out_infos[pos].req = req;
177 static inline void arch_set_irn_register_reqs_in(ir_node *node,
178 const arch_register_req_t **reqs)
180 backend_info_t *info = be_get_info(node);
181 info->in_reqs = reqs;
184 static inline const arch_register_req_t **arch_get_irn_register_reqs_in(
187 backend_info_t *info = be_get_info(node);
188 return info->in_reqs;
191 const arch_register_req_t *arch_get_irn_register_req(const ir_node *node);
194 * Get the flags of a node.
195 * @param irn The node.
198 arch_irn_flags_t arch_get_irn_flags(const ir_node *irn);
200 void arch_set_irn_flags(ir_node *node, arch_irn_flags_t flags);
201 void arch_add_irn_flags(ir_node *node, arch_irn_flags_t flags);
203 #define arch_irn_is(irn, flag) ((arch_get_irn_flags(irn) & arch_irn_flags_ ## flag) != 0)
205 static inline unsigned arch_get_irn_n_outs(const ir_node *node)
207 backend_info_t *info = be_get_info(node);
208 if (info->out_infos == NULL)
211 return (unsigned)ARR_LEN(info->out_infos);
215 * Initialize the architecture environment struct.
216 * @param isa The isa which shall be put into the environment.
217 * @param file_handle The file handle
218 * @return The environment.
220 extern arch_env_t *arch_env_init(const arch_isa_if_t *isa,
221 be_main_env_t *main_env);
224 * Register an instruction set architecture
226 void be_register_isa_if(const char *name, const arch_isa_if_t *isa);
231 struct arch_register_t {
232 const char *name; /**< The name of the register. */
233 const arch_register_class_t *reg_class; /**< The class of the register */
234 unsigned short index; /**< The index of the register in
236 unsigned short global_index; /** The global index this register
237 in the architecture. */
238 arch_register_type_t type; /**< The type of the register. */
239 /** register constraint allowing just this register */
240 const arch_register_req_t *single_req;
243 static inline const arch_register_class_t *arch_register_get_class(
244 const arch_register_t *reg)
246 return reg->reg_class;
249 static inline unsigned arch_register_get_index(const arch_register_t *reg)
254 static inline const char *arch_register_get_name(const arch_register_t *reg)
260 * A class of registers.
261 * Like general purpose or floating point.
263 struct arch_register_class_t {
264 unsigned index; /**< index of this register class */
265 const char *name; /**< The name of the register class.*/
266 unsigned n_regs; /**< Number of registers in this
268 ir_mode *mode; /**< The mode of the register class.*/
269 const arch_register_t *regs; /**< The array of registers. */
270 arch_register_class_flags_t flags; /**< register class flags. */
271 const arch_register_req_t *class_req;
274 /** return the number of registers in this register class */
275 #define arch_register_class_n_regs(cls) ((cls)->n_regs)
277 /** return the largest mode of this register class */
278 #define arch_register_class_mode(cls) ((cls)->mode)
280 /** return the name of this register class */
281 #define arch_register_class_name(cls) ((cls)->name)
283 /** return the index of this register class */
284 #define arch_register_class_index(cls) ((cls)->index)
286 /** return the register class flags */
287 #define arch_register_class_flags(cls) ((cls)->flags)
289 static inline const arch_register_t *arch_register_for_index(
290 const arch_register_class_t *cls, unsigned idx)
292 assert(idx < cls->n_regs);
293 return &cls->regs[idx];
297 * Convenience macro to check for set constraints.
298 * @param req A pointer to register requirements.
299 * @param kind The kind of constraint to check for
300 * (see arch_register_req_type_t).
301 * @return 1, If the kind of constraint is present, 0 if not.
303 #define arch_register_req_is(req, kind) \
304 (((req)->type & (arch_register_req_type_ ## kind)) != 0)
307 * Expresses requirements to register allocation for an operand.
309 struct arch_register_req_t {
310 arch_register_req_type_t type; /**< The type of the constraint. */
311 const arch_register_class_t *cls; /**< The register class this constraint
313 const unsigned *limited; /**< allowed register bitset */
314 unsigned other_same; /**< Bitmask of ins which should use the
315 same register (should_be_same). */
316 unsigned other_different; /**< Bitmask of ins which shall use a
318 (must_be_different) */
319 unsigned char width; /**< specifies how many sequential
320 registers are required */
323 static inline bool reg_reqs_equal(const arch_register_req_t *req1,
324 const arch_register_req_t *req2)
329 if (req1->type != req2->type ||
330 req1->cls != req2->cls ||
331 req1->other_same != req2->other_same ||
332 req1->other_different != req2->other_different ||
333 (req1->limited != NULL) != (req2->limited != NULL))
336 if (req1->limited != NULL) {
337 size_t const n_regs = arch_register_class_n_regs(req1->cls);
338 if (!rbitsets_equal(req1->limited, req2->limited, n_regs))
346 * An inverse operation returned by the backend
348 struct arch_inverse_t {
349 int n; /**< count of nodes returned in nodes array */
350 int costs; /**< costs of this remat */
352 /** nodes for this inverse operation. shall be in schedule order.
353 * last element is the target value */
357 struct arch_irn_ops_t {
360 * Get the entity on the stack frame this node depends on.
361 * @param irn The node in question.
362 * @return The entity on the stack frame or NULL, if the node does not have
363 * a stack frame entity.
365 ir_entity *(*get_frame_entity)(const ir_node *irn);
368 * Set the offset of a node carrying an entity on the stack frame.
369 * @param irn The node.
370 * @param offset The offset of the node's stack frame entity.
372 void (*set_frame_offset)(ir_node *irn, int offset);
375 * Returns the delta of the stackpointer for nodes that increment or
376 * decrement the stackpointer with a constant value. (push, pop
377 * nodes on most architectures).
378 * A positive value stands for an expanding stack area, a negative value for
381 * @param irn The node
382 * @return 0 if the stackpointer is not modified with a constant
383 * value, otherwise the increment/decrement value
385 int (*get_sp_bias)(const ir_node *irn);
388 * Returns an inverse operation which yields the i-th argument
389 * of the given node as result.
391 * @param irn The original operation
392 * @param i Index of the argument we want the inverse operation to
394 * @param inverse struct to be filled with the resulting inverse op
395 * @param obstack The obstack to use for allocation of the returned nodes
397 * @return The inverse operation or NULL if operation invertible
399 arch_inverse_t *(*get_inverse)(const ir_node *irn, int i,
400 arch_inverse_t *inverse,
401 struct obstack *obstack);
404 * Get the estimated cycle count for @p irn.
406 * @param irn The node.
407 * @return The estimated cycle count for this operation
409 int (*get_op_estimated_cost)(const ir_node *irn);
412 * Asks the backend whether operand @p i of @p irn can be loaded form memory
415 * @param irn The node.
416 * @param i Index of the argument we would like to know whether @p irn
417 * can load it form memory internally
418 * @return nonzero if argument can be loaded or zero otherwise
420 int (*possible_memory_operand)(const ir_node *irn, unsigned int i);
423 * Ask the backend to assimilate @p reload of operand @p i into @p irn.
425 * @param irn The node.
426 * @param spill The spill.
427 * @param i The position of the reload.
429 void (*perform_memory_operand)(ir_node *irn, ir_node *spill,
434 * Architecture interface.
436 struct arch_isa_if_t {
438 * Initialize the isa interface.
439 * @param file_handle the file handle to write the output to
440 * @return a new isa instance
442 arch_env_t *(*init)(const be_main_env_t *env);
445 * lowers current program for target. See the documentation for
446 * be_lower_for_target() for details.
448 void (*lower_for_target)(void);
451 * Free the isa instance.
453 void (*done)(void *self);
456 * Called directly after initialization. Backend should handle all
459 void (*handle_intrinsics)(void);
462 * Get the ABI restrictions for procedure calls.
463 * @param call_type The call type of the method (procedure) in question.
464 * @param p The array of parameter locations to be filled.
466 void (*get_call_abi)(ir_type *call_type, be_abi_call_t *abi);
469 * A "static" function, returns the frontend settings
470 * needed for this backend.
472 const backend_params *(*get_params)(void);
475 * mark node as rematerialized
477 void (*mark_remat)(ir_node *node);
480 * parse an assembler constraint part and set flags according to its nature
481 * advances the *c pointer to point to the last parsed character (so if you
482 * parse a single character don't advance c)
484 asm_constraint_flags_t (*parse_asm_constraint)(const char **c);
487 * returns true if the string is a valid clobbered (register) in this
490 int (*is_valid_clobber)(const char *clobber);
493 * Initialize the code generator.
495 * @return A newly created code generator.
497 void (*init_graph)(ir_graph *irg);
500 * return node used as base in pic code addresses
502 ir_node* (*get_pic_base)(ir_graph *irg);
505 * Called before abi introduce.
507 void (*before_abi)(ir_graph *irg);
510 * Called, when the graph is being normalized.
512 void (*prepare_graph)(ir_graph *irg);
515 * Called before register allocation.
517 void (*before_ra)(ir_graph *irg);
520 * Called directly before done is called. This should be the last place
521 * where the irg is modified.
523 void (*finish)(ir_graph *irg);
526 * Called after everything happened. This call should emit the final
527 * assembly code but avoid changing the irg.
528 * The code generator must also be de-allocated here.
530 void (*emit)(ir_graph *irg);
533 * Checks if the given register is callee/caller saved.
534 * @deprecated, only necessary if backend still uses beabi functions
536 int (*register_saved_by)(const arch_register_t *reg, int callee);
539 * Create a spill instruction. We assume that spill instructions
540 * do not need any additional registers and do not affect cpu-flags in any
542 * Construct a sequence of instructions after @p after (the resulting nodes
543 * are already scheduled).
544 * Returns a mode_M value which is used as input for a reload instruction.
546 ir_node *(*new_spill)(ir_node *value, ir_node *after);
549 * Create a reload instruction. We assume that reload instructions do not
550 * need any additional registers and do not affect cpu-flags in any way.
551 * Constructs a sequence of instruction before @p before (the resulting
552 * nodes are already scheduled). A rewiring of users is not performed in
554 * Returns a value representing the restored value.
556 ir_node *(*new_reload)(ir_node *value, ir_node *spilled_value,
560 #define arch_env_done(env) ((env)->impl->done(env))
561 #define arch_env_handle_intrinsics(env) \
562 do { if((env)->impl->handle_intrinsics != NULL) (env)->impl->handle_intrinsics(); } while(0)
563 #define arch_env_get_call_abi(env,tp,abi) ((env)->impl->get_call_abi((tp), (abi)))
564 #define arch_env_get_params(env) ((env)->impl->get_params())
565 #define arch_env_parse_asm_constraint(env,c) ((env)->impl->parse_asm_constraint((c))
566 #define arch_env_is_valid_clobber(env,clobber) ((env)->impl->is_valid_clobber((clobber))
567 #define arch_env_mark_remat(env,node) \
568 do { if ((env)->impl->mark_remat != NULL) (env)->impl->mark_remat((node)); } while(0)
570 #define arch_env_new_spill(env,value,after) ((env)->impl->new_spill(value, after))
571 #define arch_env_new_reload(env,value,spilled,before) ((env)->impl->new_reload(value, spilled, before))
577 const arch_isa_if_t *impl;
578 unsigned n_registers; /**< number of registers */
579 const arch_register_t *registers; /**< register array */
580 unsigned n_register_classes; /**< number of register classes*/
581 const arch_register_class_t *register_classes; /**< register classes */
582 const arch_register_t *sp; /**< The stack pointer register. */
583 const arch_register_t *bp; /**< The base pointer register. */
584 const arch_register_class_t *link_class; /**< The static link pointer
586 int stack_alignment; /**< power of 2 stack alignment */
587 const be_main_env_t *main_env; /**< the be main environment */
588 int spill_cost; /**< cost for a be_Spill node */
589 int reload_cost; /**< cost for a be_Reload node */
590 bool custom_abi : 1; /**< backend does all abi handling
591 and does not need the generic
592 stuff from beabi.h/.c */
595 static inline bool arch_irn_is_ignore(const ir_node *irn)
597 const arch_register_req_t *req = arch_get_irn_register_req(irn);
598 return req->type & arch_register_req_type_ignore;
601 static inline bool arch_irn_consider_in_reg_alloc(
602 const arch_register_class_t *cls, const ir_node *node)
604 const arch_register_req_t *req = arch_get_irn_register_req(node);
607 !(req->type & arch_register_req_type_ignore);
611 * Iterate over all values defined by an instruction.
612 * Only looks at values in a certain register class where the requirements
613 * are not marked as ignore.
614 * Executes @p code for each definition.
616 #define be_foreach_definition_(node, cls, value, code) \
618 if (get_irn_mode(node) == mode_T) { \
619 const ir_edge_t *edge_; \
620 foreach_out_edge(node, edge_) { \
621 const arch_register_req_t *req_; \
622 value = get_edge_src_irn(edge_); \
623 req_ = arch_get_irn_register_req(value); \
624 if (req_->cls != cls) \
629 const arch_register_req_t *req_ = arch_get_irn_register_req(node); \
631 if (req_->cls == cls) { \
637 #define be_foreach_definition(node, cls, value, code) \
638 be_foreach_definition_(node, cls, value, \
639 if (req_->type & arch_register_req_type_ignore) \
644 static inline const arch_register_class_t *arch_get_irn_reg_class(
647 const arch_register_req_t *req = arch_get_irn_register_req(node);
651 bool arch_reg_is_allocatable(const arch_register_req_t *req,
652 const arch_register_t *reg);