2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Processor architecture specification.
23 * @author Sebastian Hack
25 #ifndef FIRM_BE_BEARCH_H
26 #define FIRM_BE_BEARCH_H
30 #include "firm_types.h"
32 #include "raw_bitset.h"
39 * this constant is returned by the get_sp_bias functions if the stack
40 * is reset (usually because the frame pointer is copied to the stack
43 #define SP_BIAS_RESET INT_MIN
45 typedef enum arch_register_class_flags_t {
46 arch_register_class_flag_none = 0,
47 /** don't do automatic register allocation for this class */
48 arch_register_class_flag_manual_ra = 1U << 0,
49 /** the register models an abstract state (example: fpu rounding mode) */
50 arch_register_class_flag_state = 1U << 1
51 } arch_register_class_flags_t;
52 ENUM_BITSET(arch_register_class_flags_t)
54 typedef enum arch_register_type_t {
55 arch_register_type_none = 0,
56 /** Do not consider this register when allocating. */
57 arch_register_type_ignore = 1U << 0,
58 /** This is just a virtual register. Virtual registers fulfill any register
59 * constraints as long as the register class matches. It is a allowed to
60 * have multiple definitions for the same virtual register at a point */
61 arch_register_type_virtual = 1U << 1,
62 /** The register represents a state that should be handled by bestate
64 arch_register_type_state = 1U << 2,
65 } arch_register_type_t;
66 ENUM_BITSET(arch_register_type_t)
69 * Different types of register allocation requirements.
71 typedef enum arch_register_req_type_t {
72 /** No register requirement. */
73 arch_register_req_type_none = 0,
74 /** All registers in the class are allowed. */
75 arch_register_req_type_normal = 1U << 0,
76 /** Only a real subset of the class is allowed. */
77 arch_register_req_type_limited = 1U << 1,
78 /** The register should be equal to another one at the node. */
79 arch_register_req_type_should_be_same = 1U << 2,
80 /** The register must be unequal from some other at the node. */
81 arch_register_req_type_must_be_different = 1U << 3,
82 /** The registernumber should be aligned (in case of multiregister values)*/
83 arch_register_req_type_aligned = 1U << 4,
84 /** ignore while allocating registers */
85 arch_register_req_type_ignore = 1U << 5,
86 /** the output produces a new value for the stack pointer
87 * (this is not really a constraint but a marker to guide the stackpointer
89 arch_register_req_type_produces_sp = 1U << 6,
90 } arch_register_req_type_t;
91 ENUM_BITSET(arch_register_req_type_t)
93 extern arch_register_req_t const arch_no_requirement;
94 #define arch_no_register_req (&arch_no_requirement)
97 * Print information about a register requirement in human readable form
98 * @param F output stream/file
99 * @param req The requirements structure to format.
101 void arch_dump_register_req(FILE *F, const arch_register_req_t *req,
102 const ir_node *node);
104 void arch_dump_register_reqs(FILE *F, const ir_node *node);
105 void arch_dump_reqs_and_registers(FILE *F, const ir_node *node);
107 void arch_set_frame_offset(ir_node *irn, int bias);
109 ir_entity *arch_get_frame_entity(const ir_node *irn);
110 int arch_get_sp_bias(ir_node *irn);
112 int arch_get_op_estimated_cost(const ir_node *irn);
113 int arch_possible_memory_operand(const ir_node *irn,
115 void arch_perform_memory_operand(ir_node *irn, ir_node *spill,
119 * Get the register allocated for a value.
121 const arch_register_t *arch_get_irn_register(const ir_node *irn);
124 * Assign register to a value
126 void arch_set_irn_register(ir_node *irn, const arch_register_t *reg);
129 * Set the register for a certain output operand.
131 void arch_set_irn_register_out(ir_node *irn, unsigned pos, const arch_register_t *r);
133 const arch_register_t *arch_get_irn_register_out(const ir_node *irn, unsigned pos);
134 const arch_register_t *arch_get_irn_register_in(const ir_node *irn, int pos);
137 * Get register constraints for an operand at position @p
139 static inline const arch_register_req_t *arch_get_irn_register_req_in(
140 const ir_node *node, int pos)
142 const backend_info_t *info = be_get_info(node);
143 return info->in_reqs[pos];
147 * Get register constraint for a produced result (the @p pos result)
149 static inline const arch_register_req_t *arch_get_irn_register_req_out(
150 const ir_node *node, unsigned pos)
152 const backend_info_t *info = be_get_info(node);
153 return info->out_infos[pos].req;
156 static inline void arch_set_irn_register_req_out(ir_node *node, unsigned pos,
157 const arch_register_req_t *req)
159 backend_info_t *info = be_get_info(node);
160 assert(pos < (unsigned)ARR_LEN(info->out_infos));
161 info->out_infos[pos].req = req;
164 static inline void arch_set_irn_register_reqs_in(ir_node *node,
165 const arch_register_req_t **reqs)
167 backend_info_t *info = be_get_info(node);
168 info->in_reqs = reqs;
171 static inline const arch_register_req_t **arch_get_irn_register_reqs_in(
174 backend_info_t *info = be_get_info(node);
175 return info->in_reqs;
178 const arch_register_req_t *arch_get_irn_register_req(const ir_node *node);
181 * Get the flags of a node.
182 * @param irn The node.
185 arch_irn_flags_t arch_get_irn_flags(const ir_node *irn);
187 void arch_set_irn_flags(ir_node *node, arch_irn_flags_t flags);
188 void arch_add_irn_flags(ir_node *node, arch_irn_flags_t flags);
190 #define arch_irn_is(irn, flag) ((arch_get_irn_flags(irn) & arch_irn_flags_ ## flag) != 0)
192 static inline unsigned arch_get_irn_n_outs(const ir_node *node)
194 backend_info_t *info = be_get_info(node);
195 if (info->out_infos == NULL)
198 return (unsigned)ARR_LEN(info->out_infos);
202 * Start codegeneration
204 arch_env_t *arch_env_begin_codegeneration(const arch_isa_if_t *isa,
205 be_main_env_t *main_env);
208 * Register an instruction set architecture
210 void be_register_isa_if(const char *name, const arch_isa_if_t *isa);
215 struct arch_register_t {
216 const char *name; /**< The name of the register. */
217 const arch_register_class_t *reg_class; /**< The class of the register */
218 unsigned short index; /**< The index of the register in
220 unsigned short global_index; /**< The global index this
221 register in the architecture. */
222 arch_register_type_t type; /**< The type of the register. */
223 /** register constraint allowing just this register */
224 const arch_register_req_t *single_req;
225 /** register number in dwarf debugging format */
226 unsigned short dwarf_number;
230 * A class of registers.
231 * Like general purpose or floating point.
233 struct arch_register_class_t {
234 unsigned index; /**< index of this register class */
235 const char *name; /**< The name of the register class.*/
236 unsigned n_regs; /**< Number of registers in this
238 ir_mode *mode; /**< The mode of the register class.*/
239 const arch_register_t *regs; /**< The array of registers. */
240 arch_register_class_flags_t flags; /**< register class flags. */
241 const arch_register_req_t *class_req;
244 /** return the number of registers in this register class */
245 #define arch_register_class_n_regs(cls) ((cls)->n_regs)
247 /** return the largest mode of this register class */
248 #define arch_register_class_mode(cls) ((cls)->mode)
250 /** return the name of this register class */
251 #define arch_register_class_name(cls) ((cls)->name)
253 /** return the index of this register class */
254 #define arch_register_class_index(cls) ((cls)->index)
256 /** return the register class flags */
257 #define arch_register_class_flags(cls) ((cls)->flags)
259 static inline const arch_register_t *arch_register_for_index(
260 const arch_register_class_t *cls, unsigned idx)
262 assert(idx < cls->n_regs);
263 return &cls->regs[idx];
267 * Convenience macro to check for set constraints.
268 * @param req A pointer to register requirements.
269 * @param kind The kind of constraint to check for
270 * (see arch_register_req_type_t).
271 * @return 1, If the kind of constraint is present, 0 if not.
273 #define arch_register_req_is(req, kind) \
274 (((req)->type & (arch_register_req_type_ ## kind)) != 0)
277 * Expresses requirements to register allocation for an operand.
279 struct arch_register_req_t {
280 arch_register_req_type_t type; /**< The type of the constraint. */
281 const arch_register_class_t *cls; /**< The register class this constraint
283 const unsigned *limited; /**< allowed register bitset
284 (in case of wide-values this is
285 only about the first register) */
286 unsigned other_same; /**< Bitmask of ins which should use the
287 same register (should_be_same). */
288 unsigned other_different; /**< Bitmask of ins which shall use a
290 (must_be_different) */
291 unsigned char width; /**< specifies how many sequential
292 registers are required */
295 static inline bool reg_reqs_equal(const arch_register_req_t *req1,
296 const arch_register_req_t *req2)
301 if (req1->type != req2->type ||
302 req1->cls != req2->cls ||
303 req1->other_same != req2->other_same ||
304 req1->other_different != req2->other_different ||
305 (req1->limited != NULL) != (req2->limited != NULL))
308 if (req1->limited != NULL) {
309 size_t const n_regs = arch_register_class_n_regs(req1->cls);
310 if (!rbitsets_equal(req1->limited, req2->limited, n_regs))
317 struct arch_irn_ops_t {
320 * Get the entity on the stack frame this node depends on.
321 * @param irn The node in question.
322 * @return The entity on the stack frame or NULL, if the node does not have
323 * a stack frame entity.
325 ir_entity *(*get_frame_entity)(const ir_node *irn);
328 * Set the offset of a node carrying an entity on the stack frame.
329 * @param irn The node.
330 * @param offset The offset of the node's stack frame entity.
332 void (*set_frame_offset)(ir_node *irn, int offset);
335 * Returns the delta of the stackpointer for nodes that increment or
336 * decrement the stackpointer with a constant value. (push, pop
337 * nodes on most architectures).
338 * A positive value stands for an expanding stack area, a negative value for
341 * @param irn The node
342 * @return 0 if the stackpointer is not modified with a constant
343 * value, otherwise the increment/decrement value
345 int (*get_sp_bias)(const ir_node *irn);
348 * Get the estimated cycle count for @p irn.
350 * @param irn The node.
351 * @return The estimated cycle count for this operation
353 int (*get_op_estimated_cost)(const ir_node *irn);
356 * Asks the backend whether operand @p i of @p irn can be loaded form memory
359 * @param irn The node.
360 * @param i Index of the argument we would like to know whether @p irn
361 * can load it form memory internally
362 * @return nonzero if argument can be loaded or zero otherwise
364 int (*possible_memory_operand)(const ir_node *irn, unsigned int i);
367 * Ask the backend to assimilate @p reload of operand @p i into @p irn.
369 * @param irn The node.
370 * @param spill The spill.
371 * @param i The position of the reload.
373 void (*perform_memory_operand)(ir_node *irn, ir_node *spill,
378 * Architecture interface.
380 struct arch_isa_if_t {
382 * Initializes the isa interface. This is necessary before calling any
383 * other functions from this interface.
388 * Fress resources allocated by this isa interface.
390 void (*finish)(void);
393 * Returns the frontend settings needed for this backend.
395 const backend_params *(*get_params)(void);
398 * lowers current program for target. See the documentation for
399 * be_lower_for_target() for details.
401 void (*lower_for_target)(void);
404 * parse an assembler constraint part and set flags according to its nature
405 * advances the *c pointer to point to the last parsed character (so if you
406 * parse a single character don't advance c)
408 asm_constraint_flags_t (*parse_asm_constraint)(const char **c);
411 * returns true if the string is a valid clobbered (register) in this
414 int (*is_valid_clobber)(const char *clobber);
417 * Start codegeneration
418 * @return a new isa instance
420 arch_env_t *(*begin_codegeneration)(const be_main_env_t *env);
423 * Free the isa instance.
425 void (*end_codegeneration)(void *self);
428 * Initialize the code generator for a graph
431 void (*init_graph)(ir_graph *irg);
434 * Get the ABI restrictions for procedure calls.
435 * @param call_type The call type of the method (procedure) in question.
436 * @param p The array of parameter locations to be filled.
438 void (*get_call_abi)(ir_type *call_type, be_abi_call_t *abi);
441 * mark node as rematerialized
443 void (*mark_remat)(ir_node *node);
446 * return node used as base in pic code addresses
448 ir_node* (*get_pic_base)(ir_graph *irg);
451 * Create a spill instruction. We assume that spill instructions
452 * do not need any additional registers and do not affect cpu-flags in any
454 * Construct a sequence of instructions after @p after (the resulting nodes
455 * are already scheduled).
456 * Returns a mode_M value which is used as input for a reload instruction.
458 ir_node *(*new_spill)(ir_node *value, ir_node *after);
461 * Create a reload instruction. We assume that reload instructions do not
462 * need any additional registers and do not affect cpu-flags in any way.
463 * Constructs a sequence of instruction before @p before (the resulting
464 * nodes are already scheduled). A rewiring of users is not performed in
466 * Returns a value representing the restored value.
468 ir_node *(*new_reload)(ir_node *value, ir_node *spilled_value,
472 * Checks if the given register is callee/caller saved.
473 * @deprecated, only necessary if backend still uses beabi functions
475 int (*register_saved_by)(const arch_register_t *reg, int callee);
478 * Called directly after initialization. Backend should handle all
481 void (*handle_intrinsics)(void);
484 * Called before abi introduce.
486 void (*before_abi)(ir_graph *irg);
489 * Called, when the graph is being normalized.
491 void (*prepare_graph)(ir_graph *irg);
494 * Called before register allocation.
496 void (*before_ra)(ir_graph *irg);
499 * Called directly before done is called. This should be the last place
500 * where the irg is modified.
502 void (*finish_graph)(ir_graph *irg);
505 * Called after everything happened. This call should emit the final
506 * assembly code but avoid changing the irg.
508 void (*emit)(ir_graph *irg);
511 #define arch_env_end_codegeneration(env) ((env)->impl->end_codegeneration(env))
512 #define arch_env_handle_intrinsics(env) \
513 do { if((env)->impl->handle_intrinsics != NULL) (env)->impl->handle_intrinsics(); } while(0)
514 #define arch_env_get_call_abi(env,tp,abi) ((env)->impl->get_call_abi((tp), (abi)))
515 #define arch_env_get_params(env) ((env)->impl->get_params())
516 #define arch_env_parse_asm_constraint(env,c) ((env)->impl->parse_asm_constraint((c))
517 #define arch_env_is_valid_clobber(env,clobber) ((env)->impl->is_valid_clobber((clobber))
518 #define arch_env_mark_remat(env,node) \
519 do { if ((env)->impl->mark_remat != NULL) (env)->impl->mark_remat((node)); } while(0)
521 #define arch_env_new_spill(env,value,after) ((env)->impl->new_spill(value, after))
522 #define arch_env_new_reload(env,value,spilled,before) ((env)->impl->new_reload(value, spilled, before))
528 const arch_isa_if_t *impl;
529 unsigned n_registers; /**< number of registers */
530 const arch_register_t *registers; /**< register array */
531 unsigned n_register_classes; /**< number of register classes*/
532 const arch_register_class_t *register_classes; /**< register classes */
533 const arch_register_t *sp; /**< The stack pointer register. */
534 const arch_register_t *bp; /**< The base pointer register. */
535 int stack_alignment; /**< power of 2 stack alignment */
536 const be_main_env_t *main_env; /**< the be main environment */
537 int spill_cost; /**< cost for a be_Spill node */
538 int reload_cost; /**< cost for a be_Reload node */
539 bool custom_abi : 1; /**< backend does all abi handling
540 and does not need the generic
541 stuff from beabi.h/.c */
544 static inline bool arch_irn_is_ignore(const ir_node *irn)
546 const arch_register_req_t *req = arch_get_irn_register_req(irn);
547 return req->type & arch_register_req_type_ignore;
550 static inline bool arch_irn_consider_in_reg_alloc(
551 const arch_register_class_t *cls, const ir_node *node)
553 const arch_register_req_t *req = arch_get_irn_register_req(node);
556 !(req->type & arch_register_req_type_ignore);
560 * Iterate over all values defined by an instruction.
561 * Only looks at values in a certain register class where the requirements
562 * are not marked as ignore.
563 * Executes @p code for each definition.
565 #define be_foreach_definition_(node, ccls, value, code) \
567 if (get_irn_mode(node) == mode_T) { \
568 foreach_out_edge(node, edge_) { \
569 ir_node *const value = get_edge_src_irn(edge_); \
570 arch_register_req_t const *const req_ = arch_get_irn_register_req(value); \
571 if (req_->cls != ccls) \
576 arch_register_req_t const *const req_ = arch_get_irn_register_req(node); \
577 ir_node *const value = node; \
578 if (req_->cls == ccls) { \
584 #define be_foreach_definition(node, ccls, value, code) \
585 be_foreach_definition_(node, ccls, value, \
586 if (req_->type & arch_register_req_type_ignore) \
591 static inline const arch_register_class_t *arch_get_irn_reg_class(
594 const arch_register_req_t *req = arch_get_irn_register_req(node);
598 bool arch_reg_is_allocatable(const arch_register_req_t *req,
599 const arch_register_t *reg);