2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Processor architecture specification.
23 * @author Sebastian Hack
26 #ifndef FIRM_BE_BEARCH_H
27 #define FIRM_BE_BEARCH_H
31 #include "firm_types.h"
34 #include "raw_bitset.h"
43 typedef enum arch_register_class_flags_t {
44 arch_register_class_flag_none = 0,
45 /** don't do automatic register allocation for this class */
46 arch_register_class_flag_manual_ra = 1U << 0,
47 /** the register models an abstract state (example: fpu rounding mode) */
48 arch_register_class_flag_state = 1U << 1
49 } arch_register_class_flags_t;
51 typedef enum arch_register_type_t {
52 arch_register_type_none = 0,
53 /** The register must be saved by the caller upon a function call. It thus
54 * can be overwritten in the called function. */
55 arch_register_type_caller_save = 1U << 0,
56 /** The register must be saved by the caller upon a function call. It thus
57 * can be overwritten in the called function. */
58 arch_register_type_callee_save = 1U << 1,
59 /** Do not consider this register when allocating. */
60 arch_register_type_ignore = 1U << 2,
61 /** The emitter can choose an arbitrary register. The register fulfills any
62 * register constraints as long as the register class matches */
63 arch_register_type_joker = 1U << 3,
64 /** This is just a virtual register. Virtual registers fulfill any register
65 * constraints as long as the register class matches. It is a allowed to
66 * have multiple definitions for the same virtual register at a point */
67 arch_register_type_virtual = 1U << 4,
68 /** The register represents a state that should be handled by bestate
70 arch_register_type_state = 1U << 5,
71 } arch_register_type_t;
74 * Different types of register allocation requirements.
76 typedef enum arch_register_req_type_t {
77 /** No register requirement. */
78 arch_register_req_type_none = 0,
79 /** All registers in the class are allowed. */
80 arch_register_req_type_normal = 1U << 0,
81 /** Only a real subset of the class is allowed. */
82 arch_register_req_type_limited = 1U << 1,
83 /** The register should be equal to another one at the node. */
84 arch_register_req_type_should_be_same = 1U << 2,
85 /** The register must be unequal from some other at the node. */
86 arch_register_req_type_must_be_different = 1U << 3,
87 /** The registernumber should be aligned (in case of multiregister values)*/
88 arch_register_req_type_aligned = 1U << 4,
89 /** ignore while allocating registers */
90 arch_register_req_type_ignore = 1U << 5,
91 /** the output produces a new value for the stack pointer
92 * (this is not really a constraint but a marker to guide the stackpointer
94 arch_register_req_type_produces_sp = 1U << 6,
95 } arch_register_req_type_t;
97 extern const arch_register_req_t *arch_no_register_req;
100 * Print information about a register requirement in human readable form
101 * @param F output stream/file
102 * @param req The requirements structure to format.
104 void arch_dump_register_req(FILE *F, const arch_register_req_t *req,
105 const ir_node *node);
107 void arch_dump_register_reqs(FILE *F, const ir_node *node);
108 void arch_dump_reqs_and_registers(FILE *F, const ir_node *node);
111 * Node classification. Used for statistics and for detecting reload nodes.
113 typedef enum arch_irn_class_t {
114 arch_irn_class_spill = 1 << 0,
115 arch_irn_class_reload = 1 << 1,
116 arch_irn_class_remat = 1 << 2,
117 arch_irn_class_copy = 1 << 3,
118 arch_irn_class_perm = 1 << 4
121 void arch_set_frame_offset(ir_node *irn, int bias);
123 ir_entity *arch_get_frame_entity(const ir_node *irn);
124 int arch_get_sp_bias(ir_node *irn);
126 int arch_get_op_estimated_cost(const ir_node *irn);
127 arch_inverse_t *arch_get_inverse(const ir_node *irn, int i,
128 arch_inverse_t *inverse,
129 struct obstack *obstack);
130 int arch_possible_memory_operand(const ir_node *irn,
132 void arch_perform_memory_operand(ir_node *irn, ir_node *spill,
136 * Get the register requirements for a node.
137 * @note Deprecated API! Preferably use
138 * arch_get_in_register_req and
139 * arch_get_out_register_req.
141 * @param irn The node.
142 * @param pos The position of the operand you're interested in.
143 * @return A pointer to the register requirements. If NULL is returned, the
144 * operand was no register operand.
146 const arch_register_req_t *arch_get_register_req(const ir_node *irn, int pos);
149 * Put all registers which shall not be ignored by the register
150 * allocator in a bit set.
151 * @param cls The register class to consider.
152 * @param bs The bit set to put the registers to.
154 extern void arch_put_non_ignore_regs(const arch_register_class_t *cls,
158 * Check, if a register is assignable to an operand of a node.
159 * @param irn The node.
160 * @param pos The position of the operand.
161 * @param reg The register.
162 * @return 1, if the register might be allocated to the operand 0 if not.
164 int arch_reg_is_allocatable(const ir_node *irn, int pos,
165 const arch_register_t *reg);
167 #define arch_reg_out_is_allocatable(irn, reg) arch_reg_is_allocatable(irn, -1, reg)
170 * Get the register class of an operand of a node.
171 * @param irn The node.
172 * @param pos The position of the operand, -1 for the output.
173 * @return The register class of the operand or NULL, if
174 * operand is a non-register operand.
176 const arch_register_class_t *arch_get_irn_reg_class(const ir_node *irn,
179 #define arch_get_irn_reg_class_out(irn) arch_get_irn_reg_class(irn, -1)
182 * Get the register allocated at a certain output operand of a node.
183 * @param irn The node.
184 * @return The register allocated for this operand
186 const arch_register_t *arch_get_irn_register(const ir_node *irn);
187 const arch_register_t *arch_irn_get_register(const ir_node *irn, int pos);
190 * Set the register for a certain output operand.
191 * @param irn The node.
192 * @param reg The register.
194 void arch_set_irn_register(ir_node *irn, const arch_register_t *reg);
195 void arch_irn_set_register(ir_node *irn, int pos, const arch_register_t *reg);
199 * @param irn The node.
200 * @return A classification of the node.
202 arch_irn_class_t arch_irn_classify(const ir_node *irn);
205 * Get the flags of a node.
206 * @param irn The node.
209 arch_irn_flags_t arch_irn_get_flags(const ir_node *irn);
211 void arch_irn_set_flags(ir_node *node, arch_irn_flags_t flags);
212 void arch_irn_add_flags(ir_node *node, arch_irn_flags_t flags);
214 #define arch_irn_is(irn, flag) ((arch_irn_get_flags(irn) & arch_irn_flags_ ## flag) != 0)
217 * Get the operations of an irn.
218 * @param self The handler from which the method is invoked.
219 * @param irn Some node.
220 * @return Operations for that irn.
222 typedef const void *(arch_get_irn_ops_t)(const ir_node *irn);
225 * Initialize the architecture environment struct.
226 * @param isa The isa which shall be put into the environment.
227 * @param file_handle The file handle
228 * @return The environment.
230 extern arch_env_t *arch_env_init(const arch_isa_if_t *isa,
231 FILE *file_handle, be_main_env_t *main_env);
234 * Register an instruction set architecture
236 void be_register_isa_if(const char *name, const arch_isa_if_t *isa);
241 struct arch_register_t {
242 const char *name; /**< The name of the register. */
243 const arch_register_class_t *reg_class; /**< The class of the register */
244 unsigned index; /**< The index of the register in
246 arch_register_type_t type; /**< The type of the register. */
247 /** register constraint allowing just this register */
248 const arch_register_req_t *single_req;
251 static inline const arch_register_class_t *_arch_register_get_class(
252 const arch_register_t *reg)
254 return reg->reg_class;
257 static inline unsigned _arch_register_get_index(const arch_register_t *reg)
262 static inline const char *_arch_register_get_name(const arch_register_t *reg)
267 #define arch_register_get_class(reg) _arch_register_get_class(reg)
268 #define arch_register_get_index(reg) _arch_register_get_index(reg)
269 #define arch_register_get_name(reg) _arch_register_get_name(reg)
272 * Convenience macro to check for register type.
273 * @param req A pointer to register.
274 * @param kind The kind of type to check for (see arch_register_type_t).
275 * @return 1, If register is of given kind, 0 if not.
277 #define arch_register_type_is(reg, kind) \
278 (((reg)->type & arch_register_type_ ## kind) != 0)
281 * A class of registers.
282 * Like general purpose or floating point.
284 struct arch_register_class_t {
285 unsigned index; /**< index of this register class */
286 const char *name; /**< The name of the register class.*/
287 unsigned n_regs; /**< Number of registers in this
289 ir_mode *mode; /**< The mode of the register class.*/
290 const arch_register_t *regs; /**< The array of registers. */
291 arch_register_class_flags_t flags; /**< register class flags. */
292 const arch_register_req_t *class_req;
295 /** return the number of registers in this register class */
296 #define arch_register_class_n_regs(cls) ((cls)->n_regs)
298 /** return the largest mode of this register class */
299 #define arch_register_class_mode(cls) ((cls)->mode)
301 /** return the name of this register class */
302 #define arch_register_class_name(cls) ((cls)->name)
304 /** return the index of this register class */
305 #define arch_register_class_index(cls) ((cls)->index)
307 /** return the register class flags */
308 #define arch_register_class_flags(cls) ((cls)->flags)
310 static inline const arch_register_t *_arch_register_for_index(
311 const arch_register_class_t *cls, unsigned idx)
313 assert(idx < cls->n_regs);
314 return &cls->regs[idx];
317 #define arch_register_for_index(cls, idx) _arch_register_for_index(cls, idx)
320 * Convenience macro to check for set constraints.
321 * @param req A pointer to register requirements.
322 * @param kind The kind of constraint to check for
323 * (see arch_register_req_type_t).
324 * @return 1, If the kind of constraint is present, 0 if not.
326 #define arch_register_req_is(req, kind) \
327 (((req)->type & (arch_register_req_type_ ## kind)) != 0)
330 * Expresses requirements to register allocation for an operand.
332 struct arch_register_req_t {
333 arch_register_req_type_t type; /**< The type of the constraint. */
334 const arch_register_class_t *cls; /**< The register class this constraint
336 const unsigned *limited; /**< allowed register bitset */
337 unsigned other_same; /**< Bitmask of ins which should use the
338 same register (should_be_same). */
339 unsigned other_different; /**< Bitmask of ins which shall use a
341 (must_be_different) */
342 unsigned char width; /**< specifies how many sequential
343 registers are required */
346 static inline int reg_reqs_equal(const arch_register_req_t *req1,
347 const arch_register_req_t *req2)
352 if (req1->type != req2->type
353 || req1->cls != req2->cls
354 || req1->other_same != req2->other_same
355 || req1->other_different != req2->other_different)
358 if (req1->limited != NULL) {
361 if (req2->limited == NULL)
364 n_regs = arch_register_class_n_regs(req1->cls);
365 if (!rbitsets_equal(req1->limited, req2->limited, n_regs))
373 * An inverse operation returned by the backend
375 struct arch_inverse_t {
376 int n; /**< count of nodes returned in nodes array */
377 int costs; /**< costs of this remat */
379 /** nodes for this inverse operation. shall be in schedule order.
380 * last element is the target value */
384 struct arch_irn_ops_t {
388 * @param irn The node.
389 * @return A classification.
391 arch_irn_class_t (*classify)(const ir_node *irn);
394 * Get the entity on the stack frame this node depends on.
395 * @param irn The node in question.
396 * @return The entity on the stack frame or NULL, if the node does not have
397 * a stack frame entity.
399 ir_entity *(*get_frame_entity)(const ir_node *irn);
402 * Set the offset of a node carrying an entity on the stack frame.
403 * @param irn The node.
404 * @param offset The offset of the node's stack frame entity.
406 void (*set_frame_offset)(ir_node *irn, int offset);
409 * Returns the delta of the stackpointer for nodes that increment or
410 * decrement the stackpointer with a constant value. (push, pop
411 * nodes on most architectures).
412 * A positive value stands for an expanding stack area, a negative value for
415 * @param irn The node
416 * @return 0 if the stackpointer is not modified with a constant
417 * value, otherwise the increment/decrement value
419 int (*get_sp_bias)(const ir_node *irn);
422 * Returns an inverse operation which yields the i-th argument
423 * of the given node as result.
425 * @param irn The original operation
426 * @param i Index of the argument we want the inverse operation to
428 * @param inverse struct to be filled with the resulting inverse op
429 * @param obstack The obstack to use for allocation of the returned nodes
431 * @return The inverse operation or NULL if operation invertible
433 arch_inverse_t *(*get_inverse)(const ir_node *irn, int i,
434 arch_inverse_t *inverse,
435 struct obstack *obstack);
438 * Get the estimated cycle count for @p irn.
440 * @param irn The node.
441 * @return The estimated cycle count for this operation
443 int (*get_op_estimated_cost)(const ir_node *irn);
446 * Asks the backend whether operand @p i of @p irn can be loaded form memory
449 * @param irn The node.
450 * @param i Index of the argument we would like to know whether @p irn
451 * can load it form memory internally
452 * @return nonzero if argument can be loaded or zero otherwise
454 int (*possible_memory_operand)(const ir_node *irn, unsigned int i);
457 * Ask the backend to assimilate @p reload of operand @p i into @p irn.
459 * @param irn The node.
460 * @param spill The spill.
461 * @param i The position of the reload.
463 void (*perform_memory_operand)(ir_node *irn, ir_node *spill,
468 * The code generator interface.
470 struct arch_code_generator_if_t {
472 * Initialize the code generator.
474 * @return A newly created code generator.
476 void *(*init)(ir_graph *irg);
479 * return node used as base in pic code addresses
481 ir_node* (*get_pic_base)(void *self);
484 * Called before abi introduce.
486 void (*before_abi)(void *self);
489 * Called, when the graph is being normalized.
491 void (*prepare_graph)(void *self);
494 * Backend may provide an own spiller.
495 * This spiller needs to spill all register classes.
497 void (*spill)(void *self, ir_graph *irg);
500 * Called before register allocation.
502 void (*before_ra)(void *self);
505 * Called after register allocation.
507 void (*after_ra)(void *self);
510 * Called directly before done is called. This should be the last place
511 * where the irg is modified.
513 void (*finish)(void *self);
516 * Called after everything happened. This call should emit the final
517 * assembly code but avoid changing the irg.
518 * The code generator must also be de-allocated here.
520 void (*done)(void *self);
524 * helper macro: call function func from the code generator
525 * if it's implemented.
527 #define _arch_cg_call(cg, func) \
529 if((cg)->impl->func) \
530 (cg)->impl->func(cg); \
533 #define _arch_cg_call_env(cg, env, func) \
535 if((cg)->impl->func) \
536 (cg)->impl->func(cg, env); \
539 #define arch_code_generator_before_abi(cg) _arch_cg_call(cg, before_abi)
540 #define arch_code_generator_prepare_graph(cg) _arch_cg_call(cg, prepare_graph)
541 #define arch_code_generator_before_ra(cg) _arch_cg_call(cg, before_ra)
542 #define arch_code_generator_after_ra(cg) _arch_cg_call(cg, after_ra)
543 #define arch_code_generator_finish(cg) _arch_cg_call(cg, finish)
544 #define arch_code_generator_done(cg) _arch_cg_call(cg, done)
545 #define arch_code_generator_spill(cg, irg) _arch_cg_call_env(cg, irg, spill)
546 #define arch_code_generator_has_spiller(cg) ((cg)->impl->spill != NULL)
547 #define arch_code_generator_get_pic_base(cg) \
548 ((cg)->impl->get_pic_base != NULL ? (cg)->impl->get_pic_base(cg) : NULL)
551 * Code generator base class.
553 struct arch_code_generator_t {
554 const arch_code_generator_if_t *impl;
558 * Architecture interface.
560 struct arch_isa_if_t {
562 * Initialize the isa interface.
563 * @param file_handle the file handle to write the output to
564 * @return a new isa instance
566 arch_env_t *(*init)(FILE *file_handle);
569 * Free the isa instance.
571 void (*done)(void *self);
574 * Called directly after initialization. Backend should handle all
577 void (*handle_intrinsics)(void);
580 * Get the the number of register classes in the isa.
581 * @return The number of register classes.
583 unsigned (*get_n_reg_class)(void);
586 * Get the i-th register class.
587 * @param i The number of the register class.
588 * @return The register class.
590 const arch_register_class_t *(*get_reg_class)(unsigned i);
593 * Get the register class which shall be used to store a value of a given
595 * @param self The this pointer.
596 * @param mode The mode in question.
597 * @return A register class which can hold values of the given mode.
599 const arch_register_class_t *(*get_reg_class_for_mode)(const ir_mode *mode);
602 * Get the ABI restrictions for procedure calls.
603 * @param self The this pointer.
604 * @param call_type The call type of the method (procedure) in question.
605 * @param p The array of parameter locations to be filled.
607 void (*get_call_abi)(const void *self, ir_type *call_type,
611 * Get the code generator interface.
612 * @param self The this pointer.
613 * @return Some code generator interface.
615 const arch_code_generator_if_t *(*get_code_generator_if)(void *self);
618 * Get the list scheduler to use. There is already a selector given, the
619 * backend is free to modify and/or ignore it.
621 * @param self The isa object.
622 * @param selector The selector given by options.
623 * @return The list scheduler selector.
625 const list_sched_selector_t *(*get_list_sched_selector)(const void *self,
626 list_sched_selector_t *selector);
629 * Get the ILP scheduler to use.
630 * @param self The isa object.
631 * @return The ILP scheduler selector
633 const ilp_sched_selector_t *(*get_ilp_sched_selector)(const void *self);
636 * Get the necessary alignment for storing a register of given class.
637 * @param self The isa object.
638 * @param cls The register class.
639 * @return The alignment in bytes.
641 int (*get_reg_class_alignment)(const arch_register_class_t *cls);
644 * A "static" function, returns the frontend settings
645 * needed for this backend.
647 const backend_params *(*get_params)(void);
650 * Returns an 2-dim array of execution units, @p irn can be executed on.
651 * The first dimension is the type, the second the allowed units of this
653 * Each dimension is a NULL terminated list.
654 * @param self The isa object.
655 * @param irn The node.
656 * @return An array of allowed execution units.
658 * { unit1_of_tp1, ..., unitX1_of_tp1, NULL },
660 * { unit1_of_tpY, ..., unitXn_of_tpY, NULL },
664 const be_execution_unit_t ***(*get_allowed_execution_units)(
668 * Return the abstract machine for this isa.
669 * @param self The isa object.
671 const be_machine_t *(*get_machine)(const void *self);
674 * Return an ordered list of irgs where code should be generated for.
675 * If NULL is returned, all irg will be taken into account and they will be
676 * generated in an arbitrary order.
677 * @param self The isa object.
678 * @param irgs A flexible array ARR_F of length 0 where the backend can
679 * append the desired irgs.
680 * @return A flexible array ARR_F containing all desired irgs in the
683 ir_graph **(*get_backend_irg_list)(const void *self, ir_graph ***irgs);
686 * mark node as rematerialized
688 void (*mark_remat)(ir_node *node);
691 * parse an assembler constraint part and set flags according to its nature
692 * advances the *c pointer to point to the last parsed character (so if you
693 * parse a single character don't advance c)
695 asm_constraint_flags_t (*parse_asm_constraint)(const char **c);
698 * returns true if the string is a valid clobbered (register) in this
701 int (*is_valid_clobber)(const char *clobber);
704 #define arch_env_done(env) ((env)->impl->done(env))
705 #define arch_env_handle_intrinsics(env) \
706 do { if((env)->impl->handle_intrinsics != NULL) (env)->impl->handle_intrinsics(); } while(0)
707 #define arch_env_get_n_reg_class(env) ((env)->impl->get_n_reg_class())
708 #define arch_env_get_reg_class(env,i) ((env)->impl->get_reg_class(i))
709 #define arch_env_get_reg_class_for_mode(env,mode) ((env)->impl->get_reg_class_for_mode((mode)))
710 #define arch_env_get_call_abi(env,tp,abi) ((env)->impl->get_call_abi((env), (tp), (abi)))
711 #define arch_env_get_code_generator_if(env) ((env)->impl->get_code_generator_if((env)))
712 #define arch_env_get_list_sched_selector(env,selector) ((env)->impl->get_list_sched_selector((env), (selector)))
713 #define arch_env_get_ilp_sched_selector(env) ((env)->impl->get_ilp_sched_selector(env))
714 #define arch_env_get_reg_class_alignment(env,cls) ((env)->impl->get_reg_class_alignment((cls)))
715 #define arch_env_get_params(env) ((env)->impl->get_params())
716 #define arch_env_get_allowed_execution_units(env,irn) ((env)->impl->get_allowed_execution_units((irn)))
717 #define arch_env_get_machine(env) ((env)->impl->get_machine(env))
718 #define arch_env_get_backend_irg_list(env,irgs) ((env)->impl->get_backend_irg_list((env), (irgs)))
719 #define arch_env_parse_asm_constraint(env,c) ((env)->impl->parse_asm_constraint((c))
720 #define arch_env_is_valid_clobber(env,clobber) ((env)->impl->is_valid_clobber((clobber))
721 #define arch_env_mark_remat(env,node) \
722 do { if ((env)->impl->mark_remat != NULL) (env)->impl->mark_remat((node)); } while(0)
728 const arch_isa_if_t *impl;
729 const arch_register_t *sp; /**< The stack pointer register. */
730 const arch_register_t *bp; /**< The base pointer register. */
731 const arch_register_class_t *link_class; /**< The static link pointer
733 int stack_dir; /**< -1 for decreasing, 1 for
735 int stack_alignment; /**< power of 2 stack alignment */
736 const be_main_env_t *main_env; /**< the be main environment */
737 int spill_cost; /**< cost for a be_Spill node */
738 int reload_cost; /**< cost for a be_Reload node */
739 bool custom_abi : 1; /**< backend does all abi handling
740 and does not need the generic stuff
744 static inline unsigned arch_irn_get_n_outs(const ir_node *node)
746 backend_info_t *info = be_get_info(node);
747 if (info->out_infos == NULL)
750 return ARR_LEN(info->out_infos);
753 static inline const arch_irn_ops_t *get_irn_ops_simple(const ir_node *node)
755 const ir_op *ops = get_irn_op(node);
756 const arch_irn_ops_t *be_ops = get_op_ops(ops)->be_ops;
757 assert(!is_Proj(node));
761 static inline const arch_register_req_t *arch_get_register_req_out(
765 backend_info_t *info;
767 /* you have to query the Proj nodes for the constraints (or use
768 * arch_get_out_register_req. Querying a mode_T node and expecting
769 * arch_no_register_req is a bug in your code! */
770 assert(get_irn_mode(irn) != mode_T);
773 pos = get_Proj_proj(irn);
774 irn = get_Proj_pred(irn);
777 info = be_get_info(irn);
778 if (info->out_infos == NULL)
779 return arch_no_register_req;
781 return info->out_infos[pos].req;
784 static inline bool arch_irn_is_ignore(const ir_node *irn)
786 const arch_register_req_t *req = arch_get_register_req_out(irn);
787 return !!(req->type & arch_register_req_type_ignore);
790 static inline bool arch_irn_consider_in_reg_alloc(
791 const arch_register_class_t *cls, const ir_node *node)
793 const arch_register_req_t *req = arch_get_register_req_out(node);
796 !(req->type & arch_register_req_type_ignore);
800 * Get register constraints for an operand at position @p
802 static inline const arch_register_req_t *arch_get_in_register_req(
803 const ir_node *node, int pos)
805 const backend_info_t *info = be_get_info(node);
806 if (info->in_reqs == NULL)
807 return arch_no_register_req;
808 return info->in_reqs[pos];
812 * Get register constraint for a produced result (the @p pos result)
814 static inline const arch_register_req_t *arch_get_out_register_req(
815 const ir_node *node, int pos)
817 const backend_info_t *info = be_get_info(node);
818 if (info->out_infos == NULL)
819 return arch_no_register_req;
820 return info->out_infos[pos].req;
823 static inline void arch_set_out_register_req(ir_node *node, int pos,
824 const arch_register_req_t *req)
826 backend_info_t *info = be_get_info(node);
827 assert(pos < (int) arch_irn_get_n_outs(node));
828 info->out_infos[pos].req = req;
831 static inline void arch_set_in_register_reqs(ir_node *node,
832 const arch_register_req_t **in_reqs)
834 backend_info_t *info = be_get_info(node);
835 info->in_reqs = in_reqs;
838 static inline const arch_register_req_t **arch_get_in_register_reqs(
841 backend_info_t *info = be_get_info(node);
842 return info->in_reqs;
846 * Iterate over all values defined by an instruction.
847 * Only looks at values in a certain register class where the requirements
848 * are not marked as ignore.
849 * Executes @p code for each definition.
851 #define be_foreach_definition_(node, cls, value, code) \
853 if (get_irn_mode(node) == mode_T) { \
854 const ir_edge_t *edge_; \
855 foreach_out_edge(node, edge_) { \
856 const arch_register_req_t *req_; \
857 value = get_edge_src_irn(edge_); \
858 req_ = arch_get_register_req_out(value); \
859 if (req_->cls != cls) \
864 const arch_register_req_t *req_ = arch_get_register_req_out(node); \
866 if (req_->cls == cls) { \
872 #define be_foreach_definition(node, cls, value, code) \
873 be_foreach_definition_(node, cls, value, \
874 if (req_->type & arch_register_req_type_ignore) \