2 * This file is part of libFirm.
3 * Copyright (C) 2012 University of Karlsruhe.
8 * @brief Processor architecture specification.
9 * @author Sebastian Hack
11 #ifndef FIRM_BE_BEARCH_H
12 #define FIRM_BE_BEARCH_H
16 #include "firm_types.h"
17 #include "raw_bitset.h"
24 * this constant is returned by the get_sp_bias functions if the stack
25 * is reset (usually because the frame pointer is copied to the stack
28 #define SP_BIAS_RESET INT_MIN
30 typedef enum arch_register_class_flags_t {
31 arch_register_class_flag_none = 0,
32 /** don't do automatic register allocation for this class */
33 arch_register_class_flag_manual_ra = 1U << 0,
34 /** the register models an abstract state (example: fpu rounding mode) */
35 arch_register_class_flag_state = 1U << 1
36 } arch_register_class_flags_t;
37 ENUM_BITSET(arch_register_class_flags_t)
39 typedef enum arch_register_type_t {
40 arch_register_type_none = 0,
41 /** Do not consider this register when allocating. */
42 arch_register_type_ignore = 1U << 0,
43 /** This is just a virtual register. Virtual registers fulfill any register
44 * constraints as long as the register class matches. It is a allowed to
45 * have multiple definitions for the same virtual register at a point */
46 arch_register_type_virtual = 1U << 1,
47 /** The register represents a state that should be handled by bestate
49 arch_register_type_state = 1U << 2,
50 } arch_register_type_t;
51 ENUM_BITSET(arch_register_type_t)
54 * Different types of register allocation requirements.
56 typedef enum arch_register_req_type_t {
57 /** No register requirement. */
58 arch_register_req_type_none = 0,
59 /** All registers in the class are allowed. */
60 arch_register_req_type_normal = 1U << 0,
61 /** Only a real subset of the class is allowed. */
62 arch_register_req_type_limited = 1U << 1,
63 /** The register should be equal to another one at the node. */
64 arch_register_req_type_should_be_same = 1U << 2,
65 /** The register must be unequal from some other at the node. */
66 arch_register_req_type_must_be_different = 1U << 3,
67 /** The registernumber should be aligned (in case of multiregister values)*/
68 arch_register_req_type_aligned = 1U << 4,
69 /** ignore while allocating registers */
70 arch_register_req_type_ignore = 1U << 5,
71 /** the output produces a new value for the stack pointer
72 * (this is not really a constraint but a marker to guide the stackpointer
74 arch_register_req_type_produces_sp = 1U << 6,
75 } arch_register_req_type_t;
76 ENUM_BITSET(arch_register_req_type_t)
78 extern arch_register_req_t const arch_no_requirement;
79 #define arch_no_register_req (&arch_no_requirement)
81 void arch_dump_register_reqs(FILE *F, const ir_node *node);
82 void arch_dump_reqs_and_registers(FILE *F, const ir_node *node);
84 void arch_set_frame_offset(ir_node *irn, int bias);
86 ir_entity *arch_get_frame_entity(const ir_node *irn);
87 int arch_get_sp_bias(ir_node *irn);
89 int arch_get_op_estimated_cost(const ir_node *irn);
90 int arch_possible_memory_operand(const ir_node *irn,
92 void arch_perform_memory_operand(ir_node *irn, ir_node *spill,
96 * Get the register allocated for a value.
98 const arch_register_t *arch_get_irn_register(const ir_node *irn);
101 * Assign register to a value
103 void arch_set_irn_register(ir_node *irn, const arch_register_t *reg);
106 * Set the register for a certain output operand.
108 void arch_set_irn_register_out(ir_node *irn, unsigned pos, const arch_register_t *r);
110 const arch_register_t *arch_get_irn_register_out(const ir_node *irn, unsigned pos);
111 const arch_register_t *arch_get_irn_register_in(const ir_node *irn, int pos);
114 * Get register constraints for an operand at position @p
116 static inline const arch_register_req_t *arch_get_irn_register_req_in(
117 const ir_node *node, int pos)
119 const backend_info_t *info = be_get_info(node);
120 return info->in_reqs[pos];
124 * Get register constraint for a produced result (the @p pos result)
126 static inline const arch_register_req_t *arch_get_irn_register_req_out(
127 const ir_node *node, unsigned pos)
129 const backend_info_t *info = be_get_info(node);
130 return info->out_infos[pos].req;
133 static inline void arch_set_irn_register_req_out(ir_node *node, unsigned pos,
134 const arch_register_req_t *req)
136 backend_info_t *info = be_get_info(node);
137 assert(pos < (unsigned)ARR_LEN(info->out_infos));
138 info->out_infos[pos].req = req;
141 static inline void arch_set_irn_register_reqs_in(ir_node *node,
142 const arch_register_req_t **reqs)
144 backend_info_t *info = be_get_info(node);
145 info->in_reqs = reqs;
148 static inline const arch_register_req_t **arch_get_irn_register_reqs_in(
151 backend_info_t *info = be_get_info(node);
152 return info->in_reqs;
155 static inline reg_out_info_t *get_out_info(const ir_node *node)
158 const backend_info_t *info;
159 assert(get_irn_mode(node) != mode_T);
161 pos = get_Proj_proj(node);
162 node = get_Proj_pred(node);
165 info = be_get_info(node);
166 assert(pos < ARR_LEN(info->out_infos));
167 return &info->out_infos[pos];
170 static inline const arch_register_req_t *arch_get_irn_register_req(const ir_node *node)
172 reg_out_info_t *out = get_out_info(node);
177 * Get the flags of a node.
178 * @param irn The node.
181 static inline arch_irn_flags_t arch_get_irn_flags(const ir_node *node)
183 backend_info_t const *const info = be_get_info(node);
187 void arch_set_irn_flags(ir_node *node, arch_irn_flags_t flags);
188 void arch_add_irn_flags(ir_node *node, arch_irn_flags_t flags);
190 #define arch_irn_is(irn, flag) ((arch_get_irn_flags(irn) & arch_irn_flags_ ## flag) != 0)
192 static inline unsigned arch_get_irn_n_outs(const ir_node *node)
194 backend_info_t *const info = be_get_info(node);
195 return (unsigned)ARR_LEN(info->out_infos);
198 #define be_foreach_out(node, i) \
199 for (unsigned i = 0, i##__n = arch_get_irn_n_outs(node); i != i##__n; ++i)
202 * Register an instruction set architecture
204 void be_register_isa_if(const char *name, const arch_isa_if_t *isa);
209 struct arch_register_t {
210 const char *name; /**< The name of the register. */
211 const arch_register_class_t *reg_class; /**< The class of the register */
212 unsigned short index; /**< The index of the register in
214 unsigned short global_index; /**< The global index this
215 register in the architecture. */
216 arch_register_type_t type; /**< The type of the register. */
217 /** register constraint allowing just this register */
218 const arch_register_req_t *single_req;
219 /** register number in dwarf debugging format */
220 unsigned short dwarf_number;
224 * A class of registers.
225 * Like general purpose or floating point.
227 struct arch_register_class_t {
228 unsigned index; /**< index of this register class */
229 const char *name; /**< The name of the register class.*/
230 unsigned n_regs; /**< Number of registers in this
232 ir_mode *mode; /**< The mode of the register class.*/
233 const arch_register_t *regs; /**< The array of registers. */
234 arch_register_class_flags_t flags; /**< register class flags. */
235 const arch_register_req_t *class_req;
238 /** return the number of registers in this register class */
239 #define arch_register_class_n_regs(cls) ((cls)->n_regs)
241 /** return the largest mode of this register class */
242 #define arch_register_class_mode(cls) ((cls)->mode)
244 /** return the name of this register class */
245 #define arch_register_class_name(cls) ((cls)->name)
247 /** return the index of this register class */
248 #define arch_register_class_index(cls) ((cls)->index)
250 /** return the register class flags */
251 #define arch_register_class_flags(cls) ((cls)->flags)
253 static inline const arch_register_t *arch_register_for_index(
254 const arch_register_class_t *cls, unsigned idx)
256 assert(idx < cls->n_regs);
257 return &cls->regs[idx];
261 * Convenience macro to check for set constraints.
262 * @param req A pointer to register requirements.
263 * @param kind The kind of constraint to check for
264 * (see arch_register_req_type_t).
265 * @return 1, If the kind of constraint is present, 0 if not.
267 #define arch_register_req_is(req, kind) \
268 (((req)->type & (arch_register_req_type_ ## kind)) != 0)
271 * Expresses requirements to register allocation for an operand.
273 struct arch_register_req_t {
274 arch_register_req_type_t type; /**< The type of the constraint. */
275 const arch_register_class_t *cls; /**< The register class this constraint
277 const unsigned *limited; /**< allowed register bitset
278 (in case of wide-values this is
279 only about the first register) */
280 unsigned other_same; /**< Bitmask of ins which should use the
281 same register (should_be_same). */
282 unsigned other_different; /**< Bitmask of ins which shall use a
284 (must_be_different) */
285 unsigned char width; /**< specifies how many sequential
286 registers are required */
289 static inline bool reg_reqs_equal(const arch_register_req_t *req1,
290 const arch_register_req_t *req2)
295 if (req1->type != req2->type ||
296 req1->cls != req2->cls ||
297 req1->other_same != req2->other_same ||
298 req1->other_different != req2->other_different ||
299 (req1->limited != NULL) != (req2->limited != NULL))
302 if (req1->limited != NULL) {
303 size_t const n_regs = arch_register_class_n_regs(req1->cls);
304 if (!rbitsets_equal(req1->limited, req2->limited, n_regs))
311 struct arch_irn_ops_t {
314 * Get the entity on the stack frame this node depends on.
315 * @param irn The node in question.
316 * @return The entity on the stack frame or NULL, if the node does not have
317 * a stack frame entity.
319 ir_entity *(*get_frame_entity)(const ir_node *irn);
322 * Set the offset of a node carrying an entity on the stack frame.
323 * @param irn The node.
324 * @param offset The offset of the node's stack frame entity.
326 void (*set_frame_offset)(ir_node *irn, int offset);
329 * Returns the delta of the stackpointer for nodes that increment or
330 * decrement the stackpointer with a constant value. (push, pop
331 * nodes on most architectures).
332 * A positive value stands for an expanding stack area, a negative value for
335 * @param irn The node
336 * @return 0 if the stackpointer is not modified with a constant
337 * value, otherwise the increment/decrement value
339 int (*get_sp_bias)(const ir_node *irn);
342 * Get the estimated cycle count for @p irn.
344 * @param irn The node.
345 * @return The estimated cycle count for this operation
347 int (*get_op_estimated_cost)(const ir_node *irn);
350 * Asks the backend whether operand @p i of @p irn can be loaded form memory
353 * @param irn The node.
354 * @param i Index of the argument we would like to know whether @p irn
355 * can load it form memory internally
356 * @return nonzero if argument can be loaded or zero otherwise
358 int (*possible_memory_operand)(const ir_node *irn, unsigned int i);
361 * Ask the backend to assimilate @p reload of operand @p i into @p irn.
363 * @param irn The node.
364 * @param spill The spill.
365 * @param i The position of the reload.
367 void (*perform_memory_operand)(ir_node *irn, ir_node *spill,
372 * Architecture interface.
374 struct arch_isa_if_t {
376 * Initializes the isa interface. This is necessary before calling any
377 * other functions from this interface.
382 * Fress resources allocated by this isa interface.
384 void (*finish)(void);
387 * Returns the frontend settings needed for this backend.
389 const backend_params *(*get_params)(void);
392 * lowers current program for target. See the documentation for
393 * be_lower_for_target() for details.
395 void (*lower_for_target)(void);
398 * parse an assembler constraint part and set flags according to its nature
399 * advances the *c pointer to point to the last parsed character (so if you
400 * parse a single character don't advance c)
402 asm_constraint_flags_t (*parse_asm_constraint)(const char **c);
405 * returns true if the string is a valid clobbered (register) in this
408 int (*is_valid_clobber)(const char *clobber);
411 * Start codegeneration
412 * @return a new isa instance
414 arch_env_t *(*begin_codegeneration)(void);
417 * Free the isa instance.
419 void (*end_codegeneration)(void *self);
422 * Initialize the code generator for a graph
425 void (*init_graph)(ir_graph *irg);
428 * Get the ABI restrictions for procedure calls.
429 * @param call_type The call type of the method (procedure) in question.
430 * @param p The array of parameter locations to be filled.
432 void (*get_call_abi)(ir_type *call_type, be_abi_call_t *abi);
435 * mark node as rematerialized
437 void (*mark_remat)(ir_node *node);
440 * return node used as base in pic code addresses
442 ir_node* (*get_pic_base)(ir_graph *irg);
445 * Create a spill instruction. We assume that spill instructions
446 * do not need any additional registers and do not affect cpu-flags in any
448 * Construct a sequence of instructions after @p after (the resulting nodes
449 * are already scheduled).
450 * Returns a mode_M value which is used as input for a reload instruction.
452 ir_node *(*new_spill)(ir_node *value, ir_node *after);
455 * Create a reload instruction. We assume that reload instructions do not
456 * need any additional registers and do not affect cpu-flags in any way.
457 * Constructs a sequence of instruction before @p before (the resulting
458 * nodes are already scheduled). A rewiring of users is not performed in
460 * Returns a value representing the restored value.
462 ir_node *(*new_reload)(ir_node *value, ir_node *spilled_value,
466 * Checks if the given register is callee/caller saved.
467 * @deprecated, only necessary if backend still uses beabi functions
469 int (*register_saved_by)(const arch_register_t *reg, int callee);
472 * Called directly after initialization. Backend should handle all
475 void (*handle_intrinsics)(void);
478 * Called before abi introduce.
480 void (*before_abi)(ir_graph *irg);
483 * Called, when the graph is being normalized.
485 void (*prepare_graph)(ir_graph *irg);
488 * Called before register allocation.
490 void (*before_ra)(ir_graph *irg);
493 * Called directly before done is called. This should be the last place
494 * where the irg is modified.
496 void (*finish_graph)(ir_graph *irg);
499 * Called after everything happened. This call should emit the final
500 * assembly code but avoid changing the irg.
502 void (*emit)(ir_graph *irg);
505 #define arch_env_end_codegeneration(env) ((env)->impl->end_codegeneration(env))
506 #define arch_env_handle_intrinsics(env) \
507 do { if((env)->impl->handle_intrinsics != NULL) (env)->impl->handle_intrinsics(); } while(0)
508 #define arch_env_get_call_abi(env,tp,abi) ((env)->impl->get_call_abi((tp), (abi)))
509 #define arch_env_mark_remat(env,node) \
510 do { if ((env)->impl->mark_remat != NULL) (env)->impl->mark_remat((node)); } while(0)
512 #define arch_env_new_spill(env,value,after) ((env)->impl->new_spill(value, after))
513 #define arch_env_new_reload(env,value,spilled,before) ((env)->impl->new_reload(value, spilled, before))
519 const arch_isa_if_t *impl;
520 unsigned n_registers; /**< number of registers */
521 const arch_register_t *registers; /**< register array */
522 unsigned n_register_classes; /**< number of register classes*/
523 const arch_register_class_t *register_classes; /**< register classes */
524 const arch_register_t *sp; /**< The stack pointer register. */
525 const arch_register_t *bp; /**< The base pointer register. */
526 int stack_alignment; /**< power of 2 stack alignment */
527 int spill_cost; /**< cost for a be_Spill node */
528 int reload_cost; /**< cost for a be_Reload node */
529 bool custom_abi : 1; /**< backend does all abi handling
530 and does not need the generic
531 stuff from beabi.h/.c */
534 static inline bool arch_irn_is_ignore(const ir_node *irn)
536 const arch_register_req_t *req = arch_get_irn_register_req(irn);
537 return arch_register_req_is(req, ignore);
540 static inline bool arch_irn_consider_in_reg_alloc(
541 const arch_register_class_t *cls, const ir_node *node)
543 const arch_register_req_t *req = arch_get_irn_register_req(node);
544 return req->cls == cls && !arch_register_req_is(req, ignore);
547 #define be_foreach_value(node, value, code) \
549 if (get_irn_mode(node) == mode_T) { \
550 foreach_out_edge(node, node##__edge) { \
551 ir_node *const value = get_edge_src_irn(node##__edge); \
552 if (!is_Proj(value)) \
557 ir_node *const value = node; \
563 * Iterate over all values defined by an instruction.
564 * Only looks at values in a certain register class where the requirements
565 * are not marked as ignore.
566 * Executes @p code for each definition.
568 #define be_foreach_definition_(node, ccls, value, req, code) \
569 be_foreach_value(node, value, \
570 arch_register_req_t const *const req = arch_get_irn_register_req(value); \
571 if (req->cls != ccls) \
576 #define be_foreach_definition(node, ccls, value, req, code) \
577 be_foreach_definition_(node, ccls, value, req, \
578 if (arch_register_req_is(req, ignore)) \
583 #define be_foreach_use(node, ccls, in_req, value, value_req, code) \
585 for (int i_ = 0, n_ = get_irn_arity(node); i_ < n_; ++i_) { \
586 const arch_register_req_t *in_req = arch_get_irn_register_req_in(node, i_); \
587 if (in_req->cls != ccls) \
589 ir_node *value = get_irn_n(node, i_); \
590 const arch_register_req_t *value_req = arch_get_irn_register_req(value); \
591 if (value_req->type & arch_register_req_type_ignore) \
597 static inline const arch_register_class_t *arch_get_irn_reg_class(
600 const arch_register_req_t *req = arch_get_irn_register_req(node);
604 bool arch_reg_is_allocatable(const arch_register_req_t *req,
605 const arch_register_t *reg);