2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief declarations for arm backend -- private header
23 * @author Oliver Richter, Tobias Gneist
26 #ifndef FIRM_BE_ARM_BEARCH_ARM_T_H
27 #define FIRM_BE_ARM_BEARCH_ARM_T_H
32 #include "bearch_arm.h"
33 #include "arm_nodes_attr.h"
35 #include "../beemitter.h"
38 typedef struct _arm_isa_t arm_isa_t;
40 /** The following bitmasks control CPU extensions: */
41 enum arm_cpu_extensions {
42 ARM_EXT_V1 = 0x00000001, /**< All processors (core set). */
43 ARM_EXT_V2 = 0x00000002, /**< Multiply instructions. */
44 ARM_EXT_V2S = 0x00000004, /**< SWP instructions. */
45 ARM_EXT_V3 = 0x00000008, /**< MSR MRS. */
46 ARM_EXT_V3M = 0x00000010, /**< Allow long multiplies. */
47 ARM_EXT_V4 = 0x00000020, /**< Allow half word loads. */
48 ARM_EXT_V4T = 0x00000040, /**< Thumb v1. */
49 ARM_EXT_V5 = 0x00000080, /**< Allow CLZ, etc. */
50 ARM_EXT_V5T = 0x00000100, /**< Thumb v2.ยด*/
51 ARM_EXT_V5ExP = 0x00000200, /**< DSP core set. */
52 ARM_EXT_V5E = 0x00000400, /**< DSP Double transfers. */
53 ARM_EXT_V5J = 0x00000800, /**< Jazelle extension. */
55 /* Co-processor space extensions. */
56 ARM_CEXT_XSCALE = 0x00800000, /**< Allow MIA etc. */
57 ARM_CEXT_MAVERICK = 0x00400000, /**< Use Cirrus/DSP coprocessor. */
58 ARM_CEXT_IWMMXT = 0x00200000, /**< Intel Wireless MMX technology coprocessor. */
62 * Architectures are the sum of the base and extensions. The ARM ARM (rev E)
63 * defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
64 * ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add
65 * three more to cover cores prior to ARM6. Finally, there are cores which
66 * implement further extensions in the co-processor space.
68 enum arm_architectures {
69 ARM_ARCH_V1 = ARM_EXT_V1,
70 ARM_ARCH_V2 = ARM_ARCH_V1 | ARM_EXT_V2,
71 ARM_ARCH_V2S = ARM_ARCH_V2 | ARM_EXT_V2S,
72 ARM_ARCH_V3 = ARM_ARCH_V2S | ARM_EXT_V3,
73 ARM_ARCH_V3M = ARM_ARCH_V3 | ARM_EXT_V3M,
74 ARM_ARCH_V4xM = ARM_ARCH_V3 | ARM_EXT_V4,
75 ARM_ARCH_V4 = ARM_ARCH_V3M | ARM_EXT_V4,
76 ARM_ARCH_V4TxM = ARM_ARCH_V4xM | ARM_EXT_V4T,
77 ARM_ARCH_V4T = ARM_ARCH_V4 | ARM_EXT_V4T,
78 ARM_ARCH_V5xM = ARM_ARCH_V4xM| ARM_EXT_V5,
79 ARM_ARCH_V5 = ARM_ARCH_V4 | ARM_EXT_V5,
80 ARM_ARCH_V5TxM = ARM_ARCH_V5xM | ARM_EXT_V4T | ARM_EXT_V5T,
81 ARM_ARCH_V5T = ARM_ARCH_V5 | ARM_EXT_V4T | ARM_EXT_V5T,
82 ARM_ARCH_V5TExP = ARM_ARCH_V5T | ARM_EXT_V5ExP,
83 ARM_ARCH_V5TE = ARM_ARCH_V5TExP | ARM_EXT_V5E,
84 ARM_ARCH_V5TEJ = ARM_ARCH_V5TE | ARM_EXT_V5J,
86 /* Processors with specific extensions in the co-processor space. */
87 ARM_ARCH_XSCALE = ARM_ARCH_V5TE | ARM_CEXT_XSCALE,
88 ARM_ARCH_IWMMXT = ARM_ARCH_XSCALE | ARM_CEXT_IWMMXT,
90 ARM_ARCH_MASK = 0x00ffffff,
93 /** Floating point instruction set. */
94 enum arm_fp_architectures {
95 ARM_FPU_FPA_EXT_V1 = 0x80000000, /**< Base FPA instruction set. */
96 ARM_FPU_FPA_EXT_V2 = 0x40000000, /**< LFM/SFM. */
97 ARM_FPU_VFP_EXT_NONE = 0x20000000, /**< Use VFP word-ordering. */
98 ARM_FPU_VFP_EXT_V1xD = 0x10000000, /**< Base VFP instruction set. */
99 ARM_FPU_VFP_EXT_V1 = 0x08000000, /**< Double-precision insns. */
100 ARM_FPU_VFP_EXT_V2 = 0x04000000, /**< ARM10E VFPr1. */
102 ARM_FPU_SOFTFLOAT = 0x01000000, /**< soft float library */
105 ARM_FPU_ARCH_FPE = ARM_FPU_FPA_EXT_V1,
106 ARM_FPU_ARCH_FPA = ARM_FPU_ARCH_FPE | ARM_FPU_FPA_EXT_V2,
108 ARM_FPU_ARCH_VFP = ARM_FPU_VFP_EXT_NONE,
109 ARM_FPU_ARCH_VFP_V1xD = ARM_FPU_VFP_EXT_V1xD | ARM_FPU_VFP_EXT_NONE,
110 ARM_FPU_ARCH_VFP_V1 = ARM_FPU_ARCH_VFP_V1xD | ARM_FPU_VFP_EXT_V1,
111 ARM_FPU_ARCH_VFP_V2 = ARM_FPU_ARCH_VFP_V1 | ARM_FPU_VFP_EXT_V2,
113 ARM_FPU_ARCH_SOFTFLOAT = ARM_FPU_SOFTFLOAT,
115 ARM_FPU_MASK = 0xff000000,
118 /** Returns non-zero if FPA instructions should be issued. */
119 #define USE_FPA(isa) ((isa)->fpu_arch & ARM_FPU_FPA_EXT_V1)
121 /** Returns non-zero if VFP instructions should be issued. */
122 #define USE_VFP(isa) ((isa)->fpu_arch & ARM_FPU_VFP_EXT_V1xD)
124 /** Types of processor to generate code for. */
125 enum arm_processor_types {
128 ARM_2a = ARM_ARCH_V2,
129 ARM_3 = ARM_ARCH_V2S,
130 ARM_3G = ARM_ARCH_V2S,
131 ARM_250 = ARM_ARCH_V2S,
135 ARM_9 = ARM_ARCH_V4T,
136 ARM_STRONG = ARM_ARCH_V4,
139 typedef struct _arm_code_gen_t {
140 const arch_code_generator_if_t *impl; /**< implementation */
141 ir_graph *irg; /**< current irg */
142 const arch_env_t *arch_env; /**< the arch env */
143 set *reg_set; /**< set to memorize registers for FIRM nodes (e.g. phi) */
144 arm_isa_t *isa; /**< the isa instance */
145 be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */
146 ir_type *int_tp; /**< the int type, needed for Call conversion */
147 ir_node *unknown_gp; /**< unique Unknown_GP node */
148 ir_node *unknown_fpa; /**< unique Unknown_FPA node */
149 char have_fp_insn; /**< non-zero, if fp hardware instructions are emitted */
150 char dump; /**< set to 1 if graphs should be dumped */
151 DEBUG_ONLY(firm_dbg_module_t *mod;) /**< debugging module */
156 arch_isa_t arch_isa; /**< must be derived from arch_isa_t */
157 int gen_reg_names; /**< use generic register names instead of SP, LR, PC */
158 int fpu_arch; /**< FPU architecture */
159 arm_code_gen_t *cg; /**< current code generator */
163 typedef struct _arm_irn_ops_t {
164 const arch_irn_ops_if_t *impl;