2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 #ifndef _BEARCH_ARM_T_H_
21 #define _BEARCH_ARM_T_H_
26 #include "bearch_arm.h"
27 #include "arm_nodes_attr.h"
31 typedef struct _arm_isa_t arm_isa_t;
33 /** The following bitmasks control CPU extensions: */
34 enum arm_cpu_extensions {
35 ARM_EXT_V1 = 0x00000001, /**< All processors (core set). */
36 ARM_EXT_V2 = 0x00000002, /**< Multiply instructions. */
37 ARM_EXT_V2S = 0x00000004, /**< SWP instructions. */
38 ARM_EXT_V3 = 0x00000008, /**< MSR MRS. */
39 ARM_EXT_V3M = 0x00000010, /**< Allow long multiplies. */
40 ARM_EXT_V4 = 0x00000020, /**< Allow half word loads. */
41 ARM_EXT_V4T = 0x00000040, /**< Thumb v1. */
42 ARM_EXT_V5 = 0x00000080, /**< Allow CLZ, etc. */
43 ARM_EXT_V5T = 0x00000100, /**< Thumb v2.ยด*/
44 ARM_EXT_V5ExP = 0x00000200, /**< DSP core set. */
45 ARM_EXT_V5E = 0x00000400, /**< DSP Double transfers. */
46 ARM_EXT_V5J = 0x00000800, /**< Jazelle extension. */
48 /* Co-processor space extensions. */
49 ARM_CEXT_XSCALE = 0x00800000, /**< Allow MIA etc. */
50 ARM_CEXT_MAVERICK = 0x00400000, /**< Use Cirrus/DSP coprocessor. */
51 ARM_CEXT_IWMMXT = 0x00200000, /**< Intel Wireless MMX technology coprocessor. */
55 * Architectures are the sum of the base and extensions. The ARM ARM (rev E)
56 * defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
57 * ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add
58 * three more to cover cores prior to ARM6. Finally, there are cores which
59 * implement further extensions in the co-processor space.
61 enum arm_architectiures {
62 ARM_ARCH_V1 = ARM_EXT_V1,
63 ARM_ARCH_V2 = ARM_ARCH_V1 | ARM_EXT_V2,
64 ARM_ARCH_V2S = ARM_ARCH_V2 | ARM_EXT_V2S,
65 ARM_ARCH_V3 = ARM_ARCH_V2S | ARM_EXT_V3,
66 ARM_ARCH_V3M = ARM_ARCH_V3 | ARM_EXT_V3M,
67 ARM_ARCH_V4xM = ARM_ARCH_V3 | ARM_EXT_V4,
68 ARM_ARCH_V4 = ARM_ARCH_V3M | ARM_EXT_V4,
69 ARM_ARCH_V4TxM = ARM_ARCH_V4xM | ARM_EXT_V4T,
70 ARM_ARCH_V4T = ARM_ARCH_V4 | ARM_EXT_V4T,
71 ARM_ARCH_V5xM = ARM_ARCH_V4xM| ARM_EXT_V5,
72 ARM_ARCH_V5 = ARM_ARCH_V4 | ARM_EXT_V5,
73 ARM_ARCH_V5TxM = ARM_ARCH_V5xM | ARM_EXT_V4T | ARM_EXT_V5T,
74 ARM_ARCH_V5T = ARM_ARCH_V5 | ARM_EXT_V4T | ARM_EXT_V5T,
75 ARM_ARCH_V5TExP = ARM_ARCH_V5T | ARM_EXT_V5ExP,
76 ARM_ARCH_V5TE = ARM_ARCH_V5TExP | ARM_EXT_V5E,
77 ARM_ARCH_V5TEJ = ARM_ARCH_V5TE | ARM_EXT_V5J,
79 /* Processors with specific extensions in the co-processor space. */
80 ARM_ARCH_XSCALE = ARM_ARCH_V5TE | ARM_CEXT_XSCALE,
81 ARM_ARCH_IWMMXT = ARM_ARCH_XSCALE | ARM_CEXT_IWMMXT,
83 ARM_ARCH_MASK = 0x00ffffff,
86 /** Floating point instruction set. */
87 enum arm_fp_architectures {
88 ARM_FPU_FPA_EXT_V1 = 0x80000000, /**< Base FPA instruction set. */
89 ARM_FPU_FPA_EXT_V2 = 0x40000000, /**< LFM/SFM. */
90 ARM_FPU_VFP_EXT_NONE = 0x20000000, /**< Use VFP word-ordering. */
91 ARM_FPU_VFP_EXT_V1xD = 0x10000000, /**< Base VFP instruction set. */
92 ARM_FPU_VFP_EXT_V1 = 0x08000000, /**< Double-precision insns. */
93 ARM_FPU_VFP_EXT_V2 = 0x04000000, /**< ARM10E VFPr1. */
95 ARM_FPU_SOFTFLOAT = 0x01000000, /**< soft float library */
98 ARM_FPU_ARCH_FPE = ARM_FPU_FPA_EXT_V1,
99 ARM_FPU_ARCH_FPA = ARM_FPU_ARCH_FPE | ARM_FPU_FPA_EXT_V2,
101 ARM_FPU_ARCH_VFP = ARM_FPU_VFP_EXT_NONE,
102 ARM_FPU_ARCH_VFP_V1xD = ARM_FPU_VFP_EXT_V1xD | ARM_FPU_VFP_EXT_NONE,
103 ARM_FPU_ARCH_VFP_V1 = ARM_FPU_ARCH_VFP_V1xD | ARM_FPU_VFP_EXT_V1,
104 ARM_FPU_ARCH_VFP_V2 = ARM_FPU_ARCH_VFP_V1 | ARM_FPU_VFP_EXT_V2,
106 ARM_FPU_ARCH_SOFTFLOAT = ARM_FPU_SOFTFLOAT,
108 ARM_FPU_MASK = 0xff000000,
111 /** Returns non-zero if FPA instructions should be issued. */
112 #define USE_FPA(cg) ((cg)->fpu_arch & ARM_FPU_FPA_EXT_V1)
114 /** Returns non-zero if VFP instructions should be issued. */
115 #define USE_VFP(cg) ((cg)->fpu_arch & ARM_FPU_VFP_EXT_V1xD)
117 /** Types of processor to generate code for. */
118 enum arm_processor_types {
121 ARM_3 = ARM_ARCH_V2S,
122 ARM_250 = ARM_ARCH_V2S,
126 ARM_9 = ARM_ARCH_V4T,
127 ARM_STRONG = ARM_ARCH_V4,
130 typedef struct _arm_code_gen_t {
131 const arch_code_generator_if_t *impl; /**< implementation */
132 ir_graph *irg; /**< current irg */
133 const arch_env_t *arch_env; /**< the arch env */
134 set *reg_set; /**< set to memorize registers for FIRM nodes (e.g. phi) */
135 int emit_decls; /**< flag indicating if decls were already emitted */
136 arm_isa_t *isa; /**< the isa instance */
137 const be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */
138 ir_type *int_tp; /**< the int type, needed for Call conversion */
139 int have_fp; /**< non-zero, if fp hardware instructions are emitted */
140 DEBUG_ONLY(firm_dbg_module_t *mod;) /**< debugging module */
145 const arch_isa_if_t *impl;
146 const arch_register_t *sp; /**< The stack pointer register. */
147 const arch_register_t *bp; /**< The base pointer register. */
148 const int stack_dir; /**< -1 for decreasing, 1 for increasing. */
150 int gen_reg_names; /**< use generic register names instead of SP, LR, PC */
151 arm_code_gen_t *cg; /**< current code generator */
152 FILE *out; /**< output file */
154 int fpu_arch; /**< FPU architecture */
158 typedef struct _arm_irn_ops_t {
159 const arch_irn_ops_if_t *impl;
164 #endif /* _BEARCH_ARM_T_H_ */