1 /* The main arm backend driver file. */
9 #include <libcore/lc_opts.h>
10 #include <libcore/lc_opts_enum.h>
11 #endif /* WITH_LIBCORE */
13 #include "pseudo_irg.h"
19 #include "lower_intrinsics.h"
24 #include "../bearch.h" /* the general register allocator interface */
25 #include "../benode_t.h"
26 #include "../belower.h"
27 #include "../besched_t.h"
30 #include "../bemachine.h"
31 #include "../beilpsched.h"
33 #include "bearch_arm_t.h"
35 #include "arm_new_nodes.h" /* arm nodes interface */
36 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
37 #include "arm_gen_decls.h" /* interface declaration emitter */
38 #include "arm_transform.h"
39 #include "arm_emitter.h"
40 #include "arm_map_regs.h"
42 #define DEBUG_MODULE "firm.be.arm.isa"
44 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
45 static set *cur_reg_set = NULL;
47 /**************************************************
50 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
51 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
52 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
53 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
56 **************************************************/
58 static ir_node *my_skip_proj(const ir_node *n) {
65 * Return register requirements for a arm node.
66 * If the node returns a tuple (mode_T) then the proj's
67 * will be asked for this information.
69 static const arch_register_req_t *arm_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
70 const arm_register_req_t *irn_req;
71 long node_pos = pos == -1 ? 0 : pos;
72 ir_mode *mode = get_irn_mode(irn);
73 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
75 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
76 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
80 if (mode == mode_T && pos < 0) {
81 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
85 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
88 /* in case of a proj, we need to get the correct OUT slot */
89 /* of the node corresponding to the proj number */
91 node_pos = arm_translate_proj_pos(irn);
97 irn = my_skip_proj(irn);
99 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
102 /* get requirements for our own nodes */
103 if (is_arm_irn(irn)) {
105 irn_req = get_arm_in_req(irn, pos);
108 irn_req = get_arm_out_req(irn, node_pos);
111 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
113 memcpy(req, &(irn_req->req), sizeof(*req));
115 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
116 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
117 req->other_same = get_irn_n(irn, irn_req->same_pos);
120 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
121 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
122 req->other_different = get_irn_n(irn, irn_req->different_pos);
125 /* get requirements for FIRM nodes */
127 /* treat Phi like Const with default requirements */
129 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
131 if (mode_is_float(mode)) {
132 memcpy(req, &(arm_default_req_arm_fpa.req), sizeof(*req));
134 else if (mode_is_int(mode) || mode_is_reference(mode)) {
135 memcpy(req, &(arm_default_req_arm_gp.req), sizeof(*req));
137 else if (mode == mode_T || mode == mode_M) {
138 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
142 assert(0 && "unsupported Phi-Mode");
146 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
154 static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
159 if (get_irn_mode(irn) == mode_X) {
163 pos = arm_translate_proj_pos(irn);
164 irn = my_skip_proj(irn);
167 if (is_arm_irn(irn)) {
168 const arch_register_t **slots;
170 slots = get_arm_slots(irn);
174 /* here we set the registers for the Phi nodes */
175 arm_set_firm_reg(irn, reg, cur_reg_set);
179 static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) {
181 const arch_register_t *reg = NULL;
185 if (get_irn_mode(irn) == mode_X) {
189 pos = arm_translate_proj_pos(irn);
190 irn = my_skip_proj(irn);
193 if (is_arm_irn(irn)) {
194 const arch_register_t **slots;
195 slots = get_arm_slots(irn);
199 reg = arm_get_firm_reg(irn, cur_reg_set);
205 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
206 irn = my_skip_proj(irn);
209 return arch_irn_class_branch;
211 else if (is_arm_irn(irn)) {
212 return arch_irn_class_normal;
218 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
219 irn = my_skip_proj(irn);
221 if (is_arm_irn(irn)) {
222 return get_arm_flags(irn);
224 else if (is_Unknown(irn)) {
225 return arch_irn_flags_ignore;
231 static entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
232 /* TODO: return the entity assigned to the frame */
236 static void arm_set_frame_entity(const void *self, ir_node *irn, entity *ent) {
237 /* TODO: set the entity assigned to the frame */
241 * This function is called by the generic backend to correct offsets for
242 * nodes accessing the stack.
244 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
245 /* TODO: correct offset if irn accesses the stack */
248 static int arm_get_sp_bias(const void *self, const ir_node *irn) {
252 /* fill register allocator interface */
254 static const arch_irn_ops_if_t arm_irn_ops_if = {
260 arm_get_frame_entity,
261 arm_set_frame_entity,
264 NULL, /* get_inverse */
265 NULL, /* get_op_estimated_cost */
266 NULL, /* possible_memory_operand */
267 NULL, /* perform_memory_operand */
270 arm_irn_ops_t arm_irn_ops = {
277 /**************************************************
280 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
281 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
282 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
283 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
286 **************************************************/
289 * Transforms the standard Firm graph into
292 static void arm_prepare_graph(void *self) {
293 arm_code_gen_t *cg = self;
295 arm_register_transformers();
296 irg_walk_blkwise_graph(cg->irg, arm_move_consts, arm_transform_node, cg);
302 * Called immediately before emit phase.
304 static void arm_finish_irg(void *self) {
305 /* TODO: - fix offsets for nodes accessing stack
312 * These are some hooks which must be filled but are probably not needed.
314 static void arm_before_sched(void *self) {
315 /* Some stuff you need to do after scheduling but before register allocation */
318 static void arm_before_ra(void *self) {
319 /* Some stuff you need to do immediately after register allocation */
324 * Emits the code, closes the output file and frees
325 * the code generator interface.
327 static void arm_emit_and_done(void *self) {
328 arm_code_gen_t *cg = self;
329 ir_graph *irg = cg->irg;
330 FILE *out = cg->isa->out;
332 if (cg->emit_decls) {
337 dump_ir_block_graph_sched(irg, "-arm-finished");
338 arm_gen_routine(out, irg, cg);
342 /* de-allocate code generator */
343 del_set(cg->reg_set);
348 * Move a double floating point value into an integer register.
349 * Place the move operation into block bl.
351 * Handle some special cases here:
352 * 1.) A constant: simply split into two
353 * 2.) A load: siply split into two
355 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
356 ir_node **resH, ir_node **resL) {
358 tarval *tv = get_Const_tarval(arg);
361 /* get the upper 32 bits */
362 v = get_tarval_sub_bits(tv, 7);
363 v = (v << 8) | get_tarval_sub_bits(tv, 6);
364 v = (v << 8) | get_tarval_sub_bits(tv, 5);
365 v = (v << 8) | get_tarval_sub_bits(tv, 4);
366 *resH = new_Const_long(mode_Is, v);
368 /* get the lower 32 bits */
369 v = get_tarval_sub_bits(tv, 3);
370 v = (v << 8) | get_tarval_sub_bits(tv, 2);
371 v = (v << 8) | get_tarval_sub_bits(tv, 1);
372 v = (v << 8) | get_tarval_sub_bits(tv, 0);
373 *resL = new_Const_long(mode_Is, v);
375 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
376 /* FIXME: handling of low/high depends on LE/BE here */
380 ir_graph *irg = current_ir_graph;
383 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
385 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
386 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
387 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
393 * Move a single floating point value into an integer register.
394 * Place the move operation into block bl.
396 * Handle some special cases here:
397 * 1.) A constant: simply move
398 * 2.) A load: siply load
400 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) {
402 tarval *tv = get_Const_tarval(arg);
405 /* get the lower 32 bits */
406 v = get_tarval_sub_bits(tv, 3);
407 v = (v << 8) | get_tarval_sub_bits(tv, 2);
408 v = (v << 8) | get_tarval_sub_bits(tv, 1);
409 v = (v << 8) | get_tarval_sub_bits(tv, 0);
410 return new_Const_long(mode_Is, v);
412 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
415 load = skip_Proj(arg);
422 * Convert the arguments of a call to support the
423 * ARM calling convention of general purpose AND floating
426 static void handle_calls(ir_node *call, void *env)
428 arm_code_gen_t *cg = env;
429 int i, j, n, size, idx, flag, n_param, n_res;
430 ir_type *mtp, *new_mtd, *new_tp[5];
431 ir_node *new_in[5], **in;
437 /* check, if we need conversions */
438 n = get_Call_n_params(call);
439 mtp = get_Call_type(call);
440 assert(get_method_n_params(mtp) == n);
442 /* it's always enough to handle the first 4 parameters */
445 flag = size = idx = 0;
446 bl = get_nodes_block(call);
447 for (i = 0; i < n; ++i) {
448 ir_type *param_tp = get_method_param_type(mtp, i);
450 if (is_compound_type(param_tp)) {
451 /* an aggregate parameter: bad case */
455 /* a primitive parameter */
456 ir_mode *mode = get_type_mode(param_tp);
458 if (mode_is_float(mode)) {
459 if (get_mode_size_bits(mode) > 32) {
460 ir_node *mem = get_Call_mem(call);
462 /* Beware: ARM wants the high part first */
464 new_tp[idx] = cg->int_tp;
465 new_tp[idx+1] = cg->int_tp;
466 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
468 set_Call_mem(call, mem);
472 new_tp[idx] = cg->int_tp;
473 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
480 new_tp[idx] = param_tp;
481 new_in[idx] = get_Call_param(call, i);
490 /* if flag is NOT set, no need to translate the method type */
494 /* construct a new method type */
496 n_param = get_method_n_params(mtp) - n + idx;
497 n_res = get_method_n_ress(mtp);
498 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
500 for (i = 0; i < idx; ++i)
501 set_method_param_type(new_mtd, i, new_tp[i]);
502 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
503 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
504 for (i = 0; i < n_res; ++i)
505 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
507 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
508 set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp));
510 if (is_lowered_type(mtp)) {
511 mtp = get_associated_type(mtp);
513 set_lowered_type(mtp, new_mtd);
515 set_Call_type(call, new_mtd);
517 /* calculate new in array of the Call */
518 NEW_ARR_A(ir_node *, in, n_param + 2);
519 for (i = 0; i < idx; ++i)
520 in[2 + i] = new_in[i];
521 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
522 in[2 + j++] = get_Call_param(call, i);
524 in[0] = get_Call_mem(call);
525 in[1] = get_Call_ptr(call);
527 /* finally, change the call inputs */
528 set_irn_in(call, n_param + 2, in);
532 * Handle graph transformations before the abi converter does its work.
534 static void arm_before_abi(void *self) {
535 arm_code_gen_t *cg = self;
537 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
540 static void *arm_cg_init(const be_irg_t *birg);
542 static const arch_code_generator_if_t arm_code_gen_if = {
544 arm_before_abi, /* before abi introduce */
547 arm_before_sched, /* before scheduling hook */
548 arm_before_ra, /* before register allocation hook */
549 NULL, /* after register allocation */
555 * Initializes the code generator.
557 static void *arm_cg_init(const be_irg_t *birg) {
558 static ir_type *int_tp = NULL;
559 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
563 /* create an integer type with machine size */
564 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
567 cg = xmalloc(sizeof(*cg));
568 cg->impl = &arm_code_gen_if;
570 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
571 cg->arch_env = birg->main_env->arch_env;
577 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
581 if (isa->num_codegens > 1)
586 cur_reg_set = cg->reg_set;
590 /* enter the current code generator */
593 return (arch_code_generator_t *)cg;
598 * Maps all intrinsic calls that the backend support
599 * and map all instructions the backend did not support
602 static void arm_handle_intrinsics(void) {
603 ir_type *tp, *int_tp, *uint_tp;
607 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
609 int_tp = new_type_primitive(ID("int"), mode_Is);
610 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
612 /* ARM has neither a signed div instruction ... */
615 i_instr_record *map_Div = &records[n_records++].i_instr;
617 tp = new_type_method(ID("rt_iDiv"), 2, 1);
618 set_method_param_type(tp, 0, int_tp);
619 set_method_param_type(tp, 1, int_tp);
620 set_method_res_type(tp, 0, int_tp);
622 rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
623 rt_Div.mode = mode_T;
624 rt_Div.mem_proj_nr = pn_Div_M;
625 rt_Div.exc_proj_nr = pn_Div_X_except;
626 rt_Div.exc_mem_proj_nr = pn_Div_M;
627 rt_Div.res_proj_nr = pn_Div_res;
629 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
631 map_Div->kind = INTRINSIC_INSTR;
632 map_Div->op = op_Div;
633 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
634 map_Div->ctx = &rt_Div;
636 /* ... nor a signed div instruction ... */
639 i_instr_record *map_Div = &records[n_records++].i_instr;
641 tp = new_type_method(ID("rt_uDiv"), 2, 1);
642 set_method_param_type(tp, 0, uint_tp);
643 set_method_param_type(tp, 1, uint_tp);
644 set_method_res_type(tp, 0, uint_tp);
646 rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
647 rt_Div.mode = mode_T;
648 rt_Div.mem_proj_nr = pn_Div_M;
649 rt_Div.exc_proj_nr = pn_Div_X_except;
650 rt_Div.exc_mem_proj_nr = pn_Div_M;
651 rt_Div.res_proj_nr = pn_Div_res;
653 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
655 map_Div->kind = INTRINSIC_INSTR;
656 map_Div->op = op_Div;
657 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
658 map_Div->ctx = &rt_Div;
660 /* ... nor a signed mod instruction ... */
663 i_instr_record *map_Mod = &records[n_records++].i_instr;
665 tp = new_type_method(ID("rt_iMod"), 2, 1);
666 set_method_param_type(tp, 0, int_tp);
667 set_method_param_type(tp, 1, int_tp);
668 set_method_res_type(tp, 0, int_tp);
670 rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
671 rt_Mod.mode = mode_T;
672 rt_Mod.mem_proj_nr = pn_Mod_M;
673 rt_Mod.exc_proj_nr = pn_Mod_X_except;
674 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
675 rt_Mod.res_proj_nr = pn_Mod_res;
677 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
679 map_Mod->kind = INTRINSIC_INSTR;
680 map_Mod->op = op_Mod;
681 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
682 map_Mod->ctx = &rt_Mod;
684 /* ... nor a unsigned mod. */
687 i_instr_record *map_Mod = &records[n_records++].i_instr;
689 tp = new_type_method(ID("rt_uMod"), 2, 1);
690 set_method_param_type(tp, 0, uint_tp);
691 set_method_param_type(tp, 1, uint_tp);
692 set_method_res_type(tp, 0, uint_tp);
694 rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
695 rt_Mod.mode = mode_T;
696 rt_Mod.mem_proj_nr = pn_Mod_M;
697 rt_Mod.exc_proj_nr = pn_Mod_X_except;
698 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
699 rt_Mod.res_proj_nr = pn_Mod_res;
701 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
703 map_Mod->kind = INTRINSIC_INSTR;
704 map_Mod->op = op_Mod;
705 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
706 map_Mod->ctx = &rt_Mod;
710 lower_intrinsics(records, n_records);
713 /*****************************************************************
714 * ____ _ _ _____ _____
715 * | _ \ | | | | |_ _|/ ____| /\
716 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
717 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
718 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
719 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
721 *****************************************************************/
723 static arm_isa_t arm_isa_template = {
724 &arm_isa_if, /* isa interface */
725 &arm_gp_regs[REG_SP], /* stack pointer */
726 &arm_gp_regs[REG_R11], /* base pointer */
727 -1, /* stack direction */
728 0, /* number of codegenerator objects */
729 0, /* use generic register names instead of SP, LR, PC */
730 NULL, /* current code generator */
731 NULL, /* output file */
732 ARM_FPU_ARCH_FPE, /* FPU architecture */
736 * Initializes the backend ISA and opens the output file.
738 static void *arm_init(FILE *file_handle) {
739 static int inited = 0;
745 isa = xmalloc(sizeof(*isa));
746 memcpy(isa, &arm_isa_template, sizeof(*isa));
748 arm_register_init(isa);
749 if (isa->gen_reg_names) {
750 /* patch register names */
751 arm_gp_regs[REG_R11].name = "r11";
752 arm_gp_regs[REG_SP].name = "r13";
753 arm_gp_regs[REG_LR].name = "r14";
754 arm_gp_regs[REG_PC].name = "r15";
758 isa->out = file_handle;
760 arm_create_opcodes();
761 arm_handle_intrinsics();
762 arm_switch_section(NULL, NO_SECTION);
771 * frees the ISA structure.
773 static void arm_done(void *self) {
779 * Report the number of register classes.
780 * If we don't have fp instructions, report only GP
781 * here to speed up register allocation (and makes dumps
782 * smaller and more readable).
784 static int arm_get_n_reg_class(const void *self) {
785 const arm_isa_t *isa = self;
787 return isa->cg->have_fp ? 2 : 1;
791 * Return the register class with requested index.
793 static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
794 return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa];
798 * Get the register class which shall be used to store a value of a given mode.
799 * @param self The this pointer.
800 * @param mode The mode in question.
801 * @return A register class which can hold values of the given mode.
803 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
804 if (mode_is_float(mode))
805 return &arm_reg_classes[CLASS_arm_fpa];
807 return &arm_reg_classes[CLASS_arm_gp];
811 * Produces the type which sits between the stack args and the locals on the stack.
812 * it will contain the return address and space to store the old base pointer.
813 * @return The Firm type modelling the ABI between type.
815 static ir_type *arm_get_between_type(void *self) {
816 static ir_type *between_type = NULL;
817 static entity *old_bp_ent = NULL;
820 entity *ret_addr_ent;
821 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
822 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
824 between_type = new_type_class(new_id_from_str("arm_between_type"));
825 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
826 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
828 set_entity_offset(old_bp_ent, 0);
829 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
830 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
838 be_abi_call_flags_bits_t flags;
839 const arch_env_t *arch_env;
840 const arch_isa_t *isa;
844 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
846 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
847 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
848 env->flags = fl.bits;
850 env->arch_env = arch_env;
851 env->isa = arch_env->isa;
855 static void arm_abi_dont_save_regs(void *self, pset *s)
857 arm_abi_env_t *env = self;
858 if (env->flags.try_omit_fp)
859 pset_insert_ptr(s, env->isa->bp);
865 * Build the ARM prolog
867 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
868 ir_node *keep, *store;
869 arm_abi_env_t *env = self;
870 ir_graph *irg = env->irg;
871 ir_node *block = get_irg_start_block(irg);
872 // ir_node *regs[16];
874 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
875 static const arm_register_req_t *fp_req[] = {
876 &arm_default_req_arm_gp_r11
879 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
880 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
881 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
882 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
883 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
884 // ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]);
885 // ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]);
886 // ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]);
887 // ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]);
889 if(env->flags.try_omit_fp)
892 ip = be_new_Copy(gp, irg, block, sp );
893 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
894 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
896 // if (r0) regs[n_regs++] = r0;
897 // if (r1) regs[n_regs++] = r1;
898 // if (r2) regs[n_regs++] = r2;
899 // if (r3) regs[n_regs++] = r3;
900 // sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
901 // set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
902 // arch_set_irn_register(env->arch_env, sp, env->isa->sp);
903 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
904 set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
905 // arch_set_irn_register(env->arch_env, store, env->isa->sp);
907 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
908 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
909 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
911 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
912 be_node_set_reg_class(keep, 1, gp);
913 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
914 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
916 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
917 new_tarval_from_long(4, get_irn_mode(fp)));
918 set_arm_req_out_all(fp, fp_req);
919 //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
920 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
922 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
923 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
924 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2);
925 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3);
926 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
927 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
928 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
929 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
930 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
935 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
936 arm_abi_env_t *env = self;
937 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
938 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
939 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
940 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
941 static const arm_register_req_t *sub12_req[] = {
942 &arm_default_req_arm_gp_sp
945 // TODO: Activate Omit fp in epilogue
946 if(env->flags.try_omit_fp) {
947 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
948 add_irn_dep(curr_sp, *mem);
950 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
951 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
952 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
953 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
955 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
956 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
957 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
961 tarval *tv = new_tarval_from_long(12,mode_Iu);
962 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
963 set_arm_req_out_all(sub12_node, sub12_req);
964 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
965 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
966 set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
967 set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
968 set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
969 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
970 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
971 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
972 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
973 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
974 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
975 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
977 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
978 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
979 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
980 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
983 static const be_abi_callbacks_t arm_abi_callbacks = {
986 arm_get_between_type,
987 arm_abi_dont_save_regs,
994 * Get the ABI restrictions for procedure calls.
995 * @param self The this pointer.
996 * @param method_type The type of the method (procedure) in question.
997 * @param abi The abi object to be modified
999 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1003 int n = get_method_n_params(method_type);
1004 be_abi_call_flags_t flags = {
1006 0, /* store from left to right */
1007 0, /* store arguments sequential */
1008 1, /* try to omit the frame pointer */
1009 1, /* the function can use any register as frame pointer */
1010 1 /* a call can take the callee's address as an immediate */
1014 /* set stack parameter passing style */
1015 be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
1017 for (i = 0; i < n; i++) {
1018 /* reg = get reg for param i; */
1019 /* be_abi_call_param_reg(abi, i, reg); */
1022 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1024 be_abi_call_param_stack(abi, i, 4, 0, 0);
1027 /* default: return value is in R0 resp. F0 */
1028 assert(get_method_n_ress(method_type) < 2);
1029 if (get_method_n_ress(method_type) > 0) {
1030 tp = get_method_res_type(method_type, 0);
1031 mode = get_type_mode(tp);
1033 be_abi_call_res_reg(abi, 0,
1034 mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]);
1038 static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1039 return &arm_irn_ops;
1042 const arch_irn_handler_t arm_irn_handler = {
1046 const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
1047 return &arm_irn_handler;
1050 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1051 return is_arm_irn(irn);
1055 * Initializes the code generator interface.
1057 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1058 return &arm_code_gen_if;
1061 list_sched_selector_t arm_sched_selector;
1064 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1066 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1067 memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1068 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1069 return &arm_sched_selector;
1072 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
1077 * Returns the necessary byte alignment for storing a register of given class.
1079 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1080 ir_mode *mode = arch_register_class_mode(cls);
1081 return get_mode_size_bytes(mode);
1084 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1090 static const be_machine_t *arm_get_machine(const void *self) {
1097 * Returns the libFirm configuration parameter for this backend.
1099 static const backend_params *arm_get_libfirm_params(void) {
1100 static arch_dep_params_t ad = {
1102 0, /* Muls are fast enough on ARM */
1103 31, /* shift would be ok */
1104 0, /* SMUL is needed, only in Arch M*/
1105 0, /* UMUL is needed, only in Arch M */
1106 32, /* SMUL & UMUL available for 32 bit */
1108 static backend_params p = {
1109 NULL, /* no additional opcodes */
1110 NULL, /* will be set later */
1111 1, /* need dword lowering */
1112 NULL, /* but yet no creator function */
1113 NULL, /* context for create_intrinsic_fkt */
1122 /* fpu set architectures. */
1123 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1124 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1125 { "fpe", ARM_FPU_ARCH_FPE },
1126 { "fpa", ARM_FPU_ARCH_FPA },
1127 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1128 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1129 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1133 static lc_opt_enum_int_var_t arch_fpu_var = {
1134 &arm_isa_template.fpu_arch, arm_fpu_items
1137 static const lc_opt_table_entry_t arm_options[] = {
1138 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1139 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1144 * Register command line options for the ARM backend.
1148 * arm-fpuunit=unit select the floating point unit
1149 * arm-gen_reg_names use generic register names instead of SP, LR, PC
1151 static void arm_register_options(lc_opt_entry_t *ent)
1153 lc_opt_entry_t *be_grp_arm = lc_opt_get_grp(ent, "arm");
1154 lc_opt_add_table(be_grp_arm, arm_options);
1156 #endif /* WITH_LIBCORE */
1158 const arch_isa_if_t arm_isa_if = {
1161 arm_get_n_reg_class,
1163 arm_get_reg_class_for_mode,
1165 arm_get_irn_handler,
1166 arm_get_code_generator_if,
1167 arm_get_list_sched_selector,
1168 arm_get_ilp_sched_selector,
1169 arm_get_reg_class_alignment,
1170 arm_get_libfirm_params,
1171 arm_get_allowed_execution_units,
1174 arm_register_options