2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Oliver Richter, Tobias Gneist
31 #include "lc_opts_enum.h"
33 #include "pseudo_irg.h"
40 #include "iroptimize.h"
47 #include "../bearch_t.h" /* the general register allocator interface */
48 #include "../benode_t.h"
49 #include "../belower.h"
50 #include "../besched_t.h"
53 #include "../bemachine.h"
54 #include "../beilpsched.h"
55 #include "../bemodule.h"
56 #include "../beirg_t.h"
57 #include "../bespillslots.h"
58 #include "../begnuas.h"
60 #include "bearch_arm_t.h"
62 #include "arm_new_nodes.h" /* arm nodes interface */
63 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
64 #include "arm_transform.h"
65 #include "arm_emitter.h"
66 #include "arm_map_regs.h"
68 #define DEBUG_MODULE "firm.be.arm.isa"
70 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
71 static set *cur_reg_set = NULL;
73 /**************************************************
76 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
77 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
78 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
79 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
82 **************************************************/
85 * Return register requirements for a arm node.
86 * If the node returns a tuple (mode_T) then the proj's
87 * will be asked for this information.
90 arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node,
93 long node_pos = pos == -1 ? 0 : pos;
94 ir_mode *mode = get_irn_mode(node);
97 if (is_Block(node) || mode == mode_X) {
98 return arch_no_register_req;
101 if (mode == mode_T && pos < 0) {
102 return arch_no_register_req;
107 return arch_no_register_req;
110 return arch_no_register_req;
113 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
114 node = skip_Proj_const(node);
117 /* get requirements for our own nodes */
118 if (is_arm_irn(node)) {
119 const arch_register_req_t *req;
121 req = get_arm_in_req(node, pos);
123 req = get_arm_out_req(node, node_pos);
129 /* unknown should be transformed by now */
130 assert(!is_Unknown(node));
131 return arch_no_register_req;
134 static void arm_set_irn_reg(const void *self, ir_node *irn,
135 const arch_register_t *reg)
140 if (get_irn_mode(irn) == mode_X) {
145 pos = get_Proj_proj(irn);
146 irn = skip_Proj(irn);
149 if (is_arm_irn(irn)) {
150 const arch_register_t **slots;
152 slots = get_arm_slots(irn);
156 /* here we set the registers for the Phi nodes */
157 arm_set_firm_reg(irn, reg, cur_reg_set);
161 static const arch_register_t *arm_get_irn_reg(const void *self,
165 const arch_register_t *reg = NULL;
170 if (get_irn_mode(irn) == mode_X) {
174 pos = get_Proj_proj(irn);
175 irn = skip_Proj_const(irn);
178 if (is_arm_irn(irn)) {
179 const arch_register_t **slots;
180 slots = get_arm_slots(irn);
184 reg = arm_get_firm_reg(irn, cur_reg_set);
190 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn)
193 irn = skip_Proj_const(irn);
196 return arch_irn_class_branch;
198 else if (is_arm_irn(irn)) {
199 return arch_irn_class_normal;
205 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn)
207 arch_irn_flags_t flags = arch_irn_flags_none;
210 if(is_Unknown(irn)) {
211 return arch_irn_flags_ignore;
214 if (is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
215 ir_node *pred = get_Proj_pred(irn);
216 if (is_arm_irn(pred)) {
217 flags = get_arm_out_flags(pred, get_Proj_proj(irn));
222 if (is_arm_irn(irn)) {
223 flags |= get_arm_flags(irn);
229 static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn)
233 /* TODO: return the entity assigned to the frame */
237 static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent)
242 /* TODO: set the entity assigned to the frame */
246 * This function is called by the generic backend to correct offsets for
247 * nodes accessing the stack.
249 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias)
254 /* TODO: correct offset if irn accesses the stack */
257 static int arm_get_sp_bias(const void *self, const ir_node *irn)
264 /* fill register allocator interface */
266 static const arch_irn_ops_t arm_irn_ops = {
272 arm_get_frame_entity,
273 arm_set_frame_entity,
276 NULL, /* get_inverse */
277 NULL, /* get_op_estimated_cost */
278 NULL, /* possible_memory_operand */
279 NULL, /* perform_memory_operand */
282 /**************************************************
285 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
286 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
287 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
288 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
291 **************************************************/
294 * Transforms the standard Firm graph into
297 static void arm_prepare_graph(void *self) {
298 arm_code_gen_t *cg = self;
300 /* transform nodes into assembler instructions */
301 arm_transform_graph(cg);
303 /* do local optimizations (mainly CSE) */
304 local_optimize_graph(cg->irg);
307 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
309 /* do code placement, to optimize the position of constants */
313 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
317 * Called immediately before emit phase.
319 static void arm_finish_irg(void *self)
322 /* TODO: - fix offsets for nodes accessing stack
329 * These are some hooks which must be filled but are probably not needed.
331 static void arm_before_sched(void *self)
334 /* Some stuff you need to do after scheduling but before register allocation */
337 static void arm_before_ra(void *self)
340 /* Some stuff you need to do immediately after register allocation */
344 * We transform Spill and Reload here. This needs to be done before
345 * stack biasing otherwise we would miss the corrected offset for these nodes.
347 static void arm_after_ra(void *self)
349 arm_code_gen_t *cg = self;
350 be_coalesce_spillslots(cg->birg);
354 * Emits the code, closes the output file and frees
355 * the code generator interface.
357 static void arm_emit_and_done(void *self) {
358 arm_code_gen_t *cg = self;
359 ir_graph *irg = cg->irg;
361 arm_gen_routine(cg, irg);
365 /* de-allocate code generator */
366 del_set(cg->reg_set);
371 * Move a double floating point value into an integer register.
372 * Place the move operation into block bl.
374 * Handle some special cases here:
375 * 1.) A constant: simply split into two
376 * 2.) A load: simply split into two
378 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
379 ir_node **resH, ir_node **resL) {
381 tarval *tv = get_Const_tarval(arg);
384 /* get the upper 32 bits */
385 v = get_tarval_sub_bits(tv, 7);
386 v = (v << 8) | get_tarval_sub_bits(tv, 6);
387 v = (v << 8) | get_tarval_sub_bits(tv, 5);
388 v = (v << 8) | get_tarval_sub_bits(tv, 4);
389 *resH = new_Const_long(mode_Is, v);
391 /* get the lower 32 bits */
392 v = get_tarval_sub_bits(tv, 3);
393 v = (v << 8) | get_tarval_sub_bits(tv, 2);
394 v = (v << 8) | get_tarval_sub_bits(tv, 1);
395 v = (v << 8) | get_tarval_sub_bits(tv, 0);
396 *resL = new_Const_long(mode_Is, v);
398 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
399 /* FIXME: handling of low/high depends on LE/BE here */
403 ir_graph *irg = current_ir_graph;
406 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
408 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
409 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
410 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
416 * Move a single floating point value into an integer register.
417 * Place the move operation into block bl.
419 * Handle some special cases here:
420 * 1.) A constant: simply move
421 * 2.) A load: simply load
423 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg)
428 tarval *tv = get_Const_tarval(arg);
431 /* get the lower 32 bits */
432 v = get_tarval_sub_bits(tv, 3);
433 v = (v << 8) | get_tarval_sub_bits(tv, 2);
434 v = (v << 8) | get_tarval_sub_bits(tv, 1);
435 v = (v << 8) | get_tarval_sub_bits(tv, 0);
436 return new_Const_long(mode_Is, v);
438 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
441 load = skip_Proj(arg);
448 * Convert the arguments of a call to support the
449 * ARM calling convention of general purpose AND floating
452 static void handle_calls(ir_node *call, void *env)
454 arm_code_gen_t *cg = env;
455 int i, j, n, size, idx, flag, n_param, n_res, first_variadic;
456 ir_type *mtp, *new_mtd, *new_tp[5];
457 ir_node *new_in[5], **in;
463 /* check, if we need conversions */
464 n = get_Call_n_params(call);
465 mtp = get_Call_type(call);
466 assert(get_method_n_params(mtp) == n);
468 /* it's always enough to handle the first 4 parameters */
471 flag = size = idx = 0;
472 bl = get_nodes_block(call);
473 for (i = 0; i < n; ++i) {
474 ir_type *param_tp = get_method_param_type(mtp, i);
476 if (is_compound_type(param_tp)) {
477 /* an aggregate parameter: bad case */
481 /* a primitive parameter */
482 ir_mode *mode = get_type_mode(param_tp);
484 if (mode_is_float(mode)) {
485 if (get_mode_size_bits(mode) > 32) {
486 ir_node *mem = get_Call_mem(call);
488 /* Beware: ARM wants the high part first */
490 new_tp[idx] = cg->int_tp;
491 new_tp[idx+1] = cg->int_tp;
492 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
494 set_Call_mem(call, mem);
498 new_tp[idx] = cg->int_tp;
499 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
506 new_tp[idx] = param_tp;
507 new_in[idx] = get_Call_param(call, i);
516 /* if flag is NOT set, no need to translate the method type */
520 /* construct a new method type */
522 n_param = get_method_n_params(mtp) - n + idx;
523 n_res = get_method_n_ress(mtp);
524 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
526 for (i = 0; i < idx; ++i)
527 set_method_param_type(new_mtd, i, new_tp[i]);
528 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
529 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
530 for (i = 0; i < n_res; ++i)
531 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
533 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
534 first_variadic = get_method_first_variadic_param_index(mtp);
535 if (first_variadic >= 0)
536 set_method_first_variadic_param_index(new_mtd, first_variadic);
538 if (is_lowered_type(mtp)) {
539 mtp = get_associated_type(mtp);
541 set_lowered_type(mtp, new_mtd);
543 set_Call_type(call, new_mtd);
545 /* calculate new in array of the Call */
546 NEW_ARR_A(ir_node *, in, n_param + 2);
547 for (i = 0; i < idx; ++i)
548 in[2 + i] = new_in[i];
549 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
550 in[2 + j++] = get_Call_param(call, i);
552 in[0] = get_Call_mem(call);
553 in[1] = get_Call_ptr(call);
555 /* finally, change the call inputs */
556 set_irn_in(call, n_param + 2, in);
560 * Handle graph transformations before the abi converter does its work.
562 static void arm_before_abi(void *self) {
563 arm_code_gen_t *cg = self;
565 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
569 static void *arm_cg_init(be_irg_t *birg);
571 static const arch_code_generator_if_t arm_code_gen_if = {
573 NULL, /* get_pic_base */
574 arm_before_abi, /* before abi introduce */
577 arm_before_sched, /* before scheduling hook */
578 arm_before_ra, /* before register allocation hook */
585 * Initializes the code generator.
587 static void *arm_cg_init(be_irg_t *birg) {
588 static ir_type *int_tp = NULL;
589 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env.isa;
593 /* create an integer type with machine size */
594 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
597 cg = xmalloc(sizeof(*cg));
598 cg->impl = &arm_code_gen_if;
600 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
601 cg->arch_env = &birg->main_env->arch_env;
605 cg->have_fp_insn = 0;
606 cg->unknown_gp = NULL;
607 cg->unknown_fpa = NULL;
608 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
610 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
612 cur_reg_set = cg->reg_set;
614 /* enter the current code generator */
617 return (arch_code_generator_t *)cg;
622 * Maps all intrinsic calls that the backend support
623 * and map all instructions the backend did not support
626 static void arm_handle_intrinsics(void) {
627 ir_type *tp, *int_tp, *uint_tp;
631 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
633 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
635 int_tp = new_type_primitive(ID("int"), mode_Is);
636 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
638 /* ARM has neither a signed div instruction ... */
640 i_instr_record *map_Div = &records[n_records++].i_instr;
642 tp = new_type_method(ID("rt_iDiv"), 2, 1);
643 set_method_param_type(tp, 0, int_tp);
644 set_method_param_type(tp, 1, int_tp);
645 set_method_res_type(tp, 0, int_tp);
647 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
648 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
649 rt_iDiv.mode = mode_T;
650 rt_iDiv.res_mode = mode_Is;
651 rt_iDiv.mem_proj_nr = pn_Div_M;
652 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
653 rt_iDiv.exc_proj_nr = pn_Div_X_except;
654 rt_iDiv.exc_mem_proj_nr = pn_Div_M;
655 rt_iDiv.res_proj_nr = pn_Div_res;
657 set_entity_visibility(rt_iDiv.ent, visibility_external_allocated);
659 map_Div->kind = INTRINSIC_INSTR;
660 map_Div->op = op_Div;
661 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
662 map_Div->ctx = &rt_iDiv;
664 /* ... nor an unsigned div instruction ... */
666 i_instr_record *map_Div = &records[n_records++].i_instr;
668 tp = new_type_method(ID("rt_uDiv"), 2, 1);
669 set_method_param_type(tp, 0, uint_tp);
670 set_method_param_type(tp, 1, uint_tp);
671 set_method_res_type(tp, 0, uint_tp);
673 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
674 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
675 rt_uDiv.mode = mode_T;
676 rt_uDiv.res_mode = mode_Iu;
677 rt_uDiv.mem_proj_nr = pn_Div_M;
678 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
679 rt_uDiv.exc_proj_nr = pn_Div_X_except;
680 rt_uDiv.exc_mem_proj_nr = pn_Div_M;
681 rt_uDiv.res_proj_nr = pn_Div_res;
683 set_entity_visibility(rt_uDiv.ent, visibility_external_allocated);
685 map_Div->kind = INTRINSIC_INSTR;
686 map_Div->op = op_Div;
687 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
688 map_Div->ctx = &rt_uDiv;
690 /* ... nor a signed mod instruction ... */
692 i_instr_record *map_Mod = &records[n_records++].i_instr;
694 tp = new_type_method(ID("rt_iMod"), 2, 1);
695 set_method_param_type(tp, 0, int_tp);
696 set_method_param_type(tp, 1, int_tp);
697 set_method_res_type(tp, 0, int_tp);
699 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
700 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
701 rt_iMod.mode = mode_T;
702 rt_iMod.res_mode = mode_Is;
703 rt_iMod.mem_proj_nr = pn_Mod_M;
704 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
705 rt_iMod.exc_proj_nr = pn_Mod_X_except;
706 rt_iMod.exc_mem_proj_nr = pn_Mod_M;
707 rt_iMod.res_proj_nr = pn_Mod_res;
709 set_entity_visibility(rt_iMod.ent, visibility_external_allocated);
711 map_Mod->kind = INTRINSIC_INSTR;
712 map_Mod->op = op_Mod;
713 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
714 map_Mod->ctx = &rt_iMod;
716 /* ... nor an unsigned mod. */
718 i_instr_record *map_Mod = &records[n_records++].i_instr;
720 tp = new_type_method(ID("rt_uMod"), 2, 1);
721 set_method_param_type(tp, 0, uint_tp);
722 set_method_param_type(tp, 1, uint_tp);
723 set_method_res_type(tp, 0, uint_tp);
725 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
726 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
727 rt_uMod.mode = mode_T;
728 rt_uMod.res_mode = mode_Iu;
729 rt_uMod.mem_proj_nr = pn_Mod_M;
730 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
731 rt_uMod.exc_proj_nr = pn_Mod_X_except;
732 rt_uMod.exc_mem_proj_nr = pn_Mod_M;
733 rt_uMod.res_proj_nr = pn_Mod_res;
735 set_entity_visibility(rt_uMod.ent, visibility_external_allocated);
737 map_Mod->kind = INTRINSIC_INSTR;
738 map_Mod->op = op_Mod;
739 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
740 map_Mod->ctx = &rt_uMod;
744 lower_intrinsics(records, n_records, /*part_block_used=*/0);
747 /*****************************************************************
748 * ____ _ _ _____ _____
749 * | _ \ | | | | |_ _|/ ____| /\
750 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
751 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
752 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
753 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
755 *****************************************************************/
757 static arm_isa_t arm_isa_template = {
759 &arm_isa_if, /* isa interface */
760 &arm_gp_regs[REG_SP], /* stack pointer */
761 &arm_gp_regs[REG_R11], /* base pointer */
762 -1, /* stack direction */
763 1, /* stack alignment for calls */
764 NULL, /* main environment */
766 5, /* reload costs */
768 0, /* use generic register names instead of SP, LR, PC */
769 ARM_FPU_ARCH_FPE, /* FPU architecture */
770 NULL, /* current code generator */
774 * Initializes the backend ISA and opens the output file.
776 static void *arm_init(FILE *file_handle) {
777 static int inited = 0;
783 isa = xmalloc(sizeof(*isa));
784 memcpy(isa, &arm_isa_template, sizeof(*isa));
789 be_emit_init(file_handle);
791 arm_create_opcodes(&arm_irn_ops);
792 arm_handle_intrinsics();
794 /* we mark referenced global entities, so we can only emit those which
795 * are actually referenced. (Note: you mustn't use the type visited flag
796 * elsewhere in the backend)
798 inc_master_type_visited();
807 * Closes the output file and frees the ISA structure.
809 static void arm_done(void *self) {
810 arm_isa_t *isa = self;
812 be_gas_emit_decls(isa->arch_isa.main_env, 1);
820 * Report the number of register classes.
821 * If we don't have fp instructions, report only GP
822 * here to speed up register allocation (and makes dumps
823 * smaller and more readable).
825 static unsigned arm_get_n_reg_class(const void *self) {
831 * Return the register class with requested index.
833 static const arch_register_class_t *arm_get_reg_class(const void *self,
836 assert(i < N_CLASSES);
837 return &arm_reg_classes[i];
841 * Get the register class which shall be used to store a value of a given mode.
842 * @param self The this pointer.
843 * @param mode The mode in question.
844 * @return A register class which can hold values of the given mode.
846 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
848 if (mode_is_float(mode))
849 return &arm_reg_classes[CLASS_arm_fpa];
851 return &arm_reg_classes[CLASS_arm_gp];
855 * Produces the type which sits between the stack args and the locals on the stack.
856 * it will contain the return address and space to store the old base pointer.
857 * @return The Firm type modeling the ABI between type.
859 static ir_type *arm_get_between_type(void *self) {
860 static ir_type *between_type = NULL;
861 static ir_entity *old_bp_ent = NULL;
864 if (between_type == NULL) {
865 ir_entity *ret_addr_ent;
866 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
867 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
869 between_type = new_type_class(new_id_from_str("arm_between_type"));
870 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
871 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
873 set_entity_offset(old_bp_ent, 0);
874 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
875 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
883 be_abi_call_flags_bits_t flags;
884 const arch_env_t *arch_env;
885 const arch_isa_t *isa;
889 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
891 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
892 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
893 env->flags = fl.bits;
895 env->arch_env = arch_env;
896 env->isa = arch_env->isa;
900 static void arm_abi_dont_save_regs(void *self, pset *s)
902 arm_abi_env_t *env = self;
903 if (env->flags.try_omit_fp)
904 pset_insert_ptr(s, env->isa->bp);
910 * Build the ARM prolog
912 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
913 ir_node *keep, *store;
914 arm_abi_env_t *env = self;
915 ir_graph *irg = env->irg;
916 ir_node *block = get_irg_start_block(irg);
917 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
919 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
920 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
921 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
922 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
923 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
925 if (env->flags.try_omit_fp)
928 ip = be_new_Copy(gp, irg, block, sp);
929 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
930 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
932 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
934 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
935 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
936 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
938 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
939 be_node_set_reg_class(keep, 1, gp);
940 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
941 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
943 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp), 4);
944 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
946 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
947 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
948 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
949 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
950 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
956 * Builds the ARM epilogue
958 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
959 arm_abi_env_t *env = self;
960 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
961 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
962 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
963 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
965 // TODO: Activate Omit fp in epilogue
966 if (env->flags.try_omit_fp) {
967 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
968 add_irn_dep(curr_sp, *mem);
970 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
971 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
972 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
973 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
975 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
976 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
977 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
978 be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
982 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, 12);
984 //set_arm_req_out_all(sub12_node, sub12_req);
985 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
986 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
988 //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
989 //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
990 //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
991 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
992 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
993 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
994 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
995 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
996 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
997 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
999 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
1000 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
1001 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
1002 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
1005 static const be_abi_callbacks_t arm_abi_callbacks = {
1008 arm_get_between_type,
1009 arm_abi_dont_save_regs,
1016 * Get the ABI restrictions for procedure calls.
1017 * @param self The this pointer.
1018 * @param method_type The type of the method (procedure) in question.
1019 * @param abi The abi object to be modified
1021 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1025 int n = get_method_n_params(method_type);
1026 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1029 /* set abi flags for calls */
1030 call_flags.bits.left_to_right = 0;
1031 call_flags.bits.store_args_sequential = 0;
1032 /* call_flags.bits.try_omit_fp don't change this we can handle both */
1033 call_flags.bits.fp_free = 0;
1034 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1036 /* set stack parameter passing style */
1037 be_abi_call_set_flags(abi, call_flags, &arm_abi_callbacks);
1039 for (i = 0; i < n; i++) {
1040 /* reg = get reg for param i; */
1041 /* be_abi_call_param_reg(abi, i, reg); */
1043 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1045 tp = get_method_param_type(method_type, i);
1046 mode = get_type_mode(tp);
1047 be_abi_call_param_stack(abi, i, mode, 4, 0, 0);
1051 /* set return registers */
1052 n = get_method_n_ress(method_type);
1054 assert(n <= 2 && "more than two results not supported");
1056 /* In case of 64bit returns, we will have two 32bit values */
1058 tp = get_method_res_type(method_type, 0);
1059 mode = get_type_mode(tp);
1061 assert(!mode_is_float(mode) && "two FP results not supported");
1063 tp = get_method_res_type(method_type, 1);
1064 mode = get_type_mode(tp);
1066 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1068 be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0]);
1069 be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1]);
1070 } else if (n == 1) {
1071 const arch_register_t *reg;
1073 tp = get_method_res_type(method_type, 0);
1074 assert(is_atomic_type(tp));
1075 mode = get_type_mode(tp);
1077 reg = mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0];
1078 be_abi_call_res_reg(abi, 0, reg);
1082 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1084 if(!is_arm_irn(irn))
1091 * Initializes the code generator interface.
1093 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1095 return &arm_code_gen_if;
1098 list_sched_selector_t arm_sched_selector;
1101 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1103 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1105 memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
1106 /* arm_sched_selector.exectime = arm_sched_exectime; */
1107 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1108 return &arm_sched_selector;
1112 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
1118 * Returns the necessary byte alignment for storing a register of given class.
1120 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1123 /* ARM is a 32 bit CPU, no need for other alignment */
1127 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1135 static const be_machine_t *arm_get_machine(const void *self) {
1143 * Return irp irgs in the desired order.
1145 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
1152 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1153 * @return 1 if allowed, 0 otherwise
1155 static int arm_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) {
1156 ir_node *cmp, *cmp_a, *phi;
1160 /* currently Psi support is not implemented */
1163 /* we don't want long long Psi */
1164 #define IS_BAD_PSI_MODE(mode) (!mode_is_float(mode) && get_mode_size_bits(mode) > 32)
1166 if (get_irn_mode(sel) != mode_b)
1169 cmp = get_Proj_pred(sel);
1170 cmp_a = get_Cmp_left(cmp);
1171 mode = get_irn_mode(cmp_a);
1173 if (IS_BAD_PSI_MODE(mode))
1176 /* check the Phi nodes */
1177 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1178 ir_node *pred_i = get_irn_n(phi, i);
1179 ir_node *pred_j = get_irn_n(phi, j);
1180 ir_mode *mode_i = get_irn_mode(pred_i);
1181 ir_mode *mode_j = get_irn_mode(pred_j);
1183 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1187 #undef IS_BAD_PSI_MODE
1193 * Returns the libFirm configuration parameter for this backend.
1195 static const backend_params *arm_get_libfirm_params(void) {
1196 static const ir_settings_if_conv_t ifconv = {
1197 4, /* maxdepth, doesn't matter for Psi-conversion */
1198 arm_is_psi_allowed /* allows or disallows Psi creation for given selector */
1200 static ir_settings_arch_dep_t ad = {
1202 1, /* Muls are fast enough on ARM but ... */
1203 31, /* ... one shift would be possible better */
1204 NULL, /* no evaluator function */
1205 0, /* SMUL is needed, only in Arch M */
1206 0, /* UMUL is needed, only in Arch M */
1207 32, /* SMUL & UMUL available for 32 bit */
1209 static backend_params p = {
1210 1, /* need dword lowering */
1211 0, /* don't support inline assembler yet */
1212 NULL, /* no additional opcodes */
1213 NULL, /* will be set later */
1214 NULL, /* but yet no creator function */
1215 NULL, /* context for create_intrinsic_fkt */
1216 NULL, /* will be set below */
1220 p.if_conv_info = &ifconv;
1224 /* fpu set architectures. */
1225 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1226 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1227 { "fpe", ARM_FPU_ARCH_FPE },
1228 { "fpa", ARM_FPU_ARCH_FPA },
1229 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1230 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1231 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1235 static lc_opt_enum_int_var_t arch_fpu_var = {
1236 &arm_isa_template.fpu_arch, arm_fpu_items
1239 static const lc_opt_table_entry_t arm_options[] = {
1240 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1241 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1245 const arch_isa_if_t arm_isa_if = {
1248 arm_get_n_reg_class,
1250 arm_get_reg_class_for_mode,
1252 arm_get_code_generator_if,
1253 arm_get_list_sched_selector,
1254 arm_get_ilp_sched_selector,
1255 arm_get_reg_class_alignment,
1256 arm_get_libfirm_params,
1257 arm_get_allowed_execution_units,
1262 void be_init_arch_arm(void)
1264 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1265 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1267 lc_opt_add_table(arm_grp, arm_options);
1269 be_register_isa_if("arm", &arm_isa_if);
1271 arm_init_transform();
1275 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);