2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist
29 #include "lc_opts_enum.h"
31 #include "pseudo_irg.h"
38 #include "iroptimize.h"
48 #include "../bearch.h"
49 #include "../benode.h"
50 #include "../belower.h"
51 #include "../besched.h"
53 #include "../bemachine.h"
54 #include "../beilpsched.h"
55 #include "../bemodule.h"
57 #include "../bespillslots.h"
58 #include "../begnuas.h"
59 #include "../belistsched.h"
60 #include "../beflags.h"
62 #include "bearch_arm_t.h"
64 #include "arm_new_nodes.h"
65 #include "gen_arm_regalloc_if.h"
66 #include "arm_transform.h"
67 #include "arm_optimize.h"
68 #include "arm_emitter.h"
69 #include "arm_map_regs.h"
71 static arch_irn_class_t arm_classify(const ir_node *irn)
74 /* TODO: we should mark reload/spill instructions and classify them here */
78 static ir_entity *arm_get_frame_entity(const ir_node *irn)
80 const arm_attr_t *attr = get_arm_attr_const(irn);
82 if (is_arm_FrameAddr(irn)) {
83 const arm_SymConst_attr_t *attr = get_irn_generic_attr_const(irn);
86 if (attr->is_load_store) {
87 const arm_load_store_attr_t *load_store_attr
88 = get_arm_load_store_attr_const(irn);
89 if (load_store_attr->is_frame_entity) {
90 return load_store_attr->entity;
96 static void arm_set_frame_entity(ir_node *irn, ir_entity *ent)
100 panic("arm_set_frame_entity() called. This should not happen.");
104 * This function is called by the generic backend to correct offsets for
105 * nodes accessing the stack.
107 static void arm_set_stack_bias(ir_node *irn, int bias)
109 if (is_arm_FrameAddr(irn)) {
110 arm_SymConst_attr_t *attr = get_irn_generic_attr(irn);
111 attr->fp_offset += bias;
113 arm_load_store_attr_t *attr = get_arm_load_store_attr(irn);
114 assert(attr->base.is_load_store);
115 attr->offset += bias;
119 static int arm_get_sp_bias(const ir_node *irn)
121 /* We don't have any nodes changing the stack pointer.
122 We probably want to support post-/pre increment/decrement later */
127 /* fill register allocator interface */
129 static const arch_irn_ops_t arm_irn_ops = {
132 arm_get_frame_entity,
133 arm_set_frame_entity,
136 NULL, /* get_inverse */
137 NULL, /* get_op_estimated_cost */
138 NULL, /* possible_memory_operand */
139 NULL, /* perform_memory_operand */
143 * Transforms the standard Firm graph into
146 static void arm_prepare_graph(void *self)
148 arm_code_gen_t *cg = self;
150 /* transform nodes into assembler instructions */
151 arm_transform_graph(cg);
153 /* do local optimizations (mainly CSE) */
154 local_optimize_graph(cg->irg);
157 dump_ir_graph(cg->irg, "transformed");
159 /* do code placement, to optimize the position of constants */
163 dump_ir_graph(cg->irg, "place");
167 * Called immediately before emit phase.
169 static void arm_finish_irg(void *self)
171 arm_code_gen_t *cg = self;
173 /* do peephole optimizations and fix stack offsets */
174 arm_peephole_optimization(cg);
177 static ir_node *arm_flags_remat(ir_node *node, ir_node *after)
182 if (is_Block(after)) {
185 block = get_nodes_block(after);
187 copy = exact_copy(node);
188 set_nodes_block(copy, block);
189 sched_add_after(after, copy);
193 static void arm_before_ra(void *self)
195 arm_code_gen_t *cg = self;
197 be_sched_fix_flags(cg->irg, &arm_reg_classes[CLASS_arm_flags],
201 static void transform_Reload(ir_node *node)
203 ir_node *block = get_nodes_block(node);
204 dbg_info *dbgi = get_irn_dbg_info(node);
205 ir_node *ptr = get_irn_n(node, be_pos_Reload_frame);
206 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
207 ir_mode *mode = get_irn_mode(node);
208 ir_entity *entity = be_get_frame_entity(node);
209 const arch_register_t *reg;
213 ir_node *sched_point = sched_prev(node);
215 load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true);
216 sched_add_after(sched_point, load);
219 proj = new_rd_Proj(dbgi, load, mode, pn_arm_Ldr_res);
221 reg = arch_get_irn_register(node);
222 arch_set_irn_register(proj, reg);
224 exchange(node, proj);
227 static void transform_Spill(ir_node *node)
229 ir_node *block = get_nodes_block(node);
230 dbg_info *dbgi = get_irn_dbg_info(node);
231 ir_node *ptr = get_irn_n(node, be_pos_Spill_frame);
232 ir_node *mem = new_NoMem();
233 ir_node *val = get_irn_n(node, be_pos_Spill_val);
234 ir_mode *mode = get_irn_mode(val);
235 ir_entity *entity = be_get_frame_entity(node);
236 ir_node *sched_point;
239 sched_point = sched_prev(node);
240 store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0,
244 sched_add_after(sched_point, store);
246 exchange(node, store);
249 static void arm_after_ra_walker(ir_node *block, void *data)
251 ir_node *node, *prev;
254 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
255 prev = sched_prev(node);
257 if (be_is_Reload(node)) {
258 transform_Reload(node);
259 } else if (be_is_Spill(node)) {
260 transform_Spill(node);
265 static void arm_after_ra(void *self)
267 arm_code_gen_t *cg = self;
268 be_coalesce_spillslots(cg->irg);
270 irg_block_walk_graph(cg->irg, NULL, arm_after_ra_walker, NULL);
274 * Emits the code, closes the output file and frees
275 * the code generator interface.
277 static void arm_emit_and_done(void *self)
279 arm_code_gen_t *cg = self;
280 ir_graph *irg = cg->irg;
282 arm_gen_routine(cg, irg);
284 /* de-allocate code generator */
285 del_set(cg->reg_set);
290 static void *arm_cg_init(ir_graph *irg);
292 static const arch_code_generator_if_t arm_code_gen_if = {
294 NULL, /* get_pic_base */
295 NULL, /* before abi introduce */
298 arm_before_ra, /* before register allocation hook */
305 * Initializes the code generator.
307 static void *arm_cg_init(ir_graph *irg)
309 static ir_type *int_tp = NULL;
310 arm_isa_t *isa = (arm_isa_t *) be_get_irg_arch_env(irg);
314 /* create an integer type with machine size */
315 int_tp = new_type_primitive(mode_Is);
318 cg = XMALLOC(arm_code_gen_t);
319 cg->impl = &arm_code_gen_if;
321 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
324 cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
326 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
328 /* enter the current code generator */
331 return (arch_code_generator_t *)cg;
336 * Maps all intrinsic calls that the backend support
337 * and map all instructions the backend did not support
340 static void arm_handle_intrinsics(void)
342 ir_type *tp, *int_tp, *uint_tp;
346 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
348 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
350 int_tp = new_type_primitive(mode_Is);
351 uint_tp = new_type_primitive(mode_Iu);
353 /* ARM has neither a signed div instruction ... */
355 i_instr_record *map_Div = &records[n_records++].i_instr;
357 tp = new_type_method(2, 1);
358 set_method_param_type(tp, 0, int_tp);
359 set_method_param_type(tp, 1, int_tp);
360 set_method_res_type(tp, 0, int_tp);
362 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
363 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
364 rt_iDiv.mode = mode_T;
365 rt_iDiv.res_mode = mode_Is;
366 rt_iDiv.mem_proj_nr = pn_Div_M;
367 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
368 rt_iDiv.exc_proj_nr = pn_Div_X_except;
369 rt_iDiv.exc_mem_proj_nr = pn_Div_M;
370 rt_iDiv.res_proj_nr = pn_Div_res;
372 add_entity_linkage(rt_iDiv.ent, IR_LINKAGE_CONSTANT);
373 set_entity_visibility(rt_iDiv.ent, ir_visibility_external);
375 map_Div->kind = INTRINSIC_INSTR;
376 map_Div->op = op_Div;
377 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
378 map_Div->ctx = &rt_iDiv;
380 /* ... nor an unsigned div instruction ... */
382 i_instr_record *map_Div = &records[n_records++].i_instr;
384 tp = new_type_method(2, 1);
385 set_method_param_type(tp, 0, uint_tp);
386 set_method_param_type(tp, 1, uint_tp);
387 set_method_res_type(tp, 0, uint_tp);
389 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
390 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
391 rt_uDiv.mode = mode_T;
392 rt_uDiv.res_mode = mode_Iu;
393 rt_uDiv.mem_proj_nr = pn_Div_M;
394 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
395 rt_uDiv.exc_proj_nr = pn_Div_X_except;
396 rt_uDiv.exc_mem_proj_nr = pn_Div_M;
397 rt_uDiv.res_proj_nr = pn_Div_res;
399 set_entity_visibility(rt_uDiv.ent, ir_visibility_external);
401 map_Div->kind = INTRINSIC_INSTR;
402 map_Div->op = op_Div;
403 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
404 map_Div->ctx = &rt_uDiv;
406 /* ... nor a signed mod instruction ... */
408 i_instr_record *map_Mod = &records[n_records++].i_instr;
410 tp = new_type_method(2, 1);
411 set_method_param_type(tp, 0, int_tp);
412 set_method_param_type(tp, 1, int_tp);
413 set_method_res_type(tp, 0, int_tp);
415 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
416 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
417 rt_iMod.mode = mode_T;
418 rt_iMod.res_mode = mode_Is;
419 rt_iMod.mem_proj_nr = pn_Mod_M;
420 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
421 rt_iMod.exc_proj_nr = pn_Mod_X_except;
422 rt_iMod.exc_mem_proj_nr = pn_Mod_M;
423 rt_iMod.res_proj_nr = pn_Mod_res;
425 set_entity_visibility(rt_iMod.ent, ir_visibility_external);
427 map_Mod->kind = INTRINSIC_INSTR;
428 map_Mod->op = op_Mod;
429 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
430 map_Mod->ctx = &rt_iMod;
432 /* ... nor an unsigned mod. */
434 i_instr_record *map_Mod = &records[n_records++].i_instr;
436 tp = new_type_method(2, 1);
437 set_method_param_type(tp, 0, uint_tp);
438 set_method_param_type(tp, 1, uint_tp);
439 set_method_res_type(tp, 0, uint_tp);
441 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
442 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
443 rt_uMod.mode = mode_T;
444 rt_uMod.res_mode = mode_Iu;
445 rt_uMod.mem_proj_nr = pn_Mod_M;
446 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
447 rt_uMod.exc_proj_nr = pn_Mod_X_except;
448 rt_uMod.exc_mem_proj_nr = pn_Mod_M;
449 rt_uMod.res_proj_nr = pn_Mod_res;
451 set_entity_visibility(rt_uMod.ent, ir_visibility_external);
453 map_Mod->kind = INTRINSIC_INSTR;
454 map_Mod->op = op_Mod;
455 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
456 map_Mod->ctx = &rt_uMod;
460 lower_intrinsics(records, n_records, /*part_block_used=*/0);
464 static arm_isa_t arm_isa_template = {
466 &arm_isa_if, /* isa interface */
467 &arm_gp_regs[REG_SP], /* stack pointer */
468 &arm_gp_regs[REG_R11], /* base pointer */
469 &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */
470 -1, /* stack direction */
471 2, /* power of two stack alignment for calls, 2^2 == 4 */
472 NULL, /* main environment */
474 5, /* reload costs */
475 true, /* we do have custom abi handling */
477 0, /* use generic register names instead of SP, LR, PC */
478 ARM_FPU_ARCH_FPE, /* FPU architecture */
479 NULL, /* current code generator */
483 * Initializes the backend ISA and opens the output file.
485 static arch_env_t *arm_init(FILE *file_handle)
487 static int inited = 0;
493 isa = XMALLOC(arm_isa_t);
494 memcpy(isa, &arm_isa_template, sizeof(*isa));
499 be_emit_init(file_handle);
501 arm_create_opcodes(&arm_irn_ops);
502 arm_handle_intrinsics();
504 be_gas_emit_types = false;
506 /* needed for the debug support */
507 be_gas_emit_switch_section(GAS_SECTION_TEXT);
508 be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
509 be_emit_write_line();
512 return &isa->arch_env;
518 * Closes the output file and frees the ISA structure.
520 static void arm_done(void *self)
522 arm_isa_t *isa = self;
524 be_gas_emit_decls(isa->arch_env.main_env);
532 * Report the number of register classes.
533 * If we don't have fp instructions, report only GP
534 * here to speed up register allocation (and makes dumps
535 * smaller and more readable).
537 static unsigned arm_get_n_reg_class(void)
543 * Return the register class with requested index.
545 static const arch_register_class_t *arm_get_reg_class(unsigned i)
547 assert(i < N_CLASSES);
548 return &arm_reg_classes[i];
552 * Get the register class which shall be used to store a value of a given mode.
553 * @param self The this pointer.
554 * @param mode The mode in question.
555 * @return A register class which can hold values of the given mode.
557 static const arch_register_class_t *arm_get_reg_class_for_mode(const ir_mode *mode)
559 if (mode_is_float(mode))
560 return &arm_reg_classes[CLASS_arm_fpa];
562 return &arm_reg_classes[CLASS_arm_gp];
565 static int arm_to_appear_in_schedule(void *block_env, const ir_node *irn)
568 if (!is_arm_irn(irn))
575 * Initializes the code generator interface.
577 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self)
580 return &arm_code_gen_if;
583 list_sched_selector_t arm_sched_selector;
586 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
588 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector)
591 memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
592 /* arm_sched_selector.exectime = arm_sched_exectime; */
593 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
594 return &arm_sched_selector;
598 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self)
605 * Returns the necessary byte alignment for storing a register of given class.
607 static int arm_get_reg_class_alignment(const arch_register_class_t *cls)
610 /* ARM is a 32 bit CPU, no need for other alignment */
614 static const be_execution_unit_t ***arm_get_allowed_execution_units(const ir_node *irn)
618 panic("Unimplemented arm_get_allowed_execution_units()");
621 static const be_machine_t *arm_get_machine(const void *self)
625 panic("Unimplemented arm_get_machine()");
629 * Return irp irgs in the desired order.
631 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list)
639 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
640 * @return 1 if allowed, 0 otherwise
642 static int arm_is_mux_allowed(ir_node *sel, ir_node *mux_false,
652 static asm_constraint_flags_t arm_parse_asm_constraint(const char **c)
654 /* asm not supported */
656 return ASM_CONSTRAINT_FLAG_INVALID;
659 static int arm_is_valid_clobber(const char *clobber)
666 * Returns the libFirm configuration parameter for this backend.
668 static const backend_params *arm_get_libfirm_params(void)
670 static const ir_settings_if_conv_t ifconv = {
671 4, /* maxdepth, doesn't matter for Psi-conversion */
672 arm_is_mux_allowed /* allows or disallows Mux creation for given selector */
674 static ir_settings_arch_dep_t ad = {
676 1, /* Muls are fast enough on ARM but ... */
677 31, /* ... one shift would be possible better */
678 NULL, /* no evaluator function */
679 0, /* SMUL is needed, only in Arch M */
680 0, /* UMUL is needed, only in Arch M */
681 32, /* SMUL & UMUL available for 32 bit */
683 static backend_params p = {
684 1, /* need dword lowering */
685 0, /* don't support inline assembler yet */
686 NULL, /* will be set later */
687 NULL, /* but yet no creator function */
688 NULL, /* context for create_intrinsic_fkt */
689 NULL, /* ifconv_info will be set below */
690 NULL, /* float arithmetic mode (TODO) */
691 0, /* no trampoline support: size 0 */
692 0, /* no trampoline support: align 0 */
693 NULL, /* no trampoline support: no trampoline builder */
694 4 /* alignment of stack parameter */
698 p.if_conv_info = &ifconv;
702 /* fpu set architectures. */
703 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
704 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
705 { "fpe", ARM_FPU_ARCH_FPE },
706 { "fpa", ARM_FPU_ARCH_FPA },
707 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
708 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
709 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
713 static lc_opt_enum_int_var_t arch_fpu_var = {
714 &arm_isa_template.fpu_arch, arm_fpu_items
717 static const lc_opt_table_entry_t arm_options[] = {
718 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
719 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
723 const arch_isa_if_t arm_isa_if = {
726 NULL, /* handle_intrinsics */
729 arm_get_reg_class_for_mode,
731 arm_get_code_generator_if,
732 arm_get_list_sched_selector,
733 arm_get_ilp_sched_selector,
734 arm_get_reg_class_alignment,
735 arm_get_libfirm_params,
736 arm_get_allowed_execution_units,
739 NULL, /* mark remat */
740 arm_parse_asm_constraint,
744 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);
745 void be_init_arch_arm(void)
747 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
748 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
750 lc_opt_add_table(arm_grp, arm_options);
752 be_register_isa_if("arm", &arm_isa_if);
754 arm_init_transform();