1 /* The main arm backend driver file. */
8 #include <libcore/lc_opts.h>
9 #include <libcore/lc_opts_enum.h>
11 #include "pseudo_irg.h"
17 #include "lower_intrinsics.h"
22 #include "../bearch_t.h" /* the general register allocator interface */
23 #include "../benode_t.h"
24 #include "../belower.h"
25 #include "../besched_t.h"
28 #include "../bemachine.h"
29 #include "../beilpsched.h"
30 #include "../bemodule.h"
31 #include "../beirg_t.h"
33 #include "bearch_arm_t.h"
35 #include "arm_new_nodes.h" /* arm nodes interface */
36 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
37 #include "arm_gen_decls.h" /* interface declaration emitter */
38 #include "arm_transform.h"
39 #include "arm_emitter.h"
40 #include "arm_map_regs.h"
42 #define DEBUG_MODULE "firm.be.arm.isa"
44 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
45 static set *cur_reg_set = NULL;
47 /**************************************************
50 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
51 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
52 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
53 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
56 **************************************************/
59 * Return register requirements for a arm node.
60 * If the node returns a tuple (mode_T) then the proj's
61 * will be asked for this information.
64 arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node,
66 long node_pos = pos == -1 ? 0 : pos;
67 ir_mode *mode = get_irn_mode(node);
68 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
70 if (is_Block(node) || mode == mode_X || mode == mode_M) {
71 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", node));
72 return arch_no_register_req;
75 if (mode == mode_T && pos < 0) {
76 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", node));
77 return arch_no_register_req;
80 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, node));
83 /* in case of a proj, we need to get the correct OUT slot */
84 /* of the node corresponding to the proj number */
86 node_pos = arm_translate_proj_pos(node);
92 node = skip_Proj_const(node);
94 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", node, node_pos));
97 /* get requirements for our own nodes */
98 if (is_arm_irn(node)) {
99 const arch_register_req_t *req;
101 req = get_arm_in_req(node, pos);
103 req = get_arm_out_req(node, node_pos);
106 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", node, pos));
110 /* unknown should be tranformed by now */
111 assert(!is_Unknown(node));
112 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", node));
114 return arch_no_register_req;
117 static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
122 if (get_irn_mode(irn) == mode_X) {
126 pos = arm_translate_proj_pos(irn);
127 irn = skip_Proj(irn);
130 if (is_arm_irn(irn)) {
131 const arch_register_t **slots;
133 slots = get_arm_slots(irn);
137 /* here we set the registers for the Phi nodes */
138 arm_set_firm_reg(irn, reg, cur_reg_set);
142 static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) {
144 const arch_register_t *reg = NULL;
148 if (get_irn_mode(irn) == mode_X) {
152 pos = arm_translate_proj_pos(irn);
153 irn = skip_Proj_const(irn);
156 if (is_arm_irn(irn)) {
157 const arch_register_t **slots;
158 slots = get_arm_slots(irn);
162 reg = arm_get_firm_reg(irn, cur_reg_set);
168 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
169 irn = skip_Proj_const(irn);
172 return arch_irn_class_branch;
174 else if (is_arm_irn(irn)) {
175 return arch_irn_class_normal;
181 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
182 irn = skip_Proj_const(irn);
184 if (is_arm_irn(irn)) {
185 return get_arm_flags(irn);
187 else if (is_Unknown(irn)) {
188 return arch_irn_flags_ignore;
194 static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
195 /* TODO: return the entity assigned to the frame */
199 static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
200 /* TODO: set the entity assigned to the frame */
204 * This function is called by the generic backend to correct offsets for
205 * nodes accessing the stack.
207 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
208 /* TODO: correct offset if irn accesses the stack */
211 static int arm_get_sp_bias(const void *self, const ir_node *irn) {
215 /* fill register allocator interface */
217 static const arch_irn_ops_if_t arm_irn_ops_if = {
223 arm_get_frame_entity,
224 arm_set_frame_entity,
227 NULL, /* get_inverse */
228 NULL, /* get_op_estimated_cost */
229 NULL, /* possible_memory_operand */
230 NULL, /* perform_memory_operand */
233 arm_irn_ops_t arm_irn_ops = {
240 /**************************************************
243 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
244 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
245 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
246 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
249 **************************************************/
252 * Transforms the standard Firm graph into
255 static void arm_prepare_graph(void *self) {
256 arm_code_gen_t *cg = self;
258 arm_register_transformers();
259 irg_walk_blkwise_graph(cg->irg, arm_move_consts, arm_transform_node, cg);
265 * Called immediately before emit phase.
267 static void arm_finish_irg(void *self) {
268 /* TODO: - fix offsets for nodes accessing stack
275 * These are some hooks which must be filled but are probably not needed.
277 static void arm_before_sched(void *self) {
278 /* Some stuff you need to do after scheduling but before register allocation */
281 static void arm_before_ra(void *self) {
282 /* Some stuff you need to do immediately after register allocation */
287 * Emits the code, closes the output file and frees
288 * the code generator interface.
290 static void arm_emit_and_done(void *self) {
291 arm_code_gen_t *cg = self;
292 ir_graph *irg = cg->irg;
293 FILE *out = cg->isa->out;
295 if (cg->emit_decls) {
300 dump_ir_block_graph_sched(irg, "-arm-finished");
301 arm_gen_routine(out, irg, cg);
305 /* de-allocate code generator */
306 del_set(cg->reg_set);
311 * Move a double floating point value into an integer register.
312 * Place the move operation into block bl.
314 * Handle some special cases here:
315 * 1.) A constant: simply split into two
316 * 2.) A load: siply split into two
318 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
319 ir_node **resH, ir_node **resL) {
321 tarval *tv = get_Const_tarval(arg);
324 /* get the upper 32 bits */
325 v = get_tarval_sub_bits(tv, 7);
326 v = (v << 8) | get_tarval_sub_bits(tv, 6);
327 v = (v << 8) | get_tarval_sub_bits(tv, 5);
328 v = (v << 8) | get_tarval_sub_bits(tv, 4);
329 *resH = new_Const_long(mode_Is, v);
331 /* get the lower 32 bits */
332 v = get_tarval_sub_bits(tv, 3);
333 v = (v << 8) | get_tarval_sub_bits(tv, 2);
334 v = (v << 8) | get_tarval_sub_bits(tv, 1);
335 v = (v << 8) | get_tarval_sub_bits(tv, 0);
336 *resL = new_Const_long(mode_Is, v);
338 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
339 /* FIXME: handling of low/high depends on LE/BE here */
343 ir_graph *irg = current_ir_graph;
346 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
348 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
349 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
350 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
356 * Move a single floating point value into an integer register.
357 * Place the move operation into block bl.
359 * Handle some special cases here:
360 * 1.) A constant: simply move
361 * 2.) A load: siply load
363 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) {
365 tarval *tv = get_Const_tarval(arg);
368 /* get the lower 32 bits */
369 v = get_tarval_sub_bits(tv, 3);
370 v = (v << 8) | get_tarval_sub_bits(tv, 2);
371 v = (v << 8) | get_tarval_sub_bits(tv, 1);
372 v = (v << 8) | get_tarval_sub_bits(tv, 0);
373 return new_Const_long(mode_Is, v);
375 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
378 load = skip_Proj(arg);
385 * Convert the arguments of a call to support the
386 * ARM calling convention of general purpose AND floating
389 static void handle_calls(ir_node *call, void *env)
391 arm_code_gen_t *cg = env;
392 int i, j, n, size, idx, flag, n_param, n_res;
393 ir_type *mtp, *new_mtd, *new_tp[5];
394 ir_node *new_in[5], **in;
400 /* check, if we need conversions */
401 n = get_Call_n_params(call);
402 mtp = get_Call_type(call);
403 assert(get_method_n_params(mtp) == n);
405 /* it's always enough to handle the first 4 parameters */
408 flag = size = idx = 0;
409 bl = get_nodes_block(call);
410 for (i = 0; i < n; ++i) {
411 ir_type *param_tp = get_method_param_type(mtp, i);
413 if (is_compound_type(param_tp)) {
414 /* an aggregate parameter: bad case */
418 /* a primitive parameter */
419 ir_mode *mode = get_type_mode(param_tp);
421 if (mode_is_float(mode)) {
422 if (get_mode_size_bits(mode) > 32) {
423 ir_node *mem = get_Call_mem(call);
425 /* Beware: ARM wants the high part first */
427 new_tp[idx] = cg->int_tp;
428 new_tp[idx+1] = cg->int_tp;
429 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
431 set_Call_mem(call, mem);
435 new_tp[idx] = cg->int_tp;
436 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
443 new_tp[idx] = param_tp;
444 new_in[idx] = get_Call_param(call, i);
453 /* if flag is NOT set, no need to translate the method type */
457 /* construct a new method type */
459 n_param = get_method_n_params(mtp) - n + idx;
460 n_res = get_method_n_ress(mtp);
461 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
463 for (i = 0; i < idx; ++i)
464 set_method_param_type(new_mtd, i, new_tp[i]);
465 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
466 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
467 for (i = 0; i < n_res; ++i)
468 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
470 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
471 set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp));
473 if (is_lowered_type(mtp)) {
474 mtp = get_associated_type(mtp);
476 set_lowered_type(mtp, new_mtd);
478 set_Call_type(call, new_mtd);
480 /* calculate new in array of the Call */
481 NEW_ARR_A(ir_node *, in, n_param + 2);
482 for (i = 0; i < idx; ++i)
483 in[2 + i] = new_in[i];
484 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
485 in[2 + j++] = get_Call_param(call, i);
487 in[0] = get_Call_mem(call);
488 in[1] = get_Call_ptr(call);
490 /* finally, change the call inputs */
491 set_irn_in(call, n_param + 2, in);
495 * Handle graph transformations before the abi converter does its work.
497 static void arm_before_abi(void *self) {
498 arm_code_gen_t *cg = self;
500 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
503 static void *arm_cg_init(be_irg_t *birg);
505 static const arch_code_generator_if_t arm_code_gen_if = {
507 arm_before_abi, /* before abi introduce */
510 arm_before_sched, /* before scheduling hook */
511 arm_before_ra, /* before register allocation hook */
512 NULL, /* after register allocation */
518 * Initializes the code generator.
520 static void *arm_cg_init(be_irg_t *birg) {
521 static ir_type *int_tp = NULL;
522 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
526 /* create an integer type with machine size */
527 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
530 cg = xmalloc(sizeof(*cg));
531 cg->impl = &arm_code_gen_if;
533 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
534 cg->arch_env = birg->main_env->arch_env;
540 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
544 if (isa->num_codegens > 1)
549 cur_reg_set = cg->reg_set;
553 /* enter the current code generator */
556 return (arch_code_generator_t *)cg;
561 * Maps all intrinsic calls that the backend support
562 * and map all instructions the backend did not support
565 static void arm_handle_intrinsics(void) {
566 ir_type *tp, *int_tp, *uint_tp;
570 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
572 int_tp = new_type_primitive(ID("int"), mode_Is);
573 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
575 /* ARM has neither a signed div instruction ... */
578 i_instr_record *map_Div = &records[n_records++].i_instr;
580 tp = new_type_method(ID("rt_iDiv"), 2, 1);
581 set_method_param_type(tp, 0, int_tp);
582 set_method_param_type(tp, 1, int_tp);
583 set_method_res_type(tp, 0, int_tp);
585 rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
586 rt_Div.mode = mode_T;
587 rt_Div.mem_proj_nr = pn_Div_M;
588 rt_Div.exc_proj_nr = pn_Div_X_except;
589 rt_Div.exc_mem_proj_nr = pn_Div_M;
590 rt_Div.res_proj_nr = pn_Div_res;
592 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
594 map_Div->kind = INTRINSIC_INSTR;
595 map_Div->op = op_Div;
596 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
597 map_Div->ctx = &rt_Div;
599 /* ... nor a signed div instruction ... */
602 i_instr_record *map_Div = &records[n_records++].i_instr;
604 tp = new_type_method(ID("rt_uDiv"), 2, 1);
605 set_method_param_type(tp, 0, uint_tp);
606 set_method_param_type(tp, 1, uint_tp);
607 set_method_res_type(tp, 0, uint_tp);
609 rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
610 rt_Div.mode = mode_T;
611 rt_Div.mem_proj_nr = pn_Div_M;
612 rt_Div.exc_proj_nr = pn_Div_X_except;
613 rt_Div.exc_mem_proj_nr = pn_Div_M;
614 rt_Div.res_proj_nr = pn_Div_res;
616 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
618 map_Div->kind = INTRINSIC_INSTR;
619 map_Div->op = op_Div;
620 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
621 map_Div->ctx = &rt_Div;
623 /* ... nor a signed mod instruction ... */
626 i_instr_record *map_Mod = &records[n_records++].i_instr;
628 tp = new_type_method(ID("rt_iMod"), 2, 1);
629 set_method_param_type(tp, 0, int_tp);
630 set_method_param_type(tp, 1, int_tp);
631 set_method_res_type(tp, 0, int_tp);
633 rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
634 rt_Mod.mode = mode_T;
635 rt_Mod.mem_proj_nr = pn_Mod_M;
636 rt_Mod.exc_proj_nr = pn_Mod_X_except;
637 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
638 rt_Mod.res_proj_nr = pn_Mod_res;
640 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
642 map_Mod->kind = INTRINSIC_INSTR;
643 map_Mod->op = op_Mod;
644 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
645 map_Mod->ctx = &rt_Mod;
647 /* ... nor a unsigned mod. */
650 i_instr_record *map_Mod = &records[n_records++].i_instr;
652 tp = new_type_method(ID("rt_uMod"), 2, 1);
653 set_method_param_type(tp, 0, uint_tp);
654 set_method_param_type(tp, 1, uint_tp);
655 set_method_res_type(tp, 0, uint_tp);
657 rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
658 rt_Mod.mode = mode_T;
659 rt_Mod.mem_proj_nr = pn_Mod_M;
660 rt_Mod.exc_proj_nr = pn_Mod_X_except;
661 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
662 rt_Mod.res_proj_nr = pn_Mod_res;
664 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
666 map_Mod->kind = INTRINSIC_INSTR;
667 map_Mod->op = op_Mod;
668 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
669 map_Mod->ctx = &rt_Mod;
673 lower_intrinsics(records, n_records);
676 /*****************************************************************
677 * ____ _ _ _____ _____
678 * | _ \ | | | | |_ _|/ ____| /\
679 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
680 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
681 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
682 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
684 *****************************************************************/
686 static arm_isa_t arm_isa_template = {
687 &arm_isa_if, /* isa interface */
688 &arm_gp_regs[REG_SP], /* stack pointer */
689 &arm_gp_regs[REG_R11], /* base pointer */
690 -1, /* stack direction */
691 0, /* number of codegenerator objects */
692 0, /* use generic register names instead of SP, LR, PC */
693 NULL, /* current code generator */
694 NULL, /* output file */
695 ARM_FPU_ARCH_FPE, /* FPU architecture */
699 * Initializes the backend ISA and opens the output file.
701 static void *arm_init(FILE *file_handle) {
702 static int inited = 0;
708 isa = xmalloc(sizeof(*isa));
709 memcpy(isa, &arm_isa_template, sizeof(*isa));
711 arm_register_init(isa);
714 isa->out = file_handle;
716 arm_create_opcodes();
717 arm_handle_intrinsics();
718 arm_switch_section(NULL, NO_SECTION);
727 * frees the ISA structure.
729 static void arm_done(void *self) {
735 * Report the number of register classes.
736 * If we don't have fp instructions, report only GP
737 * here to speed up register allocation (and makes dumps
738 * smaller and more readable).
740 static int arm_get_n_reg_class(const void *self) {
741 const arm_isa_t *isa = self;
743 return isa->cg->have_fp ? 2 : 1;
747 * Return the register class with requested index.
749 static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
750 return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa];
754 * Get the register class which shall be used to store a value of a given mode.
755 * @param self The this pointer.
756 * @param mode The mode in question.
757 * @return A register class which can hold values of the given mode.
759 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
760 if (mode_is_float(mode))
761 return &arm_reg_classes[CLASS_arm_fpa];
763 return &arm_reg_classes[CLASS_arm_gp];
767 * Produces the type which sits between the stack args and the locals on the stack.
768 * it will contain the return address and space to store the old base pointer.
769 * @return The Firm type modelling the ABI between type.
771 static ir_type *arm_get_between_type(void *self) {
772 static ir_type *between_type = NULL;
773 static ir_entity *old_bp_ent = NULL;
776 ir_entity *ret_addr_ent;
777 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
778 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
780 between_type = new_type_class(new_id_from_str("arm_between_type"));
781 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
782 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
784 set_entity_offset(old_bp_ent, 0);
785 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
786 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
794 be_abi_call_flags_bits_t flags;
795 const arch_env_t *arch_env;
796 const arch_isa_t *isa;
800 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
802 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
803 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
804 env->flags = fl.bits;
806 env->arch_env = arch_env;
807 env->isa = arch_env->isa;
811 static void arm_abi_dont_save_regs(void *self, pset *s)
813 arm_abi_env_t *env = self;
814 if (env->flags.try_omit_fp)
815 pset_insert_ptr(s, env->isa->bp);
821 * Build the ARM prolog
823 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
824 ir_node *keep, *store;
825 arm_abi_env_t *env = self;
826 ir_graph *irg = env->irg;
827 ir_node *block = get_irg_start_block(irg);
828 // ir_node *regs[16];
830 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
832 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
833 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
834 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
835 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
836 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
837 // ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]);
838 // ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]);
839 // ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]);
840 // ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]);
842 if(env->flags.try_omit_fp)
845 ip = be_new_Copy(gp, irg, block, sp );
846 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
847 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
849 // if (r0) regs[n_regs++] = r0;
850 // if (r1) regs[n_regs++] = r1;
851 // if (r2) regs[n_regs++] = r2;
852 // if (r3) regs[n_regs++] = r3;
853 // sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
854 // set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
855 // arch_set_irn_register(env->arch_env, sp, env->isa->sp);
856 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
858 // set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
859 // arch_set_irn_register(env->arch_env, store, env->isa->sp);
861 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
862 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
863 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
865 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
866 be_node_set_reg_class(keep, 1, gp);
867 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
868 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
870 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
871 new_tarval_from_long(4, get_irn_mode(fp)));
873 //set_arm_req_out_all(fp, fp_req);
874 //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
875 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
877 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
878 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
879 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2);
880 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3);
881 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
882 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
883 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
884 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
885 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
890 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
891 arm_abi_env_t *env = self;
892 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
893 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
894 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
895 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
897 // TODO: Activate Omit fp in epilogue
898 if(env->flags.try_omit_fp) {
899 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
900 add_irn_dep(curr_sp, *mem);
902 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
903 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
904 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
905 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
907 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
908 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
909 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
913 tarval *tv = new_tarval_from_long(12,mode_Iu);
914 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
916 //set_arm_req_out_all(sub12_node, sub12_req);
917 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
918 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
920 //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
921 //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
922 //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
923 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
924 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
925 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
926 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
927 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
928 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
929 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
931 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
932 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
933 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
934 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
937 static const be_abi_callbacks_t arm_abi_callbacks = {
940 arm_get_between_type,
941 arm_abi_dont_save_regs,
948 * Get the ABI restrictions for procedure calls.
949 * @param self The this pointer.
950 * @param method_type The type of the method (procedure) in question.
951 * @param abi The abi object to be modified
953 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
957 int n = get_method_n_params(method_type);
958 be_abi_call_flags_t flags = {
960 0, /* store from left to right */
961 0, /* store arguments sequential */
962 1, /* try to omit the frame pointer */
963 1, /* the function can use any register as frame pointer */
964 1 /* a call can take the callee's address as an immediate */
968 /* set stack parameter passing style */
969 be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
971 for (i = 0; i < n; i++) {
972 /* reg = get reg for param i; */
973 /* be_abi_call_param_reg(abi, i, reg); */
976 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
978 be_abi_call_param_stack(abi, i, 4, 0, 0);
981 /* default: return value is in R0 resp. F0 */
982 assert(get_method_n_ress(method_type) < 2);
983 if (get_method_n_ress(method_type) > 0) {
984 tp = get_method_res_type(method_type, 0);
985 mode = get_type_mode(tp);
987 be_abi_call_res_reg(abi, 0,
988 mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]);
992 static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
996 const arch_irn_handler_t arm_irn_handler = {
1000 const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
1001 return &arm_irn_handler;
1004 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1005 return is_arm_irn(irn);
1009 * Initializes the code generator interface.
1011 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1012 return &arm_code_gen_if;
1015 list_sched_selector_t arm_sched_selector;
1018 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1020 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1021 memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1022 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1023 return &arm_sched_selector;
1026 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
1031 * Returns the necessary byte alignment for storing a register of given class.
1033 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1034 ir_mode *mode = arch_register_class_mode(cls);
1035 return get_mode_size_bytes(mode);
1038 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1044 static const be_machine_t *arm_get_machine(const void *self) {
1051 * Return irp irgs in the desired order.
1053 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
1058 * Returns the libFirm configuration parameter for this backend.
1060 static const backend_params *arm_get_libfirm_params(void) {
1061 static arch_dep_params_t ad = {
1063 0, /* Muls are fast enough on ARM */
1064 31, /* shift would be ok */
1065 0, /* SMUL is needed, only in Arch M*/
1066 0, /* UMUL is needed, only in Arch M */
1067 32, /* SMUL & UMUL available for 32 bit */
1069 static backend_params p = {
1070 NULL, /* no additional opcodes */
1071 NULL, /* will be set later */
1072 1, /* need dword lowering */
1073 NULL, /* but yet no creator function */
1074 NULL, /* context for create_intrinsic_fkt */
1081 /* fpu set architectures. */
1082 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1083 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1084 { "fpe", ARM_FPU_ARCH_FPE },
1085 { "fpa", ARM_FPU_ARCH_FPA },
1086 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1087 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1088 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1092 static lc_opt_enum_int_var_t arch_fpu_var = {
1093 &arm_isa_template.fpu_arch, arm_fpu_items
1096 static const lc_opt_table_entry_t arm_options[] = {
1097 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1098 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1102 const arch_isa_if_t arm_isa_if = {
1105 arm_get_n_reg_class,
1107 arm_get_reg_class_for_mode,
1109 arm_get_irn_handler,
1110 arm_get_code_generator_if,
1111 arm_get_list_sched_selector,
1112 arm_get_ilp_sched_selector,
1113 arm_get_reg_class_alignment,
1114 arm_get_libfirm_params,
1115 arm_get_allowed_execution_units,
1120 void be_init_arch_arm(void)
1122 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1123 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1125 lc_opt_add_table(arm_grp, arm_options);
1127 be_register_isa_if("arm", &arm_isa_if);
1130 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);