1 /* The main arm backend driver file. */
9 #include <libcore/lc_opts.h>
10 #include <libcore/lc_opts_enum.h>
11 #endif /* WITH_LIBCORE */
13 #include "pseudo_irg.h"
19 #include "lower_intrinsics.h"
24 #include "../bearch.h" /* the general register allocator interface */
25 #include "../benode_t.h"
26 #include "../belower.h"
27 #include "../besched_t.h"
30 #include "../bemachine.h"
32 #include "bearch_arm_t.h"
34 #include "arm_new_nodes.h" /* arm nodes interface */
35 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
36 #include "arm_gen_decls.h" /* interface declaration emitter */
37 #include "arm_transform.h"
38 #include "arm_emitter.h"
39 #include "arm_map_regs.h"
41 #define DEBUG_MODULE "firm.be.arm.isa"
43 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
44 static set *cur_reg_set = NULL;
46 /**************************************************
49 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
50 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
51 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
52 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
55 **************************************************/
57 static ir_node *my_skip_proj(const ir_node *n) {
64 * Return register requirements for a arm node.
65 * If the node returns a tuple (mode_T) then the proj's
66 * will be asked for this information.
68 static const arch_register_req_t *arm_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
69 const arm_register_req_t *irn_req;
70 long node_pos = pos == -1 ? 0 : pos;
71 ir_mode *mode = get_irn_mode(irn);
72 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
74 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
75 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
79 if (mode == mode_T && pos < 0) {
80 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
84 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
87 /* in case of a proj, we need to get the correct OUT slot */
88 /* of the node corresponding to the proj number */
90 node_pos = arm_translate_proj_pos(irn);
96 irn = my_skip_proj(irn);
98 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
101 /* get requirements for our own nodes */
102 if (is_arm_irn(irn)) {
104 irn_req = get_arm_in_req(irn, pos);
107 irn_req = get_arm_out_req(irn, node_pos);
110 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
112 memcpy(req, &(irn_req->req), sizeof(*req));
114 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
115 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
116 req->other_same = get_irn_n(irn, irn_req->same_pos);
119 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
120 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
121 req->other_different = get_irn_n(irn, irn_req->different_pos);
124 /* get requirements for FIRM nodes */
126 /* treat Phi like Const with default requirements */
128 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
130 if (mode_is_float(mode)) {
131 memcpy(req, &(arm_default_req_arm_fpa.req), sizeof(*req));
133 else if (mode_is_int(mode) || mode_is_reference(mode)) {
134 memcpy(req, &(arm_default_req_arm_gp.req), sizeof(*req));
136 else if (mode == mode_T || mode == mode_M) {
137 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
141 assert(0 && "unsupported Phi-Mode");
145 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
153 static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
158 if (get_irn_mode(irn) == mode_X) {
162 pos = arm_translate_proj_pos(irn);
163 irn = my_skip_proj(irn);
166 if (is_arm_irn(irn)) {
167 const arch_register_t **slots;
169 slots = get_arm_slots(irn);
173 /* here we set the registers for the Phi nodes */
174 arm_set_firm_reg(irn, reg, cur_reg_set);
178 static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) {
180 const arch_register_t *reg = NULL;
184 if (get_irn_mode(irn) == mode_X) {
188 pos = arm_translate_proj_pos(irn);
189 irn = my_skip_proj(irn);
192 if (is_arm_irn(irn)) {
193 const arch_register_t **slots;
194 slots = get_arm_slots(irn);
198 reg = arm_get_firm_reg(irn, cur_reg_set);
204 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
205 irn = my_skip_proj(irn);
208 return arch_irn_class_branch;
210 else if (is_arm_irn(irn)) {
211 return arch_irn_class_normal;
217 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
218 irn = my_skip_proj(irn);
220 if (is_arm_irn(irn)) {
221 return get_arm_flags(irn);
223 else if (is_Unknown(irn)) {
224 return arch_irn_flags_ignore;
230 static entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
231 /* TODO: return the entity assigned to the frame */
235 static void arm_set_frame_entity(const void *self, ir_node *irn, entity *ent) {
236 /* TODO: set the entity assigned to the frame */
240 * This function is called by the generic backend to correct offsets for
241 * nodes accessing the stack.
243 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
244 /* TODO: correct offset if irn accesses the stack */
247 static int arm_get_sp_bias(const void *self, const ir_node *irn) {
251 /* fill register allocator interface */
253 static const arch_irn_ops_if_t arm_irn_ops_if = {
259 arm_get_frame_entity,
260 arm_set_frame_entity,
263 NULL, /* get_inverse */
264 NULL, /* get_op_estimated_cost */
265 NULL, /* possible_memory_operand */
266 NULL, /* perform_memory_operand */
269 arm_irn_ops_t arm_irn_ops = {
276 /**************************************************
279 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
280 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
281 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
282 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
285 **************************************************/
288 * Transforms the standard Firm graph into
291 static void arm_prepare_graph(void *self) {
292 arm_code_gen_t *cg = self;
294 arm_register_transformers();
295 irg_walk_blkwise_graph(cg->irg, arm_move_consts, arm_transform_node, cg);
301 * Called immediately before emit phase.
303 static void arm_finish_irg(void *self) {
304 /* TODO: - fix offsets for nodes accessing stack
311 * These are some hooks which must be filled but are probably not needed.
313 static void arm_before_sched(void *self) {
314 /* Some stuff you need to do after scheduling but before register allocation */
317 static void arm_before_ra(void *self) {
318 /* Some stuff you need to do immediately after register allocation */
323 * Emits the code, closes the output file and frees
324 * the code generator interface.
326 static void arm_emit_and_done(void *self) {
327 arm_code_gen_t *cg = self;
328 ir_graph *irg = cg->irg;
329 FILE *out = cg->isa->out;
331 if (cg->emit_decls) {
336 dump_ir_block_graph_sched(irg, "-arm-finished");
337 arm_gen_routine(out, irg, cg);
341 /* de-allocate code generator */
342 del_set(cg->reg_set);
347 * Move a double floating point value into an integer register.
348 * Place the move operation into block bl.
350 * Handle some special cases here:
351 * 1.) A constant: simply split into two
352 * 2.) A load: siply split into two
354 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
355 ir_node **resH, ir_node **resL) {
357 tarval *tv = get_Const_tarval(arg);
360 /* get the upper 32 bits */
361 v = get_tarval_sub_bits(tv, 7);
362 v = (v << 8) | get_tarval_sub_bits(tv, 6);
363 v = (v << 8) | get_tarval_sub_bits(tv, 5);
364 v = (v << 8) | get_tarval_sub_bits(tv, 4);
365 *resH = new_Const_long(mode_Is, v);
367 /* get the lower 32 bits */
368 v = get_tarval_sub_bits(tv, 3);
369 v = (v << 8) | get_tarval_sub_bits(tv, 2);
370 v = (v << 8) | get_tarval_sub_bits(tv, 1);
371 v = (v << 8) | get_tarval_sub_bits(tv, 0);
372 *resL = new_Const_long(mode_Is, v);
374 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
375 /* FIXME: handling of low/high depends on LE/BE here */
379 ir_graph *irg = current_ir_graph;
382 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
384 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
385 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
386 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
392 * Move a single floating point value into an integer register.
393 * Place the move operation into block bl.
395 * Handle some special cases here:
396 * 1.) A constant: simply move
397 * 2.) A load: siply load
399 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) {
401 tarval *tv = get_Const_tarval(arg);
404 /* get the lower 32 bits */
405 v = get_tarval_sub_bits(tv, 3);
406 v = (v << 8) | get_tarval_sub_bits(tv, 2);
407 v = (v << 8) | get_tarval_sub_bits(tv, 1);
408 v = (v << 8) | get_tarval_sub_bits(tv, 0);
409 return new_Const_long(mode_Is, v);
411 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
414 load = skip_Proj(arg);
421 * Convert the arguments of a call to support the
422 * ARM calling convention of general purpose AND floating
425 static void handle_calls(ir_node *call, void *env)
427 arm_code_gen_t *cg = env;
428 int i, j, n, size, idx, flag, n_param, n_res;
429 ir_type *mtp, *new_mtd, *new_tp[5];
430 ir_node *new_in[5], **in;
436 /* check, if we need conversions */
437 n = get_Call_n_params(call);
438 mtp = get_Call_type(call);
439 assert(get_method_n_params(mtp) == n);
441 /* it's always enough to handle the first 4 parameters */
444 flag = size = idx = 0;
445 bl = get_nodes_block(call);
446 for (i = 0; i < n; ++i) {
447 ir_type *param_tp = get_method_param_type(mtp, i);
449 if (is_compound_type(param_tp)) {
450 /* an aggregate parameter: bad case */
454 /* a primitive parameter */
455 ir_mode *mode = get_type_mode(param_tp);
457 if (mode_is_float(mode)) {
458 if (get_mode_size_bits(mode) > 32) {
459 ir_node *mem = get_Call_mem(call);
461 /* Beware: ARM wants the high part first */
463 new_tp[idx] = cg->int_tp;
464 new_tp[idx+1] = cg->int_tp;
465 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
467 set_Call_mem(call, mem);
471 new_tp[idx] = cg->int_tp;
472 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
479 new_tp[idx] = param_tp;
480 new_in[idx] = get_Call_param(call, i);
489 /* if flag is NOT set, no need to translate the method type */
493 /* construct a new method type */
495 n_param = get_method_n_params(mtp) - n + idx;
496 n_res = get_method_n_ress(mtp);
497 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
499 for (i = 0; i < idx; ++i)
500 set_method_param_type(new_mtd, i, new_tp[i]);
501 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
502 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
503 for (i = 0; i < n_res; ++i)
504 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
506 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
507 set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp));
509 if (is_lowered_type(mtp)) {
510 mtp = get_associated_type(mtp);
512 set_lowered_type(mtp, new_mtd);
514 set_Call_type(call, new_mtd);
516 /* calculate new in array of the Call */
517 NEW_ARR_A(ir_node *, in, n_param + 2);
518 for (i = 0; i < idx; ++i)
519 in[2 + i] = new_in[i];
520 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
521 in[2 + j++] = get_Call_param(call, i);
523 in[0] = get_Call_mem(call);
524 in[1] = get_Call_ptr(call);
526 /* finally, change the call inputs */
527 set_irn_in(call, n_param + 2, in);
531 * Handle graph transformations before the abi converter does its work.
533 static void arm_before_abi(void *self) {
534 arm_code_gen_t *cg = self;
536 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
539 static void *arm_cg_init(const be_irg_t *birg);
541 static const arch_code_generator_if_t arm_code_gen_if = {
543 arm_before_abi, /* before abi introduce */
545 arm_before_sched, /* before scheduling hook */
546 arm_before_ra, /* before register allocation hook */
547 NULL, /* after register allocation */
553 * Initializes the code generator.
555 static void *arm_cg_init(const be_irg_t *birg) {
556 static ir_type *int_tp = NULL;
557 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
561 /* create an integer type with machine size */
562 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
565 cg = xmalloc(sizeof(*cg));
566 cg->impl = &arm_code_gen_if;
568 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
569 cg->arch_env = birg->main_env->arch_env;
575 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
579 if (isa->num_codegens > 1)
584 cur_reg_set = cg->reg_set;
588 /* enter the current code generator */
591 return (arch_code_generator_t *)cg;
596 * Maps all intrinsic calls that the backend support
597 * and map all instructions the backend did not support
600 static void arm_handle_intrinsics(void) {
601 ir_type *tp, *int_tp, *uint_tp;
605 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
607 int_tp = new_type_primitive(ID("int"), mode_Is);
608 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
610 /* ARM has neither a signed div instruction ... */
613 i_instr_record *map_Div = &records[n_records++].i_instr;
615 tp = new_type_method(ID("rt_iDiv"), 2, 1);
616 set_method_param_type(tp, 0, int_tp);
617 set_method_param_type(tp, 1, int_tp);
618 set_method_res_type(tp, 0, int_tp);
620 rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
621 rt_Div.mode = mode_T;
622 rt_Div.mem_proj_nr = pn_Div_M;
623 rt_Div.exc_proj_nr = pn_Div_X_except;
624 rt_Div.exc_mem_proj_nr = pn_Div_M;
625 rt_Div.res_proj_nr = pn_Div_res;
627 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
629 map_Div->kind = INTRINSIC_INSTR;
630 map_Div->op = op_Div;
631 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
632 map_Div->ctx = &rt_Div;
634 /* ... nor a signed div instruction ... */
637 i_instr_record *map_Div = &records[n_records++].i_instr;
639 tp = new_type_method(ID("rt_uDiv"), 2, 1);
640 set_method_param_type(tp, 0, uint_tp);
641 set_method_param_type(tp, 1, uint_tp);
642 set_method_res_type(tp, 0, uint_tp);
644 rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
645 rt_Div.mode = mode_T;
646 rt_Div.mem_proj_nr = pn_Div_M;
647 rt_Div.exc_proj_nr = pn_Div_X_except;
648 rt_Div.exc_mem_proj_nr = pn_Div_M;
649 rt_Div.res_proj_nr = pn_Div_res;
651 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
653 map_Div->kind = INTRINSIC_INSTR;
654 map_Div->op = op_Div;
655 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
656 map_Div->ctx = &rt_Div;
658 /* ... nor a signed mod instruction ... */
661 i_instr_record *map_Mod = &records[n_records++].i_instr;
663 tp = new_type_method(ID("rt_iMod"), 2, 1);
664 set_method_param_type(tp, 0, int_tp);
665 set_method_param_type(tp, 1, int_tp);
666 set_method_res_type(tp, 0, int_tp);
668 rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
669 rt_Mod.mode = mode_T;
670 rt_Mod.mem_proj_nr = pn_Mod_M;
671 rt_Mod.exc_proj_nr = pn_Mod_X_except;
672 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
673 rt_Mod.res_proj_nr = pn_Mod_res;
675 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
677 map_Mod->kind = INTRINSIC_INSTR;
678 map_Mod->op = op_Mod;
679 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
680 map_Mod->ctx = &rt_Mod;
682 /* ... nor a unsigned mod. */
685 i_instr_record *map_Mod = &records[n_records++].i_instr;
687 tp = new_type_method(ID("rt_uMod"), 2, 1);
688 set_method_param_type(tp, 0, uint_tp);
689 set_method_param_type(tp, 1, uint_tp);
690 set_method_res_type(tp, 0, uint_tp);
692 rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
693 rt_Mod.mode = mode_T;
694 rt_Mod.mem_proj_nr = pn_Mod_M;
695 rt_Mod.exc_proj_nr = pn_Mod_X_except;
696 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
697 rt_Mod.res_proj_nr = pn_Mod_res;
699 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
701 map_Mod->kind = INTRINSIC_INSTR;
702 map_Mod->op = op_Mod;
703 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
704 map_Mod->ctx = &rt_Mod;
708 lower_intrinsics(records, n_records);
711 /*****************************************************************
712 * ____ _ _ _____ _____
713 * | _ \ | | | | |_ _|/ ____| /\
714 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
715 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
716 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
717 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
719 *****************************************************************/
721 static arm_isa_t arm_isa_template = {
722 &arm_isa_if, /* isa interface */
723 &arm_gp_regs[REG_SP], /* stack pointer */
724 &arm_gp_regs[REG_R11], /* base pointer */
725 -1, /* stack direction */
726 0, /* number of codegenerator objects */
727 0, /* use generic register names instead of SP, LR, PC */
728 NULL, /* current code generator */
729 NULL, /* output file */
730 ARM_FPU_ARCH_FPE, /* FPU architecture */
734 * Initializes the backend ISA and opens the output file.
736 static void *arm_init(FILE *file_handle) {
737 static int inited = 0;
743 isa = xmalloc(sizeof(*isa));
744 memcpy(isa, &arm_isa_template, sizeof(*isa));
746 arm_register_init(isa);
747 if (isa->gen_reg_names) {
748 /* patch register names */
749 arm_gp_regs[REG_R11].name = "r11";
750 arm_gp_regs[REG_SP].name = "r13";
751 arm_gp_regs[REG_LR].name = "r14";
752 arm_gp_regs[REG_PC].name = "r15";
756 isa->out = file_handle;
758 arm_create_opcodes();
759 arm_handle_intrinsics();
760 arm_switch_section(NULL, NO_SECTION);
769 * frees the ISA structure.
771 static void arm_done(void *self) {
777 * Report the number of register classes.
778 * If we don't have fp instructions, report only GP
779 * here to speed up register allocation (and makes dumps
780 * smaller and more readable).
782 static int arm_get_n_reg_class(const void *self) {
783 const arm_isa_t *isa = self;
785 return isa->cg->have_fp ? 2 : 1;
789 * Return the register class with requested index.
791 static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
792 return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa];
796 * Get the register class which shall be used to store a value of a given mode.
797 * @param self The this pointer.
798 * @param mode The mode in question.
799 * @return A register class which can hold values of the given mode.
801 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
802 if (mode_is_float(mode))
803 return &arm_reg_classes[CLASS_arm_fpa];
805 return &arm_reg_classes[CLASS_arm_gp];
809 * Produces the type which sits between the stack args and the locals on the stack.
810 * it will contain the return address and space to store the old base pointer.
811 * @return The Firm type modelling the ABI between type.
813 static ir_type *arm_get_between_type(void *self) {
814 static ir_type *between_type = NULL;
815 static entity *old_bp_ent = NULL;
818 entity *ret_addr_ent;
819 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
820 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
822 between_type = new_type_class(new_id_from_str("arm_between_type"));
823 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
824 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
826 set_entity_offset_bytes(old_bp_ent, 0);
827 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
828 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
836 be_abi_call_flags_bits_t flags;
837 const arch_env_t *arch_env;
838 const arch_isa_t *isa;
842 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
844 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
845 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
846 env->flags = fl.bits;
848 env->arch_env = arch_env;
849 env->isa = arch_env->isa;
853 static void arm_abi_dont_save_regs(void *self, pset *s)
855 arm_abi_env_t *env = self;
856 if (env->flags.try_omit_fp)
857 pset_insert_ptr(s, env->isa->bp);
863 * Build the ARM prolog
865 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
866 ir_node *keep, *store;
867 arm_abi_env_t *env = self;
868 ir_graph *irg = env->irg;
869 ir_node *block = get_irg_start_block(irg);
870 // ir_node *regs[16];
872 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
873 static const arm_register_req_t *fp_req[] = {
874 &arm_default_req_arm_gp_r11
877 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
878 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
879 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
880 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
881 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
882 // ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]);
883 // ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]);
884 // ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]);
885 // ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]);
887 if(env->flags.try_omit_fp)
890 ip = be_new_Copy(gp, irg, block, sp );
891 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
892 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
894 // if (r0) regs[n_regs++] = r0;
895 // if (r1) regs[n_regs++] = r1;
896 // if (r2) regs[n_regs++] = r2;
897 // if (r3) regs[n_regs++] = r3;
898 // sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
899 // set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
900 // arch_set_irn_register(env->arch_env, sp, env->isa->sp);
901 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
902 set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
903 // arch_set_irn_register(env->arch_env, store, env->isa->sp);
905 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
906 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
907 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
909 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
910 be_node_set_reg_class(keep, 1, gp);
911 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
912 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
914 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
915 new_tarval_from_long(4, get_irn_mode(fp)));
916 set_arm_req_out_all(fp, fp_req);
917 //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
918 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
920 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
921 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
922 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2);
923 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3);
924 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
925 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
926 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
927 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
928 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
933 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
934 arm_abi_env_t *env = self;
935 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
936 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
937 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
938 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
939 static const arm_register_req_t *sub12_req[] = {
940 &arm_default_req_arm_gp_sp
943 // TODO: Activate Omit fp in epilogue
944 if(env->flags.try_omit_fp) {
945 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
946 add_irn_dep(curr_sp, *mem);
948 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
949 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
950 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
951 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
953 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
954 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
955 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
959 tarval *tv = new_tarval_from_long(12,mode_Iu);
960 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
961 set_arm_req_out_all(sub12_node, sub12_req);
962 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
963 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
964 set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
965 set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
966 set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
967 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
968 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
969 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
970 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
971 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
972 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
973 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
975 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
976 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
977 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
978 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
981 static const be_abi_callbacks_t arm_abi_callbacks = {
984 arm_get_between_type,
985 arm_abi_dont_save_regs,
992 * Get the ABI restrictions for procedure calls.
993 * @param self The this pointer.
994 * @param method_type The type of the method (procedure) in question.
995 * @param abi The abi object to be modified
997 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1001 int n = get_method_n_params(method_type);
1002 be_abi_call_flags_t flags = {
1004 0, /* store from left to right */
1005 0, /* store arguments sequential */
1006 1, /* try to omit the frame pointer */
1007 1, /* the function can use any register as frame pointer */
1008 1 /* a call can take the callee's address as an immediate */
1012 /* set stack parameter passing style */
1013 be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
1015 for (i = 0; i < n; i++) {
1016 /* reg = get reg for param i; */
1017 /* be_abi_call_param_reg(abi, i, reg); */
1020 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1022 be_abi_call_param_stack(abi, i, 4, 0, 0);
1025 /* default: return value is in R0 resp. F0 */
1026 assert(get_method_n_ress(method_type) < 2);
1027 if (get_method_n_ress(method_type) > 0) {
1028 tp = get_method_res_type(method_type, 0);
1029 mode = get_type_mode(tp);
1031 be_abi_call_res_reg(abi, 0,
1032 mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]);
1036 static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1037 return &arm_irn_ops;
1040 const arch_irn_handler_t arm_irn_handler = {
1044 const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
1045 return &arm_irn_handler;
1048 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1049 return is_arm_irn(irn);
1053 * Initializes the code generator interface.
1055 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1056 return &arm_code_gen_if;
1059 list_sched_selector_t arm_sched_selector;
1062 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1064 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1065 memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1066 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1067 return &arm_sched_selector;
1071 * Returns the necessary byte alignment for storing a register of given class.
1073 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1074 ir_mode *mode = arch_register_class_mode(cls);
1075 return get_mode_size_bytes(mode);
1078 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1084 static const be_machine_t *arm_get_machine(const void *self) {
1091 * Returns the libFirm configuration parameter for this backend.
1093 static const backend_params *arm_get_libfirm_params(void) {
1094 static arch_dep_params_t ad = {
1096 0, /* Muls are fast enough on ARM */
1097 31, /* shift would be ok */
1098 0, /* SMUL is needed, only in Arch M*/
1099 0, /* UMUL is needed, only in Arch M */
1100 32, /* SMUL & UMUL available for 32 bit */
1102 static backend_params p = {
1103 NULL, /* no additional opcodes */
1104 NULL, /* will be set later */
1105 1, /* need dword lowering */
1106 NULL, /* but yet no creator function */
1107 NULL, /* context for create_intrinsic_fkt */
1116 /* fpu set architectures. */
1117 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1118 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1119 { "fpe", ARM_FPU_ARCH_FPE },
1120 { "fpa", ARM_FPU_ARCH_FPA },
1121 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1122 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1123 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1127 static lc_opt_enum_int_var_t arch_fpu_var = {
1128 &arm_isa_template.fpu_arch, arm_fpu_items
1131 static const lc_opt_table_entry_t arm_options[] = {
1132 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1133 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1138 * Register command line options for the ARM backend.
1142 * arm-fpuunit=unit select the floating point unit
1143 * arm-gen_reg_names use generic register names instead of SP, LR, PC
1145 static void arm_register_options(lc_opt_entry_t *ent)
1147 lc_opt_entry_t *be_grp_arm = lc_opt_get_grp(ent, "arm");
1148 lc_opt_add_table(be_grp_arm, arm_options);
1150 #endif /* WITH_LIBCORE */
1152 const arch_isa_if_t arm_isa_if = {
1155 arm_get_n_reg_class,
1157 arm_get_reg_class_for_mode,
1159 arm_get_irn_handler,
1160 arm_get_code_generator_if,
1161 arm_get_list_sched_selector,
1162 arm_get_reg_class_alignment,
1163 arm_get_libfirm_params,
1164 arm_get_allowed_execution_units,
1167 arm_register_options