2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Oliver Richter, Tobias Gneist
29 #include "lc_opts_enum.h"
31 #include "pseudo_irg.h"
38 #include "iroptimize.h"
47 #include "../bearch_t.h" /* the general register allocator interface */
48 #include "../benode_t.h"
49 #include "../belower.h"
50 #include "../besched_t.h"
53 #include "../bemachine.h"
54 #include "../beilpsched.h"
55 #include "../bemodule.h"
56 #include "../beirg_t.h"
57 #include "../bespillslots.h"
58 #include "../begnuas.h"
60 #include "bearch_arm_t.h"
62 #include "arm_new_nodes.h" /* arm nodes interface */
63 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
64 #include "arm_transform.h"
65 #include "arm_optimize.h"
66 #include "arm_emitter.h"
67 #include "arm_map_regs.h"
69 #define DEBUG_MODULE "firm.be.arm.isa"
71 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
72 static set *cur_reg_set = NULL;
74 /**************************************************
77 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
78 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
79 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
80 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
83 **************************************************/
86 * Return register requirements for a arm node.
87 * If the node returns a tuple (mode_T) then the proj's
88 * will be asked for this information.
90 static const arch_register_req_t *arm_get_irn_reg_req(const ir_node *node,
93 long node_pos = pos == -1 ? 0 : pos;
94 ir_mode *mode = get_irn_mode(node);
96 if (is_Block(node) || mode == mode_X) {
97 return arch_no_register_req;
100 if (mode == mode_T && pos < 0) {
101 return arch_no_register_req;
106 return arch_no_register_req;
109 return arch_no_register_req;
112 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
113 node = skip_Proj_const(node);
116 /* get requirements for our own nodes */
117 if (is_arm_irn(node)) {
118 const arch_register_req_t *req;
120 req = get_arm_in_req(node, pos);
122 req = get_arm_out_req(node, node_pos);
128 /* unknown should be transformed by now */
129 assert(!is_Unknown(node));
130 return arch_no_register_req;
133 static void arm_set_irn_reg(ir_node *irn, const arch_register_t *reg)
137 if (get_irn_mode(irn) == mode_X) {
142 pos = get_Proj_proj(irn);
143 irn = skip_Proj(irn);
146 if (is_arm_irn(irn)) {
147 const arch_register_t **slots;
149 slots = get_arm_slots(irn);
153 /* here we set the registers for the Phi nodes */
154 arm_set_firm_reg(irn, reg, cur_reg_set);
158 static const arch_register_t *arm_get_irn_reg(const ir_node *irn)
161 const arch_register_t *reg = NULL;
165 if (get_irn_mode(irn) == mode_X) {
169 pos = get_Proj_proj(irn);
170 irn = skip_Proj_const(irn);
173 if (is_arm_irn(irn)) {
174 const arch_register_t **slots;
175 slots = get_arm_slots(irn);
179 reg = arm_get_firm_reg(irn, cur_reg_set);
185 static arch_irn_class_t arm_classify(const ir_node *irn)
187 irn = skip_Proj_const(irn);
190 return arch_irn_class_branch;
196 static arch_irn_flags_t arm_get_flags(const ir_node *irn)
198 arch_irn_flags_t flags = arch_irn_flags_none;
200 if(is_Unknown(irn)) {
201 return arch_irn_flags_ignore;
204 if (is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
205 ir_node *pred = get_Proj_pred(irn);
206 if (is_arm_irn(pred)) {
207 flags = get_arm_out_flags(pred, get_Proj_proj(irn));
212 if (is_arm_irn(irn)) {
213 flags |= get_arm_flags(irn);
219 static ir_entity *arm_get_frame_entity(const ir_node *irn) {
220 /* we do NOT transform be_Spill or be_Reload nodes, so we never
221 have frame access using ARM nodes. */
226 static void arm_set_frame_entity(ir_node *irn, ir_entity *ent) {
229 panic("arm_set_frame_entity() called. This should not happen.");
233 * This function is called by the generic backend to correct offsets for
234 * nodes accessing the stack.
236 static void arm_set_stack_bias(ir_node *irn, int bias)
240 /* TODO: correct offset if irn accesses the stack */
243 static int arm_get_sp_bias(const ir_node *irn)
249 /* fill register allocator interface */
251 static const arch_irn_ops_t arm_irn_ops = {
257 arm_get_frame_entity,
258 arm_set_frame_entity,
261 NULL, /* get_inverse */
262 NULL, /* get_op_estimated_cost */
263 NULL, /* possible_memory_operand */
264 NULL, /* perform_memory_operand */
267 /**************************************************
270 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
271 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
272 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
273 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
276 **************************************************/
279 * Transforms the standard Firm graph into
282 static void arm_prepare_graph(void *self) {
283 arm_code_gen_t *cg = self;
285 /* transform nodes into assembler instructions */
286 arm_transform_graph(cg);
288 /* do local optimizations (mainly CSE) */
289 local_optimize_graph(cg->irg);
292 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
294 /* do code placement, to optimize the position of constants */
298 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
302 * Called immediately before emit phase.
304 static void arm_finish_irg(void *self)
306 arm_code_gen_t *cg = self;
308 /* do peephole optimizations and fix stack offsets */
309 arm_peephole_optimization(cg);
313 static void arm_before_ra(void *self)
316 /* Some stuff you need to do immediately after register allocation */
320 * We transform Spill and Reload here. This needs to be done before
321 * stack biasing otherwise we would miss the corrected offset for these nodes.
323 static void arm_after_ra(void *self)
325 arm_code_gen_t *cg = self;
326 be_coalesce_spillslots(cg->birg);
330 * Emits the code, closes the output file and frees
331 * the code generator interface.
333 static void arm_emit_and_done(void *self) {
334 arm_code_gen_t *cg = self;
335 ir_graph *irg = cg->irg;
337 arm_gen_routine(cg, irg);
341 /* de-allocate code generator */
342 del_set(cg->reg_set);
347 * Move a double floating point value into an integer register.
348 * Place the move operation into block bl.
350 * Handle some special cases here:
351 * 1.) A constant: simply split into two
352 * 2.) A load: simply split into two
354 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
355 ir_node **resH, ir_node **resL) {
357 tarval *tv = get_Const_tarval(arg);
360 /* get the upper 32 bits */
361 v = get_tarval_sub_bits(tv, 7);
362 v = (v << 8) | get_tarval_sub_bits(tv, 6);
363 v = (v << 8) | get_tarval_sub_bits(tv, 5);
364 v = (v << 8) | get_tarval_sub_bits(tv, 4);
365 *resH = new_Const_long(mode_Is, v);
367 /* get the lower 32 bits */
368 v = get_tarval_sub_bits(tv, 3);
369 v = (v << 8) | get_tarval_sub_bits(tv, 2);
370 v = (v << 8) | get_tarval_sub_bits(tv, 1);
371 v = (v << 8) | get_tarval_sub_bits(tv, 0);
372 *resL = new_Const_long(mode_Is, v);
373 } else if (is_Load(skip_Proj(arg))) {
374 /* FIXME: handling of low/high depends on LE/BE here */
375 panic("Unimplemented convert_dbl_to_int() case");
378 ir_graph *irg = current_ir_graph;
381 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
383 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
384 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
385 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
391 * Move a single floating point value into an integer register.
392 * Place the move operation into block bl.
394 * Handle some special cases here:
395 * 1.) A constant: simply move
396 * 2.) A load: simply load
398 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg)
403 tarval *tv = get_Const_tarval(arg);
406 /* get the lower 32 bits */
407 v = get_tarval_sub_bits(tv, 3);
408 v = (v << 8) | get_tarval_sub_bits(tv, 2);
409 v = (v << 8) | get_tarval_sub_bits(tv, 1);
410 v = (v << 8) | get_tarval_sub_bits(tv, 0);
411 return new_Const_long(mode_Is, v);
412 } else if (is_Load(skip_Proj(arg))) {
415 load = skip_Proj(arg);
417 panic("Unimplemented convert_sng_to_int() case");
421 * Convert the arguments of a call to support the
422 * ARM calling convention of general purpose AND floating
425 static void handle_calls(ir_node *call, void *env)
427 arm_code_gen_t *cg = env;
428 int i, j, n, size, idx, flag, n_param, n_res, first_variadic;
429 ir_type *mtp, *new_mtd, *new_tp[5];
430 ir_node *new_in[5], **in;
436 /* check, if we need conversions */
437 n = get_Call_n_params(call);
438 mtp = get_Call_type(call);
439 assert(get_method_n_params(mtp) == n);
441 /* it's always enough to handle the first 4 parameters */
444 flag = size = idx = 0;
445 bl = get_nodes_block(call);
446 for (i = 0; i < n; ++i) {
447 ir_type *param_tp = get_method_param_type(mtp, i);
449 if (is_compound_type(param_tp)) {
450 /* an aggregate parameter: bad case */
454 /* a primitive parameter */
455 ir_mode *mode = get_type_mode(param_tp);
457 if (mode_is_float(mode)) {
458 if (get_mode_size_bits(mode) > 32) {
459 ir_node *mem = get_Call_mem(call);
461 /* Beware: ARM wants the high part first */
463 new_tp[idx] = cg->int_tp;
464 new_tp[idx+1] = cg->int_tp;
465 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
467 set_Call_mem(call, mem);
471 new_tp[idx] = cg->int_tp;
472 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
479 new_tp[idx] = param_tp;
480 new_in[idx] = get_Call_param(call, i);
489 /* if flag is NOT set, no need to translate the method type */
493 /* construct a new method type */
495 n_param = get_method_n_params(mtp) - n + idx;
496 n_res = get_method_n_ress(mtp);
497 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
499 for (i = 0; i < idx; ++i)
500 set_method_param_type(new_mtd, i, new_tp[i]);
501 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
502 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
503 for (i = 0; i < n_res; ++i)
504 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
506 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
507 first_variadic = get_method_first_variadic_param_index(mtp);
508 if (first_variadic >= 0)
509 set_method_first_variadic_param_index(new_mtd, first_variadic);
511 if (is_lowered_type(mtp)) {
512 mtp = get_associated_type(mtp);
514 set_lowered_type(mtp, new_mtd);
516 set_Call_type(call, new_mtd);
518 /* calculate new in array of the Call */
519 NEW_ARR_A(ir_node *, in, n_param + 2);
520 for (i = 0; i < idx; ++i)
521 in[2 + i] = new_in[i];
522 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
523 in[2 + j++] = get_Call_param(call, i);
525 in[0] = get_Call_mem(call);
526 in[1] = get_Call_ptr(call);
528 /* finally, change the call inputs */
529 set_irn_in(call, n_param + 2, in);
533 * Handle graph transformations before the abi converter does its work.
535 static void arm_before_abi(void *self) {
536 arm_code_gen_t *cg = self;
538 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
542 static void *arm_cg_init(be_irg_t *birg);
544 static const arch_code_generator_if_t arm_code_gen_if = {
546 NULL, /* get_pic_base */
547 arm_before_abi, /* before abi introduce */
550 arm_before_ra, /* before register allocation hook */
557 * Initializes the code generator.
559 static void *arm_cg_init(be_irg_t *birg) {
560 static ir_type *int_tp = NULL;
561 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env;
565 /* create an integer type with machine size */
566 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
569 cg = XMALLOC(arm_code_gen_t);
570 cg->impl = &arm_code_gen_if;
572 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
576 cg->have_fp_insn = 0;
577 cg->unknown_gp = NULL;
578 cg->unknown_fpa = NULL;
579 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
581 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
583 cur_reg_set = cg->reg_set;
585 /* enter the current code generator */
588 return (arch_code_generator_t *)cg;
593 * Maps all intrinsic calls that the backend support
594 * and map all instructions the backend did not support
597 static void arm_handle_intrinsics(void) {
598 ir_type *tp, *int_tp, *uint_tp;
602 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
604 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
606 int_tp = new_type_primitive(ID("int"), mode_Is);
607 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
609 /* ARM has neither a signed div instruction ... */
611 i_instr_record *map_Div = &records[n_records++].i_instr;
613 tp = new_type_method(ID("rt_iDiv"), 2, 1);
614 set_method_param_type(tp, 0, int_tp);
615 set_method_param_type(tp, 1, int_tp);
616 set_method_res_type(tp, 0, int_tp);
618 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
619 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
620 rt_iDiv.mode = mode_T;
621 rt_iDiv.res_mode = mode_Is;
622 rt_iDiv.mem_proj_nr = pn_Div_M;
623 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
624 rt_iDiv.exc_proj_nr = pn_Div_X_except;
625 rt_iDiv.exc_mem_proj_nr = pn_Div_M;
626 rt_iDiv.res_proj_nr = pn_Div_res;
628 set_entity_visibility(rt_iDiv.ent, visibility_external_allocated);
630 map_Div->kind = INTRINSIC_INSTR;
631 map_Div->op = op_Div;
632 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
633 map_Div->ctx = &rt_iDiv;
635 /* ... nor an unsigned div instruction ... */
637 i_instr_record *map_Div = &records[n_records++].i_instr;
639 tp = new_type_method(ID("rt_uDiv"), 2, 1);
640 set_method_param_type(tp, 0, uint_tp);
641 set_method_param_type(tp, 1, uint_tp);
642 set_method_res_type(tp, 0, uint_tp);
644 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
645 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
646 rt_uDiv.mode = mode_T;
647 rt_uDiv.res_mode = mode_Iu;
648 rt_uDiv.mem_proj_nr = pn_Div_M;
649 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
650 rt_uDiv.exc_proj_nr = pn_Div_X_except;
651 rt_uDiv.exc_mem_proj_nr = pn_Div_M;
652 rt_uDiv.res_proj_nr = pn_Div_res;
654 set_entity_visibility(rt_uDiv.ent, visibility_external_allocated);
656 map_Div->kind = INTRINSIC_INSTR;
657 map_Div->op = op_Div;
658 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
659 map_Div->ctx = &rt_uDiv;
661 /* ... nor a signed mod instruction ... */
663 i_instr_record *map_Mod = &records[n_records++].i_instr;
665 tp = new_type_method(ID("rt_iMod"), 2, 1);
666 set_method_param_type(tp, 0, int_tp);
667 set_method_param_type(tp, 1, int_tp);
668 set_method_res_type(tp, 0, int_tp);
670 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
671 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
672 rt_iMod.mode = mode_T;
673 rt_iMod.res_mode = mode_Is;
674 rt_iMod.mem_proj_nr = pn_Mod_M;
675 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
676 rt_iMod.exc_proj_nr = pn_Mod_X_except;
677 rt_iMod.exc_mem_proj_nr = pn_Mod_M;
678 rt_iMod.res_proj_nr = pn_Mod_res;
680 set_entity_visibility(rt_iMod.ent, visibility_external_allocated);
682 map_Mod->kind = INTRINSIC_INSTR;
683 map_Mod->op = op_Mod;
684 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
685 map_Mod->ctx = &rt_iMod;
687 /* ... nor an unsigned mod. */
689 i_instr_record *map_Mod = &records[n_records++].i_instr;
691 tp = new_type_method(ID("rt_uMod"), 2, 1);
692 set_method_param_type(tp, 0, uint_tp);
693 set_method_param_type(tp, 1, uint_tp);
694 set_method_res_type(tp, 0, uint_tp);
696 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
697 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
698 rt_uMod.mode = mode_T;
699 rt_uMod.res_mode = mode_Iu;
700 rt_uMod.mem_proj_nr = pn_Mod_M;
701 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
702 rt_uMod.exc_proj_nr = pn_Mod_X_except;
703 rt_uMod.exc_mem_proj_nr = pn_Mod_M;
704 rt_uMod.res_proj_nr = pn_Mod_res;
706 set_entity_visibility(rt_uMod.ent, visibility_external_allocated);
708 map_Mod->kind = INTRINSIC_INSTR;
709 map_Mod->op = op_Mod;
710 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
711 map_Mod->ctx = &rt_uMod;
715 lower_intrinsics(records, n_records, /*part_block_used=*/0);
718 /*****************************************************************
719 * ____ _ _ _____ _____
720 * | _ \ | | | | |_ _|/ ____| /\
721 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
722 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
723 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
724 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
726 *****************************************************************/
728 static arm_isa_t arm_isa_template = {
730 &arm_isa_if, /* isa interface */
731 &arm_gp_regs[REG_SP], /* stack pointer */
732 &arm_gp_regs[REG_R11], /* base pointer */
733 -1, /* stack direction */
734 2, /* power of two stack alignment for calls, 2^2 == 4 */
735 NULL, /* main environment */
737 5, /* reload costs */
739 0, /* use generic register names instead of SP, LR, PC */
740 ARM_FPU_ARCH_FPE, /* FPU architecture */
741 NULL, /* current code generator */
745 * Initializes the backend ISA and opens the output file.
747 static arch_env_t *arm_init(FILE *file_handle) {
748 static int inited = 0;
754 isa = XMALLOC(arm_isa_t);
755 memcpy(isa, &arm_isa_template, sizeof(*isa));
760 be_emit_init(file_handle);
762 arm_create_opcodes(&arm_irn_ops);
763 arm_handle_intrinsics();
765 /* needed for the debug support */
766 be_gas_emit_switch_section(GAS_SECTION_TEXT);
767 be_emit_cstring(".Ltext0:\n");
768 be_emit_write_line();
770 /* we mark referenced global entities, so we can only emit those which
771 * are actually referenced. (Note: you mustn't use the type visited flag
772 * elsewhere in the backend)
774 inc_master_type_visited();
777 return &isa->arch_env;
783 * Closes the output file and frees the ISA structure.
785 static void arm_done(void *self) {
786 arm_isa_t *isa = self;
788 be_gas_emit_decls(isa->arch_env.main_env, 1);
796 * Report the number of register classes.
797 * If we don't have fp instructions, report only GP
798 * here to speed up register allocation (and makes dumps
799 * smaller and more readable).
801 static unsigned arm_get_n_reg_class(const void *self) {
807 * Return the register class with requested index.
809 static const arch_register_class_t *arm_get_reg_class(const void *self,
812 assert(i < N_CLASSES);
813 return &arm_reg_classes[i];
817 * Get the register class which shall be used to store a value of a given mode.
818 * @param self The this pointer.
819 * @param mode The mode in question.
820 * @return A register class which can hold values of the given mode.
822 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
824 if (mode_is_float(mode))
825 return &arm_reg_classes[CLASS_arm_fpa];
827 return &arm_reg_classes[CLASS_arm_gp];
831 * Produces the type which sits between the stack args and the locals on the stack.
832 * it will contain the return address and space to store the old base pointer.
833 * @return The Firm type modeling the ABI between type.
835 static ir_type *arm_get_between_type(void *self) {
836 static ir_type *between_type = NULL;
837 static ir_entity *old_bp_ent = NULL;
840 if (between_type == NULL) {
841 ir_entity *ret_addr_ent;
842 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
843 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
845 between_type = new_type_class(new_id_from_str("arm_between_type"));
846 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
847 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
849 set_entity_offset(old_bp_ent, 0);
850 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
851 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
859 be_abi_call_flags_bits_t flags;
860 const arch_env_t *arch_env;
864 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
866 arm_abi_env_t *env = XMALLOC(arm_abi_env_t);
867 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
868 env->flags = fl.bits;
870 env->arch_env = arch_env;
875 * Put all registers which are saved by the prologue/epilogue in a set.
877 * @param self The callback object.
878 * @param s The result set.
880 static void arm_abi_dont_save_regs(void *self, pset *s)
882 arm_abi_env_t *env = self;
883 if (env->flags.try_omit_fp)
884 pset_insert_ptr(s, env->arch_env->bp);
888 * Generate the routine prologue.
890 * @param self The callback object.
891 * @param mem A pointer to the mem node. Update this if you define new memory.
892 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
893 * @param stack_bias Points to the current stack bias, can be modified if needed.
895 * @return The register which shall be used as a stack frame base.
897 * All nodes which define registers in @p reg_map must keep @p reg_map current.
899 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias) {
900 arm_abi_env_t *env = self;
901 ir_node *keep, *store;
904 arch_register_class_t *gp;
906 ir_node *fp, *ip, *lr, *pc;
907 ir_node *sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
911 if (env->flags.try_omit_fp)
912 return env->arch_env->sp;
914 fp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
915 ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
916 lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
917 pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
919 gp = &arm_reg_classes[CLASS_arm_gp];
921 block = get_irg_start_block(irg);
923 ip = be_new_Copy(gp, irg, block, sp);
924 arch_set_irn_register(ip, &arm_gp_regs[REG_R12]);
925 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
927 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
929 sp = new_r_Proj(irg, block, store, env->arch_env->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
930 arch_set_irn_register(sp, env->arch_env->sp);
931 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
933 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
934 be_node_set_reg_class(keep, 1, gp);
935 arch_set_irn_register(keep, &arm_gp_regs[REG_R12]);
936 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
938 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp), 4);
939 arch_set_irn_register(fp, env->arch_env->bp);
940 fp = be_new_Copy(gp, irg, block, fp); // XXX Gammelfix: only be_ nodes can have the ignore flag set
941 arch_set_irn_register(fp, env->arch_env->bp);
942 be_node_set_flags(fp, BE_OUT_POS(0), arch_irn_flags_ignore);
944 be_abi_reg_map_set(reg_map, env->arch_env->bp, fp);
945 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
946 be_abi_reg_map_set(reg_map, env->arch_env->sp, sp);
947 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
948 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
950 return env->arch_env->bp;
954 * Builds the ARM epilogue
956 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
957 arm_abi_env_t *env = self;
958 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
959 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
960 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
961 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
963 // TODO: Activate Omit fp in epilogue
964 if (env->flags.try_omit_fp) {
965 curr_sp = be_new_IncSP(env->arch_env->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
967 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
968 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
969 arch_set_irn_register(curr_lr, &arm_gp_regs[REG_LR]);
970 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
972 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
973 arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]);
974 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
975 be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
979 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, 12);
981 //set_arm_req_out_all(sub12_node, sub12_req);
982 arch_set_irn_register(sub12_node, env->arch_env->sp);
983 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
985 //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
986 //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
987 //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
988 curr_bp = new_r_Proj(env->irg, bl, load_node, env->arch_env->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
989 curr_sp = new_r_Proj(env->irg, bl, load_node, env->arch_env->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
990 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
991 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
992 arch_set_irn_register(curr_bp, env->arch_env->bp);
993 arch_set_irn_register(curr_sp, env->arch_env->sp);
994 arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]);
996 be_abi_reg_map_set(reg_map, env->arch_env->sp, curr_sp);
997 be_abi_reg_map_set(reg_map, env->arch_env->bp, curr_bp);
998 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
999 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
1002 static const be_abi_callbacks_t arm_abi_callbacks = {
1005 arm_get_between_type,
1006 arm_abi_dont_save_regs,
1013 * Get the ABI restrictions for procedure calls.
1014 * @param self The this pointer.
1015 * @param method_type The type of the method (procedure) in question.
1016 * @param abi The abi object to be modified
1018 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1022 int n = get_method_n_params(method_type);
1023 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1026 /* set abi flags for calls */
1027 call_flags.bits.left_to_right = 0;
1028 call_flags.bits.store_args_sequential = 0;
1029 /* call_flags.bits.try_omit_fp don't change this we can handle both */
1030 call_flags.bits.fp_free = 0;
1031 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1033 /* set stack parameter passing style */
1034 be_abi_call_set_flags(abi, call_flags, &arm_abi_callbacks);
1036 for (i = 0; i < n; i++) {
1037 /* reg = get reg for param i; */
1038 /* be_abi_call_param_reg(abi, i, reg); */
1040 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1042 tp = get_method_param_type(method_type, i);
1043 mode = get_type_mode(tp);
1044 be_abi_call_param_stack(abi, i, mode, 4, 0, 0);
1048 /* set return registers */
1049 n = get_method_n_ress(method_type);
1051 assert(n <= 2 && "more than two results not supported");
1053 /* In case of 64bit returns, we will have two 32bit values */
1055 tp = get_method_res_type(method_type, 0);
1056 mode = get_type_mode(tp);
1058 assert(!mode_is_float(mode) && "two FP results not supported");
1060 tp = get_method_res_type(method_type, 1);
1061 mode = get_type_mode(tp);
1063 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1065 be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0]);
1066 be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1]);
1067 } else if (n == 1) {
1068 const arch_register_t *reg;
1070 tp = get_method_res_type(method_type, 0);
1071 assert(is_atomic_type(tp));
1072 mode = get_type_mode(tp);
1074 reg = mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0];
1075 be_abi_call_res_reg(abi, 0, reg);
1079 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1081 if(!is_arm_irn(irn))
1088 * Initializes the code generator interface.
1090 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1092 return &arm_code_gen_if;
1095 list_sched_selector_t arm_sched_selector;
1098 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1100 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1102 memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
1103 /* arm_sched_selector.exectime = arm_sched_exectime; */
1104 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1105 return &arm_sched_selector;
1109 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
1115 * Returns the necessary byte alignment for storing a register of given class.
1117 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1120 /* ARM is a 32 bit CPU, no need for other alignment */
1124 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1128 panic("Unimplemented arm_get_allowed_execution_units()");
1131 static const be_machine_t *arm_get_machine(const void *self) {
1134 panic("Unimplemented arm_get_machine()");
1138 * Return irp irgs in the desired order.
1140 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
1147 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1148 * @return 1 if allowed, 0 otherwise
1150 static int arm_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) {
1151 ir_node *cmp, *cmp_a, *phi;
1155 /* currently Psi support is not implemented */
1158 /* we don't want long long Psi */
1159 #define IS_BAD_PSI_MODE(mode) (!mode_is_float(mode) && get_mode_size_bits(mode) > 32)
1161 if (get_irn_mode(sel) != mode_b)
1164 cmp = get_Proj_pred(sel);
1165 cmp_a = get_Cmp_left(cmp);
1166 mode = get_irn_mode(cmp_a);
1168 if (IS_BAD_PSI_MODE(mode))
1171 /* check the Phi nodes */
1172 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1173 ir_node *pred_i = get_irn_n(phi, i);
1174 ir_node *pred_j = get_irn_n(phi, j);
1175 ir_mode *mode_i = get_irn_mode(pred_i);
1176 ir_mode *mode_j = get_irn_mode(pred_j);
1178 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1182 #undef IS_BAD_PSI_MODE
1187 static asm_constraint_flags_t arm_parse_asm_constraint(const void *self, const char **c)
1189 /* asm not supported */
1192 return ASM_CONSTRAINT_FLAG_INVALID;
1195 static int arm_is_valid_clobber(const void *self, const char *clobber)
1203 * Returns the libFirm configuration parameter for this backend.
1205 static const backend_params *arm_get_libfirm_params(void) {
1206 static const ir_settings_if_conv_t ifconv = {
1207 4, /* maxdepth, doesn't matter for Psi-conversion */
1208 arm_is_psi_allowed /* allows or disallows Psi creation for given selector */
1210 static ir_settings_arch_dep_t ad = {
1212 1, /* Muls are fast enough on ARM but ... */
1213 31, /* ... one shift would be possible better */
1214 NULL, /* no evaluator function */
1215 0, /* SMUL is needed, only in Arch M */
1216 0, /* UMUL is needed, only in Arch M */
1217 32, /* SMUL & UMUL available for 32 bit */
1219 static backend_params p = {
1220 1, /* need dword lowering */
1221 0, /* don't support inline assembler yet */
1222 0, /* no immediate floating point mode. */
1223 NULL, /* no additional opcodes */
1224 NULL, /* will be set later */
1225 NULL, /* but yet no creator function */
1226 NULL, /* context for create_intrinsic_fkt */
1227 NULL, /* will be set below */
1228 NULL /* no immediate fp mode */
1232 p.if_conv_info = &ifconv;
1236 /* fpu set architectures. */
1237 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1238 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1239 { "fpe", ARM_FPU_ARCH_FPE },
1240 { "fpa", ARM_FPU_ARCH_FPA },
1241 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1242 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1243 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1247 static lc_opt_enum_int_var_t arch_fpu_var = {
1248 &arm_isa_template.fpu_arch, arm_fpu_items
1251 static const lc_opt_table_entry_t arm_options[] = {
1252 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1253 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1257 const arch_isa_if_t arm_isa_if = {
1260 arm_get_n_reg_class,
1262 arm_get_reg_class_for_mode,
1264 arm_get_code_generator_if,
1265 arm_get_list_sched_selector,
1266 arm_get_ilp_sched_selector,
1267 arm_get_reg_class_alignment,
1268 arm_get_libfirm_params,
1269 arm_get_allowed_execution_units,
1272 NULL, /* mark remat */
1273 arm_parse_asm_constraint,
1274 arm_is_valid_clobber
1277 void be_init_arch_arm(void)
1279 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1280 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1282 lc_opt_add_table(arm_grp, arm_options);
1284 be_register_isa_if("arm", &arm_isa_if);
1286 arm_init_transform();
1290 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);