2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Oliver Richter, Tobias Gneist
31 #include "lc_opts_enum.h"
33 #include "pseudo_irg.h"
40 #include "iroptimize.h"
48 #include "../bearch_t.h" /* the general register allocator interface */
49 #include "../benode_t.h"
50 #include "../belower.h"
51 #include "../besched_t.h"
54 #include "../bemachine.h"
55 #include "../beilpsched.h"
56 #include "../bemodule.h"
57 #include "../beirg_t.h"
58 #include "../bespillslots.h"
59 #include "../begnuas.h"
61 #include "bearch_arm_t.h"
63 #include "arm_new_nodes.h" /* arm nodes interface */
64 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
65 #include "arm_transform.h"
66 #include "arm_optimize.h"
67 #include "arm_emitter.h"
68 #include "arm_map_regs.h"
70 #define DEBUG_MODULE "firm.be.arm.isa"
72 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
73 static set *cur_reg_set = NULL;
75 /**************************************************
78 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
79 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
80 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
81 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
84 **************************************************/
87 * Return register requirements for a arm node.
88 * If the node returns a tuple (mode_T) then the proj's
89 * will be asked for this information.
91 static const arch_register_req_t *arm_get_irn_reg_req(const ir_node *node,
94 long node_pos = pos == -1 ? 0 : pos;
95 ir_mode *mode = get_irn_mode(node);
97 if (is_Block(node) || mode == mode_X) {
98 return arch_no_register_req;
101 if (mode == mode_T && pos < 0) {
102 return arch_no_register_req;
107 return arch_no_register_req;
110 return arch_no_register_req;
113 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
114 node = skip_Proj_const(node);
117 /* get requirements for our own nodes */
118 if (is_arm_irn(node)) {
119 const arch_register_req_t *req;
121 req = get_arm_in_req(node, pos);
123 req = get_arm_out_req(node, node_pos);
129 /* unknown should be transformed by now */
130 assert(!is_Unknown(node));
131 return arch_no_register_req;
134 static void arm_set_irn_reg(ir_node *irn, const arch_register_t *reg)
138 if (get_irn_mode(irn) == mode_X) {
143 pos = get_Proj_proj(irn);
144 irn = skip_Proj(irn);
147 if (is_arm_irn(irn)) {
148 const arch_register_t **slots;
150 slots = get_arm_slots(irn);
154 /* here we set the registers for the Phi nodes */
155 arm_set_firm_reg(irn, reg, cur_reg_set);
159 static const arch_register_t *arm_get_irn_reg(const ir_node *irn)
162 const arch_register_t *reg = NULL;
166 if (get_irn_mode(irn) == mode_X) {
170 pos = get_Proj_proj(irn);
171 irn = skip_Proj_const(irn);
174 if (is_arm_irn(irn)) {
175 const arch_register_t **slots;
176 slots = get_arm_slots(irn);
180 reg = arm_get_firm_reg(irn, cur_reg_set);
186 static arch_irn_class_t arm_classify(const ir_node *irn)
188 irn = skip_Proj_const(irn);
191 return arch_irn_class_branch;
193 else if (is_arm_irn(irn)) {
194 return arch_irn_class_normal;
200 static arch_irn_flags_t arm_get_flags(const ir_node *irn)
202 arch_irn_flags_t flags = arch_irn_flags_none;
204 if(is_Unknown(irn)) {
205 return arch_irn_flags_ignore;
208 if (is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
209 ir_node *pred = get_Proj_pred(irn);
210 if (is_arm_irn(pred)) {
211 flags = get_arm_out_flags(pred, get_Proj_proj(irn));
216 if (is_arm_irn(irn)) {
217 flags |= get_arm_flags(irn);
223 static ir_entity *arm_get_frame_entity(const ir_node *irn) {
224 /* we do NOT transform be_Spill or be_Reload nodes, so we never
225 have frame access using ARM nodes. */
230 static void arm_set_frame_entity(ir_node *irn, ir_entity *ent) {
233 panic("arm_set_frame_entity() called. This should not happen.");
237 * This function is called by the generic backend to correct offsets for
238 * nodes accessing the stack.
240 static void arm_set_stack_bias(ir_node *irn, int bias)
244 /* TODO: correct offset if irn accesses the stack */
247 static int arm_get_sp_bias(const ir_node *irn)
253 /* fill register allocator interface */
255 static const arch_irn_ops_t arm_irn_ops = {
261 arm_get_frame_entity,
262 arm_set_frame_entity,
265 NULL, /* get_inverse */
266 NULL, /* get_op_estimated_cost */
267 NULL, /* possible_memory_operand */
268 NULL, /* perform_memory_operand */
271 /**************************************************
274 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
275 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
276 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
277 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
280 **************************************************/
283 * Transforms the standard Firm graph into
286 static void arm_prepare_graph(void *self) {
287 arm_code_gen_t *cg = self;
289 /* transform nodes into assembler instructions */
290 arm_transform_graph(cg);
292 /* do local optimizations (mainly CSE) */
293 local_optimize_graph(cg->irg);
296 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
298 /* do code placement, to optimize the position of constants */
302 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
306 * Called immediately before emit phase.
308 static void arm_finish_irg(void *self)
310 arm_code_gen_t *cg = self;
312 /* do peephole optimizations and fix stack offsets */
313 arm_peephole_optimization(cg);
318 * These are some hooks which must be filled but are probably not needed.
320 static void arm_before_sched(void *self)
323 /* Some stuff you need to do after scheduling but before register allocation */
326 static void arm_before_ra(void *self)
329 /* Some stuff you need to do immediately after register allocation */
333 * We transform Spill and Reload here. This needs to be done before
334 * stack biasing otherwise we would miss the corrected offset for these nodes.
336 static void arm_after_ra(void *self)
338 arm_code_gen_t *cg = self;
339 be_coalesce_spillslots(cg->birg);
343 * Emits the code, closes the output file and frees
344 * the code generator interface.
346 static void arm_emit_and_done(void *self) {
347 arm_code_gen_t *cg = self;
348 ir_graph *irg = cg->irg;
350 arm_gen_routine(cg, irg);
354 /* de-allocate code generator */
355 del_set(cg->reg_set);
360 * Move a double floating point value into an integer register.
361 * Place the move operation into block bl.
363 * Handle some special cases here:
364 * 1.) A constant: simply split into two
365 * 2.) A load: simply split into two
367 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
368 ir_node **resH, ir_node **resL) {
370 tarval *tv = get_Const_tarval(arg);
373 /* get the upper 32 bits */
374 v = get_tarval_sub_bits(tv, 7);
375 v = (v << 8) | get_tarval_sub_bits(tv, 6);
376 v = (v << 8) | get_tarval_sub_bits(tv, 5);
377 v = (v << 8) | get_tarval_sub_bits(tv, 4);
378 *resH = new_Const_long(mode_Is, v);
380 /* get the lower 32 bits */
381 v = get_tarval_sub_bits(tv, 3);
382 v = (v << 8) | get_tarval_sub_bits(tv, 2);
383 v = (v << 8) | get_tarval_sub_bits(tv, 1);
384 v = (v << 8) | get_tarval_sub_bits(tv, 0);
385 *resL = new_Const_long(mode_Is, v);
386 } else if (is_Load(skip_Proj(arg))) {
387 /* FIXME: handling of low/high depends on LE/BE here */
388 panic("Unimplemented convert_dbl_to_int() case");
391 ir_graph *irg = current_ir_graph;
394 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
396 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
397 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
398 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
404 * Move a single floating point value into an integer register.
405 * Place the move operation into block bl.
407 * Handle some special cases here:
408 * 1.) A constant: simply move
409 * 2.) A load: simply load
411 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg)
416 tarval *tv = get_Const_tarval(arg);
419 /* get the lower 32 bits */
420 v = get_tarval_sub_bits(tv, 3);
421 v = (v << 8) | get_tarval_sub_bits(tv, 2);
422 v = (v << 8) | get_tarval_sub_bits(tv, 1);
423 v = (v << 8) | get_tarval_sub_bits(tv, 0);
424 return new_Const_long(mode_Is, v);
425 } else if (is_Load(skip_Proj(arg))) {
428 load = skip_Proj(arg);
430 panic("Unimplemented convert_sng_to_int() case");
434 * Convert the arguments of a call to support the
435 * ARM calling convention of general purpose AND floating
438 static void handle_calls(ir_node *call, void *env)
440 arm_code_gen_t *cg = env;
441 int i, j, n, size, idx, flag, n_param, n_res, first_variadic;
442 ir_type *mtp, *new_mtd, *new_tp[5];
443 ir_node *new_in[5], **in;
449 /* check, if we need conversions */
450 n = get_Call_n_params(call);
451 mtp = get_Call_type(call);
452 assert(get_method_n_params(mtp) == n);
454 /* it's always enough to handle the first 4 parameters */
457 flag = size = idx = 0;
458 bl = get_nodes_block(call);
459 for (i = 0; i < n; ++i) {
460 ir_type *param_tp = get_method_param_type(mtp, i);
462 if (is_compound_type(param_tp)) {
463 /* an aggregate parameter: bad case */
467 /* a primitive parameter */
468 ir_mode *mode = get_type_mode(param_tp);
470 if (mode_is_float(mode)) {
471 if (get_mode_size_bits(mode) > 32) {
472 ir_node *mem = get_Call_mem(call);
474 /* Beware: ARM wants the high part first */
476 new_tp[idx] = cg->int_tp;
477 new_tp[idx+1] = cg->int_tp;
478 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
480 set_Call_mem(call, mem);
484 new_tp[idx] = cg->int_tp;
485 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
492 new_tp[idx] = param_tp;
493 new_in[idx] = get_Call_param(call, i);
502 /* if flag is NOT set, no need to translate the method type */
506 /* construct a new method type */
508 n_param = get_method_n_params(mtp) - n + idx;
509 n_res = get_method_n_ress(mtp);
510 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
512 for (i = 0; i < idx; ++i)
513 set_method_param_type(new_mtd, i, new_tp[i]);
514 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
515 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
516 for (i = 0; i < n_res; ++i)
517 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
519 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
520 first_variadic = get_method_first_variadic_param_index(mtp);
521 if (first_variadic >= 0)
522 set_method_first_variadic_param_index(new_mtd, first_variadic);
524 if (is_lowered_type(mtp)) {
525 mtp = get_associated_type(mtp);
527 set_lowered_type(mtp, new_mtd);
529 set_Call_type(call, new_mtd);
531 /* calculate new in array of the Call */
532 NEW_ARR_A(ir_node *, in, n_param + 2);
533 for (i = 0; i < idx; ++i)
534 in[2 + i] = new_in[i];
535 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
536 in[2 + j++] = get_Call_param(call, i);
538 in[0] = get_Call_mem(call);
539 in[1] = get_Call_ptr(call);
541 /* finally, change the call inputs */
542 set_irn_in(call, n_param + 2, in);
546 * Handle graph transformations before the abi converter does its work.
548 static void arm_before_abi(void *self) {
549 arm_code_gen_t *cg = self;
551 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
555 static void *arm_cg_init(be_irg_t *birg);
557 static const arch_code_generator_if_t arm_code_gen_if = {
559 NULL, /* get_pic_base */
560 arm_before_abi, /* before abi introduce */
563 arm_before_sched, /* before scheduling hook */
564 arm_before_ra, /* before register allocation hook */
571 * Initializes the code generator.
573 static void *arm_cg_init(be_irg_t *birg) {
574 static ir_type *int_tp = NULL;
575 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env;
579 /* create an integer type with machine size */
580 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
583 cg = xmalloc(sizeof(*cg));
584 cg->impl = &arm_code_gen_if;
586 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
587 cg->arch_env = birg->main_env->arch_env;
591 cg->have_fp_insn = 0;
592 cg->unknown_gp = NULL;
593 cg->unknown_fpa = NULL;
594 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
596 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
598 cur_reg_set = cg->reg_set;
600 /* enter the current code generator */
603 return (arch_code_generator_t *)cg;
608 * Maps all intrinsic calls that the backend support
609 * and map all instructions the backend did not support
612 static void arm_handle_intrinsics(void) {
613 ir_type *tp, *int_tp, *uint_tp;
617 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
619 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
621 int_tp = new_type_primitive(ID("int"), mode_Is);
622 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
624 /* ARM has neither a signed div instruction ... */
626 i_instr_record *map_Div = &records[n_records++].i_instr;
628 tp = new_type_method(ID("rt_iDiv"), 2, 1);
629 set_method_param_type(tp, 0, int_tp);
630 set_method_param_type(tp, 1, int_tp);
631 set_method_res_type(tp, 0, int_tp);
633 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
634 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
635 rt_iDiv.mode = mode_T;
636 rt_iDiv.res_mode = mode_Is;
637 rt_iDiv.mem_proj_nr = pn_Div_M;
638 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
639 rt_iDiv.exc_proj_nr = pn_Div_X_except;
640 rt_iDiv.exc_mem_proj_nr = pn_Div_M;
641 rt_iDiv.res_proj_nr = pn_Div_res;
643 set_entity_visibility(rt_iDiv.ent, visibility_external_allocated);
645 map_Div->kind = INTRINSIC_INSTR;
646 map_Div->op = op_Div;
647 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
648 map_Div->ctx = &rt_iDiv;
650 /* ... nor an unsigned div instruction ... */
652 i_instr_record *map_Div = &records[n_records++].i_instr;
654 tp = new_type_method(ID("rt_uDiv"), 2, 1);
655 set_method_param_type(tp, 0, uint_tp);
656 set_method_param_type(tp, 1, uint_tp);
657 set_method_res_type(tp, 0, uint_tp);
659 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
660 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
661 rt_uDiv.mode = mode_T;
662 rt_uDiv.res_mode = mode_Iu;
663 rt_uDiv.mem_proj_nr = pn_Div_M;
664 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
665 rt_uDiv.exc_proj_nr = pn_Div_X_except;
666 rt_uDiv.exc_mem_proj_nr = pn_Div_M;
667 rt_uDiv.res_proj_nr = pn_Div_res;
669 set_entity_visibility(rt_uDiv.ent, visibility_external_allocated);
671 map_Div->kind = INTRINSIC_INSTR;
672 map_Div->op = op_Div;
673 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
674 map_Div->ctx = &rt_uDiv;
676 /* ... nor a signed mod instruction ... */
678 i_instr_record *map_Mod = &records[n_records++].i_instr;
680 tp = new_type_method(ID("rt_iMod"), 2, 1);
681 set_method_param_type(tp, 0, int_tp);
682 set_method_param_type(tp, 1, int_tp);
683 set_method_res_type(tp, 0, int_tp);
685 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
686 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
687 rt_iMod.mode = mode_T;
688 rt_iMod.res_mode = mode_Is;
689 rt_iMod.mem_proj_nr = pn_Mod_M;
690 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
691 rt_iMod.exc_proj_nr = pn_Mod_X_except;
692 rt_iMod.exc_mem_proj_nr = pn_Mod_M;
693 rt_iMod.res_proj_nr = pn_Mod_res;
695 set_entity_visibility(rt_iMod.ent, visibility_external_allocated);
697 map_Mod->kind = INTRINSIC_INSTR;
698 map_Mod->op = op_Mod;
699 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
700 map_Mod->ctx = &rt_iMod;
702 /* ... nor an unsigned mod. */
704 i_instr_record *map_Mod = &records[n_records++].i_instr;
706 tp = new_type_method(ID("rt_uMod"), 2, 1);
707 set_method_param_type(tp, 0, uint_tp);
708 set_method_param_type(tp, 1, uint_tp);
709 set_method_res_type(tp, 0, uint_tp);
711 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
712 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
713 rt_uMod.mode = mode_T;
714 rt_uMod.res_mode = mode_Iu;
715 rt_uMod.mem_proj_nr = pn_Mod_M;
716 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
717 rt_uMod.exc_proj_nr = pn_Mod_X_except;
718 rt_uMod.exc_mem_proj_nr = pn_Mod_M;
719 rt_uMod.res_proj_nr = pn_Mod_res;
721 set_entity_visibility(rt_uMod.ent, visibility_external_allocated);
723 map_Mod->kind = INTRINSIC_INSTR;
724 map_Mod->op = op_Mod;
725 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
726 map_Mod->ctx = &rt_uMod;
730 lower_intrinsics(records, n_records, /*part_block_used=*/0);
733 /*****************************************************************
734 * ____ _ _ _____ _____
735 * | _ \ | | | | |_ _|/ ____| /\
736 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
737 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
738 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
739 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
741 *****************************************************************/
743 static arm_isa_t arm_isa_template = {
745 &arm_isa_if, /* isa interface */
746 &arm_gp_regs[REG_SP], /* stack pointer */
747 &arm_gp_regs[REG_R11], /* base pointer */
748 -1, /* stack direction */
749 2, /* power of two stack alignment for calls, 2^2 == 4 */
750 NULL, /* main environment */
752 5, /* reload costs */
754 0, /* use generic register names instead of SP, LR, PC */
755 ARM_FPU_ARCH_FPE, /* FPU architecture */
756 NULL, /* current code generator */
760 * Initializes the backend ISA and opens the output file.
762 static arch_env_t *arm_init(FILE *file_handle) {
763 static int inited = 0;
769 isa = xmalloc(sizeof(*isa));
770 memcpy(isa, &arm_isa_template, sizeof(*isa));
775 be_emit_init(file_handle);
777 arm_create_opcodes(&arm_irn_ops);
778 arm_handle_intrinsics();
780 /* needed for the debug support */
781 be_gas_emit_switch_section(GAS_SECTION_TEXT);
782 be_emit_cstring(".Ltext0:\n");
783 be_emit_write_line();
785 /* we mark referenced global entities, so we can only emit those which
786 * are actually referenced. (Note: you mustn't use the type visited flag
787 * elsewhere in the backend)
789 inc_master_type_visited();
792 return &isa->arch_env;
798 * Closes the output file and frees the ISA structure.
800 static void arm_done(void *self) {
801 arm_isa_t *isa = self;
803 be_gas_emit_decls(isa->arch_env.main_env, 1);
811 * Report the number of register classes.
812 * If we don't have fp instructions, report only GP
813 * here to speed up register allocation (and makes dumps
814 * smaller and more readable).
816 static unsigned arm_get_n_reg_class(const void *self) {
822 * Return the register class with requested index.
824 static const arch_register_class_t *arm_get_reg_class(const void *self,
827 assert(i < N_CLASSES);
828 return &arm_reg_classes[i];
832 * Get the register class which shall be used to store a value of a given mode.
833 * @param self The this pointer.
834 * @param mode The mode in question.
835 * @return A register class which can hold values of the given mode.
837 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
839 if (mode_is_float(mode))
840 return &arm_reg_classes[CLASS_arm_fpa];
842 return &arm_reg_classes[CLASS_arm_gp];
846 * Produces the type which sits between the stack args and the locals on the stack.
847 * it will contain the return address and space to store the old base pointer.
848 * @return The Firm type modeling the ABI between type.
850 static ir_type *arm_get_between_type(void *self) {
851 static ir_type *between_type = NULL;
852 static ir_entity *old_bp_ent = NULL;
855 if (between_type == NULL) {
856 ir_entity *ret_addr_ent;
857 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
858 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
860 between_type = new_type_class(new_id_from_str("arm_between_type"));
861 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
862 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
864 set_entity_offset(old_bp_ent, 0);
865 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
866 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
874 be_abi_call_flags_bits_t flags;
875 const arch_env_t *arch_env;
879 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
881 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
882 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
883 env->flags = fl.bits;
885 env->arch_env = arch_env;
890 * Put all registers which are saved by the prologue/epilogue in a set.
892 * @param self The callback object.
893 * @param s The result set.
895 static void arm_abi_dont_save_regs(void *self, pset *s)
897 arm_abi_env_t *env = self;
898 if (env->flags.try_omit_fp)
899 pset_insert_ptr(s, env->arch_env->bp);
903 * Generate the routine prologue.
905 * @param self The callback object.
906 * @param mem A pointer to the mem node. Update this if you define new memory.
907 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
908 * @param stack_bias Points to the current stack bias, can be modified if needed.
910 * @return The register which shall be used as a stack frame base.
912 * All nodes which define registers in @p reg_map must keep @p reg_map current.
914 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias) {
915 arm_abi_env_t *env = self;
916 ir_node *keep, *store;
919 arch_register_class_t *gp;
921 ir_node *fp, *ip, *lr, *pc;
922 ir_node *sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
926 if (env->flags.try_omit_fp)
927 return env->arch_env->sp;
929 fp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
930 ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
931 lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
932 pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
934 gp = &arm_reg_classes[CLASS_arm_gp];
936 block = get_irg_start_block(irg);
938 ip = be_new_Copy(gp, irg, block, sp);
939 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
940 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
942 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
944 sp = new_r_Proj(irg, block, store, env->arch_env->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
945 arch_set_irn_register(env->arch_env, sp, env->arch_env->sp);
946 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
948 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
949 be_node_set_reg_class(keep, 1, gp);
950 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
951 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
953 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp), 4);
954 arch_set_irn_register(env->arch_env, fp, env->arch_env->bp);
955 fp = be_new_Copy(gp, irg, block, fp); // XXX Gammelfix: only be_ nodes can have the ignore flag set
956 arch_set_irn_register(env->arch_env, fp, env->arch_env->bp);
957 be_node_set_flags(fp, BE_OUT_POS(0), arch_irn_flags_ignore);
959 be_abi_reg_map_set(reg_map, env->arch_env->bp, fp);
960 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
961 be_abi_reg_map_set(reg_map, env->arch_env->sp, sp);
962 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
963 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
965 return env->arch_env->bp;
969 * Builds the ARM epilogue
971 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
972 arm_abi_env_t *env = self;
973 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
974 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
975 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
976 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
978 // TODO: Activate Omit fp in epilogue
979 if (env->flags.try_omit_fp) {
980 curr_sp = be_new_IncSP(env->arch_env->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
981 add_irn_dep(curr_sp, *mem);
983 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
984 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
985 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
986 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
988 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
989 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
990 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
991 be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
995 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, 12);
997 //set_arm_req_out_all(sub12_node, sub12_req);
998 arch_set_irn_register(env->arch_env, sub12_node, env->arch_env->sp);
999 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
1001 //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
1002 //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
1003 //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
1004 curr_bp = new_r_Proj(env->irg, bl, load_node, env->arch_env->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
1005 curr_sp = new_r_Proj(env->irg, bl, load_node, env->arch_env->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
1006 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
1007 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
1008 arch_set_irn_register(env->arch_env, curr_bp, env->arch_env->bp);
1009 arch_set_irn_register(env->arch_env, curr_sp, env->arch_env->sp);
1010 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
1012 be_abi_reg_map_set(reg_map, env->arch_env->sp, curr_sp);
1013 be_abi_reg_map_set(reg_map, env->arch_env->bp, curr_bp);
1014 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
1015 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
1018 static const be_abi_callbacks_t arm_abi_callbacks = {
1021 arm_get_between_type,
1022 arm_abi_dont_save_regs,
1029 * Get the ABI restrictions for procedure calls.
1030 * @param self The this pointer.
1031 * @param method_type The type of the method (procedure) in question.
1032 * @param abi The abi object to be modified
1034 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1038 int n = get_method_n_params(method_type);
1039 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1042 /* set abi flags for calls */
1043 call_flags.bits.left_to_right = 0;
1044 call_flags.bits.store_args_sequential = 0;
1045 /* call_flags.bits.try_omit_fp don't change this we can handle both */
1046 call_flags.bits.fp_free = 0;
1047 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1049 /* set stack parameter passing style */
1050 be_abi_call_set_flags(abi, call_flags, &arm_abi_callbacks);
1052 for (i = 0; i < n; i++) {
1053 /* reg = get reg for param i; */
1054 /* be_abi_call_param_reg(abi, i, reg); */
1056 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1058 tp = get_method_param_type(method_type, i);
1059 mode = get_type_mode(tp);
1060 be_abi_call_param_stack(abi, i, mode, 4, 0, 0);
1064 /* set return registers */
1065 n = get_method_n_ress(method_type);
1067 assert(n <= 2 && "more than two results not supported");
1069 /* In case of 64bit returns, we will have two 32bit values */
1071 tp = get_method_res_type(method_type, 0);
1072 mode = get_type_mode(tp);
1074 assert(!mode_is_float(mode) && "two FP results not supported");
1076 tp = get_method_res_type(method_type, 1);
1077 mode = get_type_mode(tp);
1079 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1081 be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0]);
1082 be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1]);
1083 } else if (n == 1) {
1084 const arch_register_t *reg;
1086 tp = get_method_res_type(method_type, 0);
1087 assert(is_atomic_type(tp));
1088 mode = get_type_mode(tp);
1090 reg = mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0];
1091 be_abi_call_res_reg(abi, 0, reg);
1095 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1097 if(!is_arm_irn(irn))
1104 * Initializes the code generator interface.
1106 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1108 return &arm_code_gen_if;
1111 list_sched_selector_t arm_sched_selector;
1114 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1116 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1118 memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
1119 /* arm_sched_selector.exectime = arm_sched_exectime; */
1120 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1121 return &arm_sched_selector;
1125 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
1131 * Returns the necessary byte alignment for storing a register of given class.
1133 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1136 /* ARM is a 32 bit CPU, no need for other alignment */
1140 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1144 panic("Unimplemented arm_get_allowed_execution_units()");
1147 static const be_machine_t *arm_get_machine(const void *self) {
1150 panic("Unimplemented arm_get_machine()");
1154 * Return irp irgs in the desired order.
1156 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
1163 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1164 * @return 1 if allowed, 0 otherwise
1166 static int arm_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) {
1167 ir_node *cmp, *cmp_a, *phi;
1171 /* currently Psi support is not implemented */
1174 /* we don't want long long Psi */
1175 #define IS_BAD_PSI_MODE(mode) (!mode_is_float(mode) && get_mode_size_bits(mode) > 32)
1177 if (get_irn_mode(sel) != mode_b)
1180 cmp = get_Proj_pred(sel);
1181 cmp_a = get_Cmp_left(cmp);
1182 mode = get_irn_mode(cmp_a);
1184 if (IS_BAD_PSI_MODE(mode))
1187 /* check the Phi nodes */
1188 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1189 ir_node *pred_i = get_irn_n(phi, i);
1190 ir_node *pred_j = get_irn_n(phi, j);
1191 ir_mode *mode_i = get_irn_mode(pred_i);
1192 ir_mode *mode_j = get_irn_mode(pred_j);
1194 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1198 #undef IS_BAD_PSI_MODE
1203 static asm_constraint_flags_t arm_parse_asm_constraint(const void *self, const char **c)
1205 /* asm not supported */
1208 return ASM_CONSTRAINT_FLAG_INVALID;
1211 static int arm_is_valid_clobber(const void *self, const char *clobber)
1219 * Returns the libFirm configuration parameter for this backend.
1221 static const backend_params *arm_get_libfirm_params(void) {
1222 static const ir_settings_if_conv_t ifconv = {
1223 4, /* maxdepth, doesn't matter for Psi-conversion */
1224 arm_is_psi_allowed /* allows or disallows Psi creation for given selector */
1226 static ir_settings_arch_dep_t ad = {
1228 1, /* Muls are fast enough on ARM but ... */
1229 31, /* ... one shift would be possible better */
1230 NULL, /* no evaluator function */
1231 0, /* SMUL is needed, only in Arch M */
1232 0, /* UMUL is needed, only in Arch M */
1233 32, /* SMUL & UMUL available for 32 bit */
1235 static backend_params p = {
1236 1, /* need dword lowering */
1237 0, /* don't support inline assembler yet */
1238 0, /* no immediate floating point mode. */
1239 NULL, /* no additional opcodes */
1240 NULL, /* will be set later */
1241 NULL, /* but yet no creator function */
1242 NULL, /* context for create_intrinsic_fkt */
1243 NULL, /* will be set below */
1244 NULL /* no immediate fp mode */
1248 p.if_conv_info = &ifconv;
1252 /* fpu set architectures. */
1253 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1254 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1255 { "fpe", ARM_FPU_ARCH_FPE },
1256 { "fpa", ARM_FPU_ARCH_FPA },
1257 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1258 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1259 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1263 static lc_opt_enum_int_var_t arch_fpu_var = {
1264 &arm_isa_template.fpu_arch, arm_fpu_items
1267 static const lc_opt_table_entry_t arm_options[] = {
1268 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1269 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1273 const arch_isa_if_t arm_isa_if = {
1276 arm_get_n_reg_class,
1278 arm_get_reg_class_for_mode,
1280 arm_get_code_generator_if,
1281 arm_get_list_sched_selector,
1282 arm_get_ilp_sched_selector,
1283 arm_get_reg_class_alignment,
1284 arm_get_libfirm_params,
1285 arm_get_allowed_execution_units,
1288 arm_parse_asm_constraint,
1289 arm_is_valid_clobber
1292 void be_init_arch_arm(void)
1294 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1295 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1297 lc_opt_add_table(arm_grp, arm_options);
1299 be_register_isa_if("arm", &arm_isa_if);
1301 arm_init_transform();
1305 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);