2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Oliver Richter, Tobias Gneist
31 #include "lc_opts_enum.h"
33 #include "pseudo_irg.h"
40 #include "iroptimize.h"
47 #include "../bearch_t.h" /* the general register allocator interface */
48 #include "../benode_t.h"
49 #include "../belower.h"
50 #include "../besched_t.h"
53 #include "../bemachine.h"
54 #include "../beilpsched.h"
55 #include "../bemodule.h"
56 #include "../beirg_t.h"
57 #include "../bespillslots.h"
58 #include "../begnuas.h"
60 #include "bearch_arm_t.h"
62 #include "arm_new_nodes.h" /* arm nodes interface */
63 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
64 #include "arm_transform.h"
65 #include "arm_emitter.h"
66 #include "arm_map_regs.h"
68 #define DEBUG_MODULE "firm.be.arm.isa"
70 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
71 static set *cur_reg_set = NULL;
73 /**************************************************
76 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
77 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
78 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
79 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
82 **************************************************/
85 * Return register requirements for a arm node.
86 * If the node returns a tuple (mode_T) then the proj's
87 * will be asked for this information.
90 arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node,
93 long node_pos = pos == -1 ? 0 : pos;
94 ir_mode *mode = get_irn_mode(node);
97 if (is_Block(node) || mode == mode_X) {
98 return arch_no_register_req;
101 if (mode == mode_T && pos < 0) {
102 return arch_no_register_req;
107 return arch_no_register_req;
110 return arch_no_register_req;
113 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
114 node = skip_Proj_const(node);
117 /* get requirements for our own nodes */
118 if (is_arm_irn(node)) {
119 const arch_register_req_t *req;
121 req = get_arm_in_req(node, pos);
123 req = get_arm_out_req(node, node_pos);
129 /* unknown should be transformed by now */
130 assert(!is_Unknown(node));
131 return arch_no_register_req;
134 static void arm_set_irn_reg(const void *self, ir_node *irn,
135 const arch_register_t *reg)
140 if (get_irn_mode(irn) == mode_X) {
145 pos = get_Proj_proj(irn);
146 irn = skip_Proj(irn);
149 if (is_arm_irn(irn)) {
150 const arch_register_t **slots;
152 slots = get_arm_slots(irn);
156 /* here we set the registers for the Phi nodes */
157 arm_set_firm_reg(irn, reg, cur_reg_set);
161 static const arch_register_t *arm_get_irn_reg(const void *self,
165 const arch_register_t *reg = NULL;
170 if (get_irn_mode(irn) == mode_X) {
174 pos = get_Proj_proj(irn);
175 irn = skip_Proj_const(irn);
178 if (is_arm_irn(irn)) {
179 const arch_register_t **slots;
180 slots = get_arm_slots(irn);
184 reg = arm_get_firm_reg(irn, cur_reg_set);
190 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn)
193 irn = skip_Proj_const(irn);
196 return arch_irn_class_branch;
198 else if (is_arm_irn(irn)) {
199 return arch_irn_class_normal;
205 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn)
207 arch_irn_flags_t flags = arch_irn_flags_none;
210 if(is_Unknown(irn)) {
211 return arch_irn_flags_ignore;
214 if (is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
215 ir_node *pred = get_Proj_pred(irn);
216 if (is_arm_irn(pred)) {
217 flags = get_arm_out_flags(pred, get_Proj_proj(irn));
222 if (is_arm_irn(irn)) {
223 flags |= get_arm_flags(irn);
229 static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn)
233 /* TODO: return the entity assigned to the frame */
237 static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent)
242 /* TODO: set the entity assigned to the frame */
246 * This function is called by the generic backend to correct offsets for
247 * nodes accessing the stack.
249 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias)
254 /* TODO: correct offset if irn accesses the stack */
257 static int arm_get_sp_bias(const void *self, const ir_node *irn)
264 /* fill register allocator interface */
266 static const arch_irn_ops_if_t arm_irn_ops_if = {
272 arm_get_frame_entity,
273 arm_set_frame_entity,
276 NULL, /* get_inverse */
277 NULL, /* get_op_estimated_cost */
278 NULL, /* possible_memory_operand */
279 NULL, /* perform_memory_operand */
282 arm_irn_ops_t arm_irn_ops = {
289 /**************************************************
292 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
293 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
294 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
295 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
298 **************************************************/
301 * Transforms the standard Firm graph into
304 static void arm_prepare_graph(void *self) {
305 arm_code_gen_t *cg = self;
307 /* transform nodes into assembler instructions */
308 arm_transform_graph(cg);
310 /* do local optimizations (mainly CSE) */
311 local_optimize_graph(cg->irg);
314 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
316 /* do code placement, to optimize the position of constants */
320 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
324 * Called immediately before emit phase.
326 static void arm_finish_irg(void *self)
329 /* TODO: - fix offsets for nodes accessing stack
336 * These are some hooks which must be filled but are probably not needed.
338 static void arm_before_sched(void *self)
341 /* Some stuff you need to do after scheduling but before register allocation */
344 static void arm_before_ra(void *self)
347 /* Some stuff you need to do immediately after register allocation */
351 * We transform Spill and Reload here. This needs to be done before
352 * stack biasing otherwise we would miss the corrected offset for these nodes.
354 static void arm_after_ra(void *self)
356 arm_code_gen_t *cg = self;
357 be_coalesce_spillslots(cg->birg);
361 * Emits the code, closes the output file and frees
362 * the code generator interface.
364 static void arm_emit_and_done(void *self) {
365 arm_code_gen_t *cg = self;
366 ir_graph *irg = cg->irg;
368 arm_gen_routine(cg, irg);
372 /* de-allocate code generator */
373 del_set(cg->reg_set);
378 * Move a double floating point value into an integer register.
379 * Place the move operation into block bl.
381 * Handle some special cases here:
382 * 1.) A constant: simply split into two
383 * 2.) A load: simply split into two
385 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
386 ir_node **resH, ir_node **resL) {
388 tarval *tv = get_Const_tarval(arg);
391 /* get the upper 32 bits */
392 v = get_tarval_sub_bits(tv, 7);
393 v = (v << 8) | get_tarval_sub_bits(tv, 6);
394 v = (v << 8) | get_tarval_sub_bits(tv, 5);
395 v = (v << 8) | get_tarval_sub_bits(tv, 4);
396 *resH = new_Const_long(mode_Is, v);
398 /* get the lower 32 bits */
399 v = get_tarval_sub_bits(tv, 3);
400 v = (v << 8) | get_tarval_sub_bits(tv, 2);
401 v = (v << 8) | get_tarval_sub_bits(tv, 1);
402 v = (v << 8) | get_tarval_sub_bits(tv, 0);
403 *resL = new_Const_long(mode_Is, v);
405 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
406 /* FIXME: handling of low/high depends on LE/BE here */
410 ir_graph *irg = current_ir_graph;
413 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
415 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
416 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
417 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
423 * Move a single floating point value into an integer register.
424 * Place the move operation into block bl.
426 * Handle some special cases here:
427 * 1.) A constant: simply move
428 * 2.) A load: simply load
430 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg)
435 tarval *tv = get_Const_tarval(arg);
438 /* get the lower 32 bits */
439 v = get_tarval_sub_bits(tv, 3);
440 v = (v << 8) | get_tarval_sub_bits(tv, 2);
441 v = (v << 8) | get_tarval_sub_bits(tv, 1);
442 v = (v << 8) | get_tarval_sub_bits(tv, 0);
443 return new_Const_long(mode_Is, v);
445 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
448 load = skip_Proj(arg);
455 * Convert the arguments of a call to support the
456 * ARM calling convention of general purpose AND floating
459 static void handle_calls(ir_node *call, void *env)
461 arm_code_gen_t *cg = env;
462 int i, j, n, size, idx, flag, n_param, n_res, first_variadic;
463 ir_type *mtp, *new_mtd, *new_tp[5];
464 ir_node *new_in[5], **in;
470 /* check, if we need conversions */
471 n = get_Call_n_params(call);
472 mtp = get_Call_type(call);
473 assert(get_method_n_params(mtp) == n);
475 /* it's always enough to handle the first 4 parameters */
478 flag = size = idx = 0;
479 bl = get_nodes_block(call);
480 for (i = 0; i < n; ++i) {
481 ir_type *param_tp = get_method_param_type(mtp, i);
483 if (is_compound_type(param_tp)) {
484 /* an aggregate parameter: bad case */
488 /* a primitive parameter */
489 ir_mode *mode = get_type_mode(param_tp);
491 if (mode_is_float(mode)) {
492 if (get_mode_size_bits(mode) > 32) {
493 ir_node *mem = get_Call_mem(call);
495 /* Beware: ARM wants the high part first */
497 new_tp[idx] = cg->int_tp;
498 new_tp[idx+1] = cg->int_tp;
499 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
501 set_Call_mem(call, mem);
505 new_tp[idx] = cg->int_tp;
506 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
513 new_tp[idx] = param_tp;
514 new_in[idx] = get_Call_param(call, i);
523 /* if flag is NOT set, no need to translate the method type */
527 /* construct a new method type */
529 n_param = get_method_n_params(mtp) - n + idx;
530 n_res = get_method_n_ress(mtp);
531 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
533 for (i = 0; i < idx; ++i)
534 set_method_param_type(new_mtd, i, new_tp[i]);
535 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
536 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
537 for (i = 0; i < n_res; ++i)
538 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
540 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
541 first_variadic = get_method_first_variadic_param_index(mtp);
542 if (first_variadic >= 0)
543 set_method_first_variadic_param_index(new_mtd, first_variadic);
545 if (is_lowered_type(mtp)) {
546 mtp = get_associated_type(mtp);
548 set_lowered_type(mtp, new_mtd);
550 set_Call_type(call, new_mtd);
552 /* calculate new in array of the Call */
553 NEW_ARR_A(ir_node *, in, n_param + 2);
554 for (i = 0; i < idx; ++i)
555 in[2 + i] = new_in[i];
556 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
557 in[2 + j++] = get_Call_param(call, i);
559 in[0] = get_Call_mem(call);
560 in[1] = get_Call_ptr(call);
562 /* finally, change the call inputs */
563 set_irn_in(call, n_param + 2, in);
567 * Handle graph transformations before the abi converter does its work.
569 static void arm_before_abi(void *self) {
570 arm_code_gen_t *cg = self;
572 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
576 static void *arm_cg_init(be_irg_t *birg);
578 static const arch_code_generator_if_t arm_code_gen_if = {
580 NULL, /* get_pic_base */
581 arm_before_abi, /* before abi introduce */
584 arm_before_sched, /* before scheduling hook */
585 arm_before_ra, /* before register allocation hook */
592 * Initializes the code generator.
594 static void *arm_cg_init(be_irg_t *birg) {
595 static ir_type *int_tp = NULL;
596 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
600 /* create an integer type with machine size */
601 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
604 cg = xmalloc(sizeof(*cg));
605 cg->impl = &arm_code_gen_if;
607 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
608 cg->arch_env = birg->main_env->arch_env;
612 cg->have_fp_insn = 0;
613 cg->unknown_gp = NULL;
614 cg->unknown_fpa = NULL;
615 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
617 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
619 cur_reg_set = cg->reg_set;
623 /* enter the current code generator */
626 return (arch_code_generator_t *)cg;
631 * Maps all intrinsic calls that the backend support
632 * and map all instructions the backend did not support
635 static void arm_handle_intrinsics(void) {
636 ir_type *tp, *int_tp, *uint_tp;
640 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
642 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
644 int_tp = new_type_primitive(ID("int"), mode_Is);
645 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
647 /* ARM has neither a signed div instruction ... */
649 i_instr_record *map_Div = &records[n_records++].i_instr;
651 tp = new_type_method(ID("rt_iDiv"), 2, 1);
652 set_method_param_type(tp, 0, int_tp);
653 set_method_param_type(tp, 1, int_tp);
654 set_method_res_type(tp, 0, int_tp);
656 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
657 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
658 rt_iDiv.mode = mode_T;
659 rt_iDiv.res_mode = mode_Is;
660 rt_iDiv.mem_proj_nr = pn_Div_M;
661 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
662 rt_iDiv.exc_proj_nr = pn_Div_X_except;
663 rt_iDiv.exc_mem_proj_nr = pn_Div_M;
664 rt_iDiv.res_proj_nr = pn_Div_res;
666 set_entity_visibility(rt_iDiv.ent, visibility_external_allocated);
668 map_Div->kind = INTRINSIC_INSTR;
669 map_Div->op = op_Div;
670 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
671 map_Div->ctx = &rt_iDiv;
673 /* ... nor an unsigned div instruction ... */
675 i_instr_record *map_Div = &records[n_records++].i_instr;
677 tp = new_type_method(ID("rt_uDiv"), 2, 1);
678 set_method_param_type(tp, 0, uint_tp);
679 set_method_param_type(tp, 1, uint_tp);
680 set_method_res_type(tp, 0, uint_tp);
682 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
683 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
684 rt_uDiv.mode = mode_T;
685 rt_uDiv.res_mode = mode_Iu;
686 rt_uDiv.mem_proj_nr = pn_Div_M;
687 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
688 rt_uDiv.exc_proj_nr = pn_Div_X_except;
689 rt_uDiv.exc_mem_proj_nr = pn_Div_M;
690 rt_uDiv.res_proj_nr = pn_Div_res;
692 set_entity_visibility(rt_uDiv.ent, visibility_external_allocated);
694 map_Div->kind = INTRINSIC_INSTR;
695 map_Div->op = op_Div;
696 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
697 map_Div->ctx = &rt_uDiv;
699 /* ... nor a signed mod instruction ... */
701 i_instr_record *map_Mod = &records[n_records++].i_instr;
703 tp = new_type_method(ID("rt_iMod"), 2, 1);
704 set_method_param_type(tp, 0, int_tp);
705 set_method_param_type(tp, 1, int_tp);
706 set_method_res_type(tp, 0, int_tp);
708 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
709 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
710 rt_iMod.mode = mode_T;
711 rt_iMod.res_mode = mode_Is;
712 rt_iMod.mem_proj_nr = pn_Mod_M;
713 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
714 rt_iMod.exc_proj_nr = pn_Mod_X_except;
715 rt_iMod.exc_mem_proj_nr = pn_Mod_M;
716 rt_iMod.res_proj_nr = pn_Mod_res;
718 set_entity_visibility(rt_iMod.ent, visibility_external_allocated);
720 map_Mod->kind = INTRINSIC_INSTR;
721 map_Mod->op = op_Mod;
722 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
723 map_Mod->ctx = &rt_iMod;
725 /* ... nor an unsigned mod. */
727 i_instr_record *map_Mod = &records[n_records++].i_instr;
729 tp = new_type_method(ID("rt_uMod"), 2, 1);
730 set_method_param_type(tp, 0, uint_tp);
731 set_method_param_type(tp, 1, uint_tp);
732 set_method_res_type(tp, 0, uint_tp);
734 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
735 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
736 rt_uMod.mode = mode_T;
737 rt_uMod.res_mode = mode_Iu;
738 rt_uMod.mem_proj_nr = pn_Mod_M;
739 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
740 rt_uMod.exc_proj_nr = pn_Mod_X_except;
741 rt_uMod.exc_mem_proj_nr = pn_Mod_M;
742 rt_uMod.res_proj_nr = pn_Mod_res;
744 set_entity_visibility(rt_uMod.ent, visibility_external_allocated);
746 map_Mod->kind = INTRINSIC_INSTR;
747 map_Mod->op = op_Mod;
748 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
749 map_Mod->ctx = &rt_uMod;
753 lower_intrinsics(records, n_records, /*part_block_used=*/0);
756 /*****************************************************************
757 * ____ _ _ _____ _____
758 * | _ \ | | | | |_ _|/ ____| /\
759 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
760 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
761 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
762 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
764 *****************************************************************/
766 static arm_isa_t arm_isa_template = {
768 &arm_isa_if, /* isa interface */
769 &arm_gp_regs[REG_SP], /* stack pointer */
770 &arm_gp_regs[REG_R11], /* base pointer */
771 -1, /* stack direction */
772 NULL, /* main environment */
774 5, /* reload costs */
776 0, /* use generic register names instead of SP, LR, PC */
777 ARM_FPU_ARCH_FPE, /* FPU architecture */
778 NULL, /* current code generator */
782 * Initializes the backend ISA and opens the output file.
784 static void *arm_init(FILE *file_handle) {
785 static int inited = 0;
791 isa = xmalloc(sizeof(*isa));
792 memcpy(isa, &arm_isa_template, sizeof(*isa));
797 be_emit_init(file_handle);
799 arm_create_opcodes();
800 arm_handle_intrinsics();
802 /* we mark referenced global entities, so we can only emit those which
803 * are actually referenced. (Note: you mustn't use the type visited flag
804 * elsewhere in the backend)
806 inc_master_type_visited();
815 * Closes the output file and frees the ISA structure.
817 static void arm_done(void *self) {
818 arm_isa_t *isa = self;
820 be_gas_emit_decls(isa->arch_isa.main_env, 1);
828 * Report the number of register classes.
829 * If we don't have fp instructions, report only GP
830 * here to speed up register allocation (and makes dumps
831 * smaller and more readable).
833 static unsigned arm_get_n_reg_class(const void *self) {
839 * Return the register class with requested index.
841 static const arch_register_class_t *arm_get_reg_class(const void *self,
844 assert(i < N_CLASSES);
845 return &arm_reg_classes[i];
849 * Get the register class which shall be used to store a value of a given mode.
850 * @param self The this pointer.
851 * @param mode The mode in question.
852 * @return A register class which can hold values of the given mode.
854 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
856 if (mode_is_float(mode))
857 return &arm_reg_classes[CLASS_arm_fpa];
859 return &arm_reg_classes[CLASS_arm_gp];
863 * Produces the type which sits between the stack args and the locals on the stack.
864 * it will contain the return address and space to store the old base pointer.
865 * @return The Firm type modeling the ABI between type.
867 static ir_type *arm_get_between_type(void *self) {
868 static ir_type *between_type = NULL;
869 static ir_entity *old_bp_ent = NULL;
872 if (between_type == NULL) {
873 ir_entity *ret_addr_ent;
874 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
875 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
877 between_type = new_type_class(new_id_from_str("arm_between_type"));
878 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
879 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
881 set_entity_offset(old_bp_ent, 0);
882 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
883 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
891 be_abi_call_flags_bits_t flags;
892 const arch_env_t *arch_env;
893 const arch_isa_t *isa;
897 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
899 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
900 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
901 env->flags = fl.bits;
903 env->arch_env = arch_env;
904 env->isa = arch_env->isa;
908 static void arm_abi_dont_save_regs(void *self, pset *s)
910 arm_abi_env_t *env = self;
911 if (env->flags.try_omit_fp)
912 pset_insert_ptr(s, env->isa->bp);
918 * Build the ARM prolog
920 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
921 ir_node *keep, *store;
922 arm_abi_env_t *env = self;
923 ir_graph *irg = env->irg;
924 ir_node *block = get_irg_start_block(irg);
925 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
927 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
928 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
929 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
930 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
931 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
933 if (env->flags.try_omit_fp)
936 ip = be_new_Copy(gp, irg, block, sp);
937 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
938 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
940 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
942 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
943 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
944 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
946 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
947 be_node_set_reg_class(keep, 1, gp);
948 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
949 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
951 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp), 4);
952 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
954 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
955 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
956 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
957 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
958 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
964 * Builds the ARM epilogue
966 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
967 arm_abi_env_t *env = self;
968 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
969 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
970 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
971 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
973 // TODO: Activate Omit fp in epilogue
974 if (env->flags.try_omit_fp) {
975 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
976 add_irn_dep(curr_sp, *mem);
978 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
979 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
980 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
981 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
983 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
984 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
985 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
986 be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
990 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, 12);
992 //set_arm_req_out_all(sub12_node, sub12_req);
993 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
994 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
996 //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
997 //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
998 //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
999 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
1000 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
1001 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
1002 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
1003 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
1004 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
1005 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
1007 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
1008 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
1009 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
1010 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
1013 static const be_abi_callbacks_t arm_abi_callbacks = {
1016 arm_get_between_type,
1017 arm_abi_dont_save_regs,
1024 * Get the ABI restrictions for procedure calls.
1025 * @param self The this pointer.
1026 * @param method_type The type of the method (procedure) in question.
1027 * @param abi The abi object to be modified
1029 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1033 int n = get_method_n_params(method_type);
1034 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1037 /* set abi flags for calls */
1038 call_flags.bits.left_to_right = 0;
1039 call_flags.bits.store_args_sequential = 0;
1040 /* call_flags.bits.try_omit_fp don't change this we can handle both */
1041 call_flags.bits.fp_free = 0;
1042 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1044 /* set stack parameter passing style */
1045 be_abi_call_set_flags(abi, call_flags, &arm_abi_callbacks);
1047 for (i = 0; i < n; i++) {
1048 /* reg = get reg for param i; */
1049 /* be_abi_call_param_reg(abi, i, reg); */
1051 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1053 tp = get_method_param_type(method_type, i);
1054 mode = get_type_mode(tp);
1055 be_abi_call_param_stack(abi, i, mode, 4, 0, 0);
1059 /* set return registers */
1060 n = get_method_n_ress(method_type);
1062 assert(n <= 2 && "more than two results not supported");
1064 /* In case of 64bit returns, we will have two 32bit values */
1066 tp = get_method_res_type(method_type, 0);
1067 mode = get_type_mode(tp);
1069 assert(!mode_is_float(mode) && "two FP results not supported");
1071 tp = get_method_res_type(method_type, 1);
1072 mode = get_type_mode(tp);
1074 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1076 be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0]);
1077 be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1]);
1078 } else if (n == 1) {
1079 const arch_register_t *reg;
1081 tp = get_method_res_type(method_type, 0);
1082 assert(is_atomic_type(tp));
1083 mode = get_type_mode(tp);
1085 reg = mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0];
1086 be_abi_call_res_reg(abi, 0, reg);
1090 static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1093 return &arm_irn_ops;
1096 const arch_irn_handler_t arm_irn_handler = {
1100 const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
1102 return &arm_irn_handler;
1105 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1107 if(!is_arm_irn(irn))
1114 * Initializes the code generator interface.
1116 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1118 return &arm_code_gen_if;
1121 list_sched_selector_t arm_sched_selector;
1124 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1126 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1128 memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
1129 /* arm_sched_selector.exectime = arm_sched_exectime; */
1130 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1131 return &arm_sched_selector;
1135 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
1141 * Returns the necessary byte alignment for storing a register of given class.
1143 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1146 /* ARM is a 32 bit CPU, no need for other alignment */
1150 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1158 static const be_machine_t *arm_get_machine(const void *self) {
1166 * Return irp irgs in the desired order.
1168 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
1175 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1176 * @return 1 if allowed, 0 otherwise
1178 static int arm_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) {
1179 ir_node *cmp, *cmp_a, *phi;
1183 /* currently Psi support is not implemented */
1186 /* we don't want long long Psi */
1187 #define IS_BAD_PSI_MODE(mode) (!mode_is_float(mode) && get_mode_size_bits(mode) > 32)
1189 if (get_irn_mode(sel) != mode_b)
1192 cmp = get_Proj_pred(sel);
1193 cmp_a = get_Cmp_left(cmp);
1194 mode = get_irn_mode(cmp_a);
1196 if (IS_BAD_PSI_MODE(mode))
1199 /* check the Phi nodes */
1200 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1201 ir_node *pred_i = get_irn_n(phi, i);
1202 ir_node *pred_j = get_irn_n(phi, j);
1203 ir_mode *mode_i = get_irn_mode(pred_i);
1204 ir_mode *mode_j = get_irn_mode(pred_j);
1206 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1210 #undef IS_BAD_PSI_MODE
1216 * Returns the libFirm configuration parameter for this backend.
1218 static const backend_params *arm_get_libfirm_params(void) {
1219 static const ir_settings_if_conv_t ifconv = {
1220 4, /* maxdepth, doesn't matter for Psi-conversion */
1221 arm_is_psi_allowed /* allows or disallows Psi creation for given selector */
1223 static ir_settings_arch_dep_t ad = {
1225 1, /* Muls are fast enough on ARM but ... */
1226 31, /* ... one shift would be possible better */
1227 NULL, /* no evaluator function */
1228 0, /* SMUL is needed, only in Arch M */
1229 0, /* UMUL is needed, only in Arch M */
1230 32, /* SMUL & UMUL available for 32 bit */
1232 static backend_params p = {
1233 1, /* need dword lowering */
1234 0, /* don't support inline assembler yet */
1235 NULL, /* no additional opcodes */
1236 NULL, /* will be set later */
1237 NULL, /* but yet no creator function */
1238 NULL, /* context for create_intrinsic_fkt */
1239 NULL, /* will be set below */
1243 p.if_conv_info = &ifconv;
1247 /* fpu set architectures. */
1248 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1249 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1250 { "fpe", ARM_FPU_ARCH_FPE },
1251 { "fpa", ARM_FPU_ARCH_FPA },
1252 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1253 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1254 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1258 static lc_opt_enum_int_var_t arch_fpu_var = {
1259 &arm_isa_template.fpu_arch, arm_fpu_items
1262 static const lc_opt_table_entry_t arm_options[] = {
1263 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1264 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1268 const arch_isa_if_t arm_isa_if = {
1271 arm_get_n_reg_class,
1273 arm_get_reg_class_for_mode,
1275 arm_get_irn_handler,
1276 arm_get_code_generator_if,
1277 arm_get_list_sched_selector,
1278 arm_get_ilp_sched_selector,
1279 arm_get_reg_class_alignment,
1280 arm_get_libfirm_params,
1281 arm_get_allowed_execution_units,
1286 void be_init_arch_arm(void)
1288 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1289 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1291 lc_opt_add_table(arm_grp, arm_options);
1293 be_register_isa_if("arm", &arm_isa_if);
1295 arm_init_transform();
1299 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);