1 /* The main arm backend driver file. */
9 #include <libcore/lc_opts.h>
10 #include <libcore/lc_opts_enum.h>
11 #endif /* WITH_LIBCORE */
13 #include "pseudo_irg.h"
19 #include "lower_intrinsics.h"
24 #include "../bearch.h" /* the general register allocator interface */
25 #include "../benode_t.h"
26 #include "../belower.h"
27 #include "../besched_t.h"
31 #include "bearch_arm_t.h"
33 #include "arm_new_nodes.h" /* arm nodes interface */
34 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
35 #include "arm_gen_decls.h" /* interface declaration emitter */
36 #include "arm_transform.h"
37 #include "arm_emitter.h"
38 #include "arm_map_regs.h"
40 #define DEBUG_MODULE "firm.be.arm.isa"
42 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
43 static set *cur_reg_set = NULL;
45 /**************************************************
48 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
49 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
50 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
51 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
54 **************************************************/
56 static ir_node *my_skip_proj(const ir_node *n) {
63 * Return register requirements for a arm node.
64 * If the node returns a tuple (mode_T) then the proj's
65 * will be asked for this information.
67 static const arch_register_req_t *arm_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
68 const arm_register_req_t *irn_req;
69 long node_pos = pos == -1 ? 0 : pos;
70 ir_mode *mode = get_irn_mode(irn);
71 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
73 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
74 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
78 if (mode == mode_T && pos < 0) {
79 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
83 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
86 /* in case of a proj, we need to get the correct OUT slot */
87 /* of the node corresponding to the proj number */
89 node_pos = arm_translate_proj_pos(irn);
95 irn = my_skip_proj(irn);
97 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
100 /* get requirements for our own nodes */
101 if (is_arm_irn(irn)) {
103 irn_req = get_arm_in_req(irn, pos);
106 irn_req = get_arm_out_req(irn, node_pos);
109 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
111 memcpy(req, &(irn_req->req), sizeof(*req));
113 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
114 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
115 req->other_same = get_irn_n(irn, irn_req->same_pos);
118 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
119 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
120 req->other_different = get_irn_n(irn, irn_req->different_pos);
123 /* get requirements for FIRM nodes */
125 /* treat Phi like Const with default requirements */
127 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
129 if (mode_is_float(mode)) {
130 memcpy(req, &(arm_default_req_arm_fpa.req), sizeof(*req));
132 else if (mode_is_int(mode) || mode_is_reference(mode)) {
133 memcpy(req, &(arm_default_req_arm_gp.req), sizeof(*req));
135 else if (mode == mode_T || mode == mode_M) {
136 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
140 assert(0 && "unsupported Phi-Mode");
144 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
152 static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
157 if (get_irn_mode(irn) == mode_X) {
161 pos = arm_translate_proj_pos(irn);
162 irn = my_skip_proj(irn);
165 if (is_arm_irn(irn)) {
166 const arch_register_t **slots;
168 slots = get_arm_slots(irn);
172 /* here we set the registers for the Phi nodes */
173 arm_set_firm_reg(irn, reg, cur_reg_set);
177 static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) {
179 const arch_register_t *reg = NULL;
183 if (get_irn_mode(irn) == mode_X) {
187 pos = arm_translate_proj_pos(irn);
188 irn = my_skip_proj(irn);
191 if (is_arm_irn(irn)) {
192 const arch_register_t **slots;
193 slots = get_arm_slots(irn);
197 reg = arm_get_firm_reg(irn, cur_reg_set);
203 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
204 irn = my_skip_proj(irn);
207 return arch_irn_class_branch;
209 else if (is_arm_irn(irn)) {
210 return arch_irn_class_normal;
216 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
217 irn = my_skip_proj(irn);
219 if (is_arm_irn(irn)) {
220 return get_arm_flags(irn);
222 else if (is_Unknown(irn)) {
223 return arch_irn_flags_ignore;
229 static entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
230 /* TODO: return the entity assigned to the frame */
234 static void arm_set_frame_entity(const void *self, const ir_node *irn, entity *ent) {
235 /* TODO: set the entity assigned to the frame */
239 * This function is called by the generic backend to correct offsets for
240 * nodes accessing the stack.
242 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
243 /* TODO: correct offset if irn accesses the stack */
246 /* fill register allocator interface */
248 static const arch_irn_ops_if_t arm_irn_ops_if = {
254 arm_get_frame_entity,
255 arm_set_frame_entity,
257 NULL, /* get_inverse */
258 NULL, /* get_op_estimated_cost */
259 NULL, /* possible_memory_operand */
260 NULL, /* perform_memory_operand */
263 arm_irn_ops_t arm_irn_ops = {
270 /**************************************************
273 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
274 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
275 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
276 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
279 **************************************************/
282 * Transforms the standard Firm graph into
285 static void arm_prepare_graph(void *self) {
286 arm_code_gen_t *cg = self;
288 arm_register_transformers();
289 irg_walk_blkwise_graph(cg->irg, arm_move_consts, arm_transform_node, cg);
295 * Called immediately before emit phase.
297 static void arm_finish_irg(void *self) {
298 /* TODO: - fix offsets for nodes accessing stack
305 * These are some hooks which must be filled but are probably not needed.
307 static void arm_before_sched(void *self) {
308 /* Some stuff you need to do after scheduling but before register allocation */
311 static void arm_before_ra(void *self) {
312 /* Some stuff you need to do immediately after register allocation */
317 * Emits the code, closes the output file and frees
318 * the code generator interface.
320 static void arm_emit_and_done(void *self) {
321 arm_code_gen_t *cg = self;
322 ir_graph *irg = cg->irg;
323 FILE *out = cg->isa->out;
325 if (cg->emit_decls) {
330 dump_ir_block_graph_sched(irg, "-arm-finished");
331 arm_gen_routine(out, irg, cg);
335 /* de-allocate code generator */
336 del_set(cg->reg_set);
341 * Move a double floating point value into an integer register.
342 * Place the move operation into block bl.
344 * Handle some special cases here:
345 * 1.) A constant: simply split into two
346 * 2.) A load: siply split into two
348 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
349 ir_node **resH, ir_node **resL) {
351 tarval *tv = get_Const_tarval(arg);
354 /* get the upper 32 bits */
355 v = get_tarval_sub_bits(tv, 7);
356 v = (v << 8) | get_tarval_sub_bits(tv, 6);
357 v = (v << 8) | get_tarval_sub_bits(tv, 5);
358 v = (v << 8) | get_tarval_sub_bits(tv, 4);
359 *resH = new_Const_long(mode_Is, v);
361 /* get the lower 32 bits */
362 v = get_tarval_sub_bits(tv, 3);
363 v = (v << 8) | get_tarval_sub_bits(tv, 2);
364 v = (v << 8) | get_tarval_sub_bits(tv, 1);
365 v = (v << 8) | get_tarval_sub_bits(tv, 0);
366 *resL = new_Const_long(mode_Is, v);
368 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
369 /* FIXME: handling of low/high depends on LE/BE here */
373 ir_graph *irg = current_ir_graph;
376 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
378 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
379 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
380 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
386 * Move a single floating point value into an integer register.
387 * Place the move operation into block bl.
389 * Handle some special cases here:
390 * 1.) A constant: simply move
391 * 2.) A load: siply load
393 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) {
395 tarval *tv = get_Const_tarval(arg);
398 /* get the lower 32 bits */
399 v = get_tarval_sub_bits(tv, 3);
400 v = (v << 8) | get_tarval_sub_bits(tv, 2);
401 v = (v << 8) | get_tarval_sub_bits(tv, 1);
402 v = (v << 8) | get_tarval_sub_bits(tv, 0);
403 return new_Const_long(mode_Is, v);
405 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
408 load = skip_Proj(arg);
415 * Convert the arguments of a call to support the
416 * ARM calling convention of general purpose AND floating
419 static void handle_calls(ir_node *call, void *env)
421 arm_code_gen_t *cg = env;
422 int i, j, n, size, idx, flag, n_param, n_res;
423 ir_type *mtp, *new_mtd, *new_tp[5];
424 ir_node *new_in[5], **in;
430 /* check, if we need conversions */
431 n = get_Call_n_params(call);
432 mtp = get_Call_type(call);
433 assert(get_method_n_params(mtp) == n);
435 /* it's always enough to handle the first 4 parameters */
438 flag = size = idx = 0;
439 bl = get_nodes_block(call);
440 for (i = 0; i < n; ++i) {
441 ir_type *param_tp = get_method_param_type(mtp, i);
443 if (is_compound_type(param_tp)) {
444 /* an aggregate parameter: bad case */
448 /* a primitive parameter */
449 ir_mode *mode = get_type_mode(param_tp);
451 if (mode_is_float(mode)) {
452 if (get_mode_size_bits(mode) > 32) {
453 ir_node *mem = get_Call_mem(call);
455 /* Beware: ARM wants the high part first */
457 new_tp[idx] = cg->int_tp;
458 new_tp[idx+1] = cg->int_tp;
459 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
461 set_Call_mem(call, mem);
465 new_tp[idx] = cg->int_tp;
466 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
473 new_tp[idx] = param_tp;
474 new_in[idx] = get_Call_param(call, i);
483 /* if flag is NOT set, no need to translate the method type */
487 /* construct a new method type */
489 n_param = get_method_n_params(mtp) - n + idx;
490 n_res = get_method_n_ress(mtp);
491 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
493 for (i = 0; i < idx; ++i)
494 set_method_param_type(new_mtd, i, new_tp[i]);
495 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
496 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
497 for (i = 0; i < n_res; ++i)
498 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
500 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
501 set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp));
503 if (is_lowered_type(mtp)) {
504 mtp = get_associated_type(mtp);
506 set_lowered_type(mtp, new_mtd);
508 set_Call_type(call, new_mtd);
510 /* calculate new in array of the Call */
511 NEW_ARR_A(ir_node *, in, n_param + 2);
512 for (i = 0; i < idx; ++i)
513 in[2 + i] = new_in[i];
514 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
515 in[2 + j++] = get_Call_param(call, i);
517 in[0] = get_Call_mem(call);
518 in[1] = get_Call_ptr(call);
520 /* finally, change the call inputs */
521 set_irn_in(call, n_param + 2, in);
525 * Handle graph transformations before the abi converter does its work.
527 static void arm_before_abi(void *self) {
528 arm_code_gen_t *cg = self;
530 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
533 static void *arm_cg_init(const be_irg_t *birg);
535 static const arch_code_generator_if_t arm_code_gen_if = {
537 arm_before_abi, /* before abi introduce */
539 arm_before_sched, /* before scheduling hook */
540 arm_before_ra, /* before register allocation hook */
541 NULL, /* after register allocation */
547 * Initializes the code generator.
549 static void *arm_cg_init(const be_irg_t *birg) {
550 static ir_type *int_tp = NULL;
551 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
555 /* create an integer type with machine size */
556 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
559 cg = xmalloc(sizeof(*cg));
560 cg->impl = &arm_code_gen_if;
562 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
563 cg->arch_env = birg->main_env->arch_env;
569 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
573 if (isa->num_codegens > 1)
578 cur_reg_set = cg->reg_set;
582 /* enter the current code generator */
585 return (arch_code_generator_t *)cg;
590 * Maps all intrinsic calls that the backend support
591 * and map all instructions the backend did not support
594 static void arm_handle_intrinsics(void) {
595 ir_type *tp, *int_tp, *uint_tp;
599 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
601 int_tp = new_type_primitive(ID("int"), mode_Is);
602 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
604 /* ARM has neither a signed div instruction ... */
607 i_instr_record *map_Div = &records[n_records++].i_instr;
609 tp = new_type_method(ID("rt_iDiv"), 2, 1);
610 set_method_param_type(tp, 0, int_tp);
611 set_method_param_type(tp, 1, int_tp);
612 set_method_res_type(tp, 0, int_tp);
614 rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
615 rt_Div.mode = mode_T;
616 rt_Div.mem_proj_nr = pn_Div_M;
617 rt_Div.exc_proj_nr = pn_Div_X_except;
618 rt_Div.exc_mem_proj_nr = pn_Div_M;
619 rt_Div.res_proj_nr = pn_Div_res;
621 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
623 map_Div->kind = INTRINSIC_INSTR;
624 map_Div->op = op_Div;
625 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
626 map_Div->ctx = &rt_Div;
628 /* ... nor a signed div instruction ... */
631 i_instr_record *map_Div = &records[n_records++].i_instr;
633 tp = new_type_method(ID("rt_uDiv"), 2, 1);
634 set_method_param_type(tp, 0, uint_tp);
635 set_method_param_type(tp, 1, uint_tp);
636 set_method_res_type(tp, 0, uint_tp);
638 rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
639 rt_Div.mode = mode_T;
640 rt_Div.mem_proj_nr = pn_Div_M;
641 rt_Div.exc_proj_nr = pn_Div_X_except;
642 rt_Div.exc_mem_proj_nr = pn_Div_M;
643 rt_Div.res_proj_nr = pn_Div_res;
645 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
647 map_Div->kind = INTRINSIC_INSTR;
648 map_Div->op = op_Div;
649 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
650 map_Div->ctx = &rt_Div;
652 /* ... nor a signed mod instruction ... */
655 i_instr_record *map_Mod = &records[n_records++].i_instr;
657 tp = new_type_method(ID("rt_iMod"), 2, 1);
658 set_method_param_type(tp, 0, int_tp);
659 set_method_param_type(tp, 1, int_tp);
660 set_method_res_type(tp, 0, int_tp);
662 rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
663 rt_Mod.mode = mode_T;
664 rt_Mod.mem_proj_nr = pn_Mod_M;
665 rt_Mod.exc_proj_nr = pn_Mod_X_except;
666 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
667 rt_Mod.res_proj_nr = pn_Mod_res;
669 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
671 map_Mod->kind = INTRINSIC_INSTR;
672 map_Mod->op = op_Mod;
673 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
674 map_Mod->ctx = &rt_Mod;
676 /* ... nor a unsigned mod. */
679 i_instr_record *map_Mod = &records[n_records++].i_instr;
681 tp = new_type_method(ID("rt_uMod"), 2, 1);
682 set_method_param_type(tp, 0, uint_tp);
683 set_method_param_type(tp, 1, uint_tp);
684 set_method_res_type(tp, 0, uint_tp);
686 rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
687 rt_Mod.mode = mode_T;
688 rt_Mod.mem_proj_nr = pn_Mod_M;
689 rt_Mod.exc_proj_nr = pn_Mod_X_except;
690 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
691 rt_Mod.res_proj_nr = pn_Mod_res;
693 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
695 map_Mod->kind = INTRINSIC_INSTR;
696 map_Mod->op = op_Mod;
697 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
698 map_Mod->ctx = &rt_Mod;
702 lower_intrinsics(records, n_records);
705 /*****************************************************************
706 * ____ _ _ _____ _____
707 * | _ \ | | | | |_ _|/ ____| /\
708 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
709 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
710 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
711 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
713 *****************************************************************/
715 static arm_isa_t arm_isa_template = {
716 &arm_isa_if, /* isa interface */
717 &arm_gp_regs[REG_SP], /* stack pointer */
718 &arm_gp_regs[REG_R11], /* base pointer */
719 -1, /* stack direction */
720 0, /* number of codegenerator objects */
721 0, /* use generic register names instead of SP, LR, PC */
722 NULL, /* current code generator */
723 NULL, /* output file */
724 ARM_FPU_ARCH_FPE, /* FPU architecture */
728 * Initializes the backend ISA and opens the output file.
730 static void *arm_init(FILE *file_handle) {
731 static int inited = 0;
737 isa = xmalloc(sizeof(*isa));
738 memcpy(isa, &arm_isa_template, sizeof(*isa));
740 arm_register_init(isa);
741 if (isa->gen_reg_names) {
742 /* patch register names */
743 arm_gp_regs[REG_R11].name = "r11";
744 arm_gp_regs[REG_SP].name = "r13";
745 arm_gp_regs[REG_LR].name = "r14";
746 arm_gp_regs[REG_PC].name = "r15";
750 isa->out = file_handle;
752 arm_create_opcodes();
753 arm_handle_intrinsics();
754 arm_switch_section(NULL, NO_SECTION);
763 * frees the ISA structure.
765 static void arm_done(void *self) {
771 * Report the number of register classes.
772 * If we don't have fp instructions, report only GP
773 * here to speed up register allocation (and makes dumps
774 * smaller and more readable).
776 static int arm_get_n_reg_class(const void *self) {
777 const arm_isa_t *isa = self;
779 return isa->cg->have_fp ? 2 : 1;
783 * Return the register class with requested index.
785 static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
786 return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa];
790 * Get the register class which shall be used to store a value of a given mode.
791 * @param self The this pointer.
792 * @param mode The mode in question.
793 * @return A register class which can hold values of the given mode.
795 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
796 if (mode_is_float(mode))
797 return &arm_reg_classes[CLASS_arm_fpa];
799 return &arm_reg_classes[CLASS_arm_gp];
803 * Produces the type which sits between the stack args and the locals on the stack.
804 * it will contain the return address and space to store the old base pointer.
805 * @return The Firm type modelling the ABI between type.
807 static ir_type *arm_get_between_type(void *self) {
808 static ir_type *between_type = NULL;
809 static entity *old_bp_ent = NULL;
812 entity *ret_addr_ent;
813 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
814 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
816 between_type = new_type_class(new_id_from_str("arm_between_type"));
817 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
818 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
820 set_entity_offset_bytes(old_bp_ent, 0);
821 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
822 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
830 be_abi_call_flags_bits_t flags;
831 const arch_env_t *arch_env;
832 const arch_isa_t *isa;
836 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
838 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
839 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
840 env->flags = fl.bits;
842 env->arch_env = arch_env;
843 env->isa = arch_env->isa;
847 static void arm_abi_dont_save_regs(void *self, pset *s)
849 arm_abi_env_t *env = self;
850 if (env->flags.try_omit_fp)
851 pset_insert_ptr(s, env->isa->bp);
857 * Build the ARM prolog
859 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
860 ir_node *keep, *store;
861 arm_abi_env_t *env = self;
862 ir_graph *irg = env->irg;
863 ir_node *block = get_irg_start_block(irg);
864 // ir_node *regs[16];
866 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
867 static const arm_register_req_t *fp_req[] = {
868 &arm_default_req_arm_gp_r11
871 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
872 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
873 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
874 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
875 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
876 // ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]);
877 // ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]);
878 // ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]);
879 // ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]);
881 if(env->flags.try_omit_fp)
884 ip = be_new_Copy(gp, irg, block, sp );
885 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
886 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
888 // if (r0) regs[n_regs++] = r0;
889 // if (r1) regs[n_regs++] = r1;
890 // if (r2) regs[n_regs++] = r2;
891 // if (r3) regs[n_regs++] = r3;
892 // sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
893 // set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
894 // arch_set_irn_register(env->arch_env, sp, env->isa->sp);
895 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
896 set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
897 // arch_set_irn_register(env->arch_env, store, env->isa->sp);
899 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
900 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
901 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
903 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
904 be_node_set_reg_class(keep, 1, gp);
905 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
906 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
908 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
909 new_tarval_from_long(4, get_irn_mode(fp)));
910 set_arm_req_out_all(fp, fp_req);
911 //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
912 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
914 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
915 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
916 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2);
917 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3);
918 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
919 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
920 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
921 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
922 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
927 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
928 arm_abi_env_t *env = self;
929 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
930 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
931 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
932 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
933 static const arm_register_req_t *sub12_req[] = {
934 &arm_default_req_arm_gp_sp
937 // TODO: Activate Omit fp in epilogue
938 if(env->flags.try_omit_fp) {
939 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
941 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
942 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
943 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
944 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
946 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
947 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
948 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
952 tarval *tv = new_tarval_from_long(12,mode_Iu);
953 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
954 set_arm_req_out_all(sub12_node, sub12_req);
955 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
956 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
957 set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
958 set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
959 set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
960 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
961 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
962 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
963 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
964 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
965 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
966 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
968 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
969 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
970 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
971 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
974 static const be_abi_callbacks_t arm_abi_callbacks = {
977 arm_get_between_type,
978 arm_abi_dont_save_regs,
985 * Get the ABI restrictions for procedure calls.
986 * @param self The this pointer.
987 * @param method_type The type of the method (procedure) in question.
988 * @param abi The abi object to be modified
990 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
994 int n = get_method_n_params(method_type);
995 be_abi_call_flags_t flags = {
997 0, /* store from left to right */
998 0, /* store arguments sequential */
999 1, /* try to omit the frame pointer */
1000 1, /* the function can use any register as frame pointer */
1001 1 /* a call can take the callee's address as an immediate */
1005 /* set stack parameter passing style */
1006 be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
1008 for (i = 0; i < n; i++) {
1009 /* reg = get reg for param i; */
1010 /* be_abi_call_param_reg(abi, i, reg); */
1013 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1015 be_abi_call_param_stack(abi, i, 4, 0, 0);
1018 /* default: return value is in R0 resp. F0 */
1019 assert(get_method_n_ress(method_type) < 2);
1020 if (get_method_n_ress(method_type) > 0) {
1021 tp = get_method_res_type(method_type, 0);
1022 mode = get_type_mode(tp);
1024 be_abi_call_res_reg(abi, 0,
1025 mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]);
1029 static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1030 return &arm_irn_ops;
1033 const arch_irn_handler_t arm_irn_handler = {
1037 const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
1038 return &arm_irn_handler;
1041 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1042 return is_arm_irn(irn);
1046 * Initializes the code generator interface.
1048 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1049 return &arm_code_gen_if;
1052 list_sched_selector_t arm_sched_selector;
1055 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1057 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self) {
1058 memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1059 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1060 return &arm_sched_selector;
1064 * Returns the necessary byte alignment for storing a register of given class.
1066 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1067 ir_mode *mode = arch_register_class_mode(cls);
1068 return get_mode_size_bytes(mode);
1072 * Returns the libFirm configuration parameter for this backend.
1074 static const backend_params *arm_get_libfirm_params(void) {
1075 static arch_dep_params_t ad = {
1077 0, /* Muls are fast enough on ARM */
1078 31, /* shift would be ok */
1079 0, /* SMUL is needed, only in Arch M*/
1080 0, /* UMUL is needed, only in Arch M */
1081 32, /* SMUL & UMUL available for 32 bit */
1083 static backend_params p = {
1084 NULL, /* no additional opcodes */
1085 NULL, /* will be set later */
1086 1, /* need dword lowering */
1087 NULL, /* but yet no creator function */
1088 NULL, /* context for create_intrinsic_fkt */
1097 /* fpu set architectures. */
1098 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1099 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1100 { "fpe", ARM_FPU_ARCH_FPE },
1101 { "fpa", ARM_FPU_ARCH_FPA },
1102 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1103 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1104 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1108 static lc_opt_enum_int_var_t arch_fpu_var = {
1109 &arm_isa_template.fpu_arch, arm_fpu_items
1112 static const lc_opt_table_entry_t arm_options[] = {
1113 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1114 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1119 * Register command line options for the ARM backend.
1123 * arm-fpuunit=unit select the floating point unit
1124 * arm-gen_reg_names use generic register names instead of SP, LR, PC
1126 static void arm_register_options(lc_opt_entry_t *ent)
1128 lc_opt_entry_t *be_grp_arm = lc_opt_get_grp(ent, "arm");
1129 lc_opt_add_table(be_grp_arm, arm_options);
1131 #endif /* WITH_LIBCORE */
1133 const arch_isa_if_t arm_isa_if = {
1136 arm_get_n_reg_class,
1138 arm_get_reg_class_for_mode,
1140 arm_get_irn_handler,
1141 arm_get_code_generator_if,
1142 arm_get_list_sched_selector,
1143 arm_get_reg_class_alignment,
1144 arm_get_libfirm_params,
1146 arm_register_options