2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist
29 #include "lc_opts_enum.h"
37 #include "iroptimize.h"
47 #include "../bearch.h"
48 #include "../benode.h"
49 #include "../belower.h"
50 #include "../besched.h"
52 #include "../bemachine.h"
53 #include "../beilpsched.h"
54 #include "../bemodule.h"
56 #include "../bespillslots.h"
57 #include "../begnuas.h"
58 #include "../belistsched.h"
59 #include "../beflags.h"
61 #include "bearch_arm_t.h"
63 #include "arm_new_nodes.h"
64 #include "gen_arm_regalloc_if.h"
65 #include "arm_transform.h"
66 #include "arm_optimize.h"
67 #include "arm_emitter.h"
68 #include "arm_map_regs.h"
70 static arch_irn_class_t arm_classify(const ir_node *irn)
73 /* TODO: we should mark reload/spill instructions and classify them here */
77 static ir_entity *arm_get_frame_entity(const ir_node *irn)
79 const arm_attr_t *attr = get_arm_attr_const(irn);
81 if (is_arm_FrameAddr(irn)) {
82 const arm_SymConst_attr_t *attr = get_irn_generic_attr_const(irn);
85 if (attr->is_load_store) {
86 const arm_load_store_attr_t *load_store_attr
87 = get_arm_load_store_attr_const(irn);
88 if (load_store_attr->is_frame_entity) {
89 return load_store_attr->entity;
96 * This function is called by the generic backend to correct offsets for
97 * nodes accessing the stack.
99 static void arm_set_stack_bias(ir_node *irn, int bias)
101 if (is_arm_FrameAddr(irn)) {
102 arm_SymConst_attr_t *attr = get_irn_generic_attr(irn);
103 attr->fp_offset += bias;
105 arm_load_store_attr_t *attr = get_arm_load_store_attr(irn);
106 assert(attr->base.is_load_store);
107 attr->offset += bias;
111 static int arm_get_sp_bias(const ir_node *irn)
113 /* We don't have any nodes changing the stack pointer.
114 We probably want to support post-/pre increment/decrement later */
119 /* fill register allocator interface */
121 static const arch_irn_ops_t arm_irn_ops = {
124 arm_get_frame_entity,
127 NULL, /* get_inverse */
128 NULL, /* get_op_estimated_cost */
129 NULL, /* possible_memory_operand */
130 NULL, /* perform_memory_operand */
134 * Transforms the standard Firm graph into
137 static void arm_prepare_graph(void *self)
139 arm_code_gen_t *cg = self;
141 /* transform nodes into assembler instructions */
142 arm_transform_graph(cg);
144 /* do local optimizations (mainly CSE) */
145 local_optimize_graph(cg->irg);
148 dump_ir_graph(cg->irg, "transformed");
150 /* do code placement, to optimize the position of constants */
154 dump_ir_graph(cg->irg, "place");
158 * Called immediately before emit phase.
160 static void arm_finish_irg(void *self)
162 arm_code_gen_t *cg = self;
164 /* do peephole optimizations and fix stack offsets */
165 arm_peephole_optimization(cg);
168 static ir_node *arm_flags_remat(ir_node *node, ir_node *after)
173 if (is_Block(after)) {
176 block = get_nodes_block(after);
178 copy = exact_copy(node);
179 set_nodes_block(copy, block);
180 sched_add_after(after, copy);
184 static void arm_before_ra(void *self)
186 arm_code_gen_t *cg = self;
188 be_sched_fix_flags(cg->irg, &arm_reg_classes[CLASS_arm_flags],
192 static void transform_Reload(ir_node *node)
194 ir_node *block = get_nodes_block(node);
195 dbg_info *dbgi = get_irn_dbg_info(node);
196 ir_node *ptr = get_irn_n(node, be_pos_Reload_frame);
197 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
198 ir_mode *mode = get_irn_mode(node);
199 ir_entity *entity = be_get_frame_entity(node);
200 const arch_register_t *reg;
204 ir_node *sched_point = sched_prev(node);
206 load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true);
207 sched_add_after(sched_point, load);
210 proj = new_rd_Proj(dbgi, load, mode, pn_arm_Ldr_res);
212 reg = arch_get_irn_register(node);
213 arch_set_irn_register(proj, reg);
215 exchange(node, proj);
218 static void transform_Spill(ir_node *node)
220 ir_node *block = get_nodes_block(node);
221 dbg_info *dbgi = get_irn_dbg_info(node);
222 ir_node *ptr = get_irn_n(node, be_pos_Spill_frame);
223 ir_node *mem = new_NoMem();
224 ir_node *val = get_irn_n(node, be_pos_Spill_val);
225 ir_mode *mode = get_irn_mode(val);
226 ir_entity *entity = be_get_frame_entity(node);
227 ir_node *sched_point;
230 sched_point = sched_prev(node);
231 store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0,
235 sched_add_after(sched_point, store);
237 exchange(node, store);
240 static void arm_after_ra_walker(ir_node *block, void *data)
242 ir_node *node, *prev;
245 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
246 prev = sched_prev(node);
248 if (be_is_Reload(node)) {
249 transform_Reload(node);
250 } else if (be_is_Spill(node)) {
251 transform_Spill(node);
256 static void arm_collect_frame_entity_nodes(ir_node *node, void *data)
258 be_fec_env_t *env = data;
262 const arm_load_store_attr_t *attr;
264 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
265 mode = get_irn_mode(node);
266 align = get_mode_size_bytes(mode);
267 be_node_needs_frame_entity(env, node, mode, align);
271 switch (get_arm_irn_opcode(node)) {
279 attr = get_arm_load_store_attr_const(node);
280 entity = attr->entity;
281 mode = attr->load_store_mode;
282 align = get_mode_size_bytes(mode);
285 if (!attr->is_frame_entity)
287 be_node_needs_frame_entity(env, node, mode, align);
290 static void arm_set_frame_entity(ir_node *node, ir_entity *entity)
292 if (is_be_node(node)) {
293 be_node_set_frame_entity(node, entity);
295 arm_load_store_attr_t *attr = get_arm_load_store_attr(node);
296 attr->entity = entity;
300 static void arm_after_ra(void *self)
302 arm_code_gen_t *cg = self;
303 ir_graph *irg = cg->irg;
305 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
307 irg_walk_graph(irg, NULL, arm_collect_frame_entity_nodes, fec_env);
308 be_assign_entities(fec_env, arm_set_frame_entity);
309 be_free_frame_entity_coalescer(fec_env);
311 irg_block_walk_graph(cg->irg, NULL, arm_after_ra_walker, NULL);
315 * Emits the code, closes the output file and frees
316 * the code generator interface.
318 static void arm_emit_and_done(void *self)
320 arm_code_gen_t *cg = self;
321 ir_graph *irg = cg->irg;
323 arm_gen_routine(cg, irg);
325 /* de-allocate code generator */
330 static void *arm_cg_init(ir_graph *irg);
332 static const arch_code_generator_if_t arm_code_gen_if = {
334 NULL, /* get_pic_base */
335 NULL, /* before abi introduce */
338 arm_before_ra, /* before register allocation hook */
345 * Initializes the code generator.
347 static void *arm_cg_init(ir_graph *irg)
349 arm_isa_t *isa = (arm_isa_t*) be_get_irg_arch_env(irg);
352 cg = XMALLOCZ(arm_code_gen_t);
353 cg->impl = &arm_code_gen_if;
356 cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
358 /* enter the current code generator */
361 return (arch_code_generator_t *)cg;
366 * Maps all intrinsic calls that the backend support
367 * and map all instructions the backend did not support
370 static void arm_handle_intrinsics(void)
372 ir_type *tp, *int_tp, *uint_tp;
376 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
378 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
380 int_tp = get_type_for_mode(mode_Is);
381 uint_tp = get_type_for_mode(mode_Iu);
383 /* ARM has neither a signed div instruction ... */
385 i_instr_record *map_Div = &records[n_records++].i_instr;
387 tp = new_type_method(2, 1);
388 set_method_param_type(tp, 0, int_tp);
389 set_method_param_type(tp, 1, int_tp);
390 set_method_res_type(tp, 0, int_tp);
392 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
393 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
394 rt_iDiv.mode = mode_T;
395 rt_iDiv.res_mode = mode_Is;
396 rt_iDiv.mem_proj_nr = pn_Div_M;
397 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
398 rt_iDiv.exc_proj_nr = pn_Div_X_except;
399 rt_iDiv.exc_mem_proj_nr = pn_Div_M;
400 rt_iDiv.res_proj_nr = pn_Div_res;
402 add_entity_linkage(rt_iDiv.ent, IR_LINKAGE_CONSTANT);
403 set_entity_visibility(rt_iDiv.ent, ir_visibility_external);
405 map_Div->kind = INTRINSIC_INSTR;
406 map_Div->op = op_Div;
407 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
408 map_Div->ctx = &rt_iDiv;
410 /* ... nor an unsigned div instruction ... */
412 i_instr_record *map_Div = &records[n_records++].i_instr;
414 tp = new_type_method(2, 1);
415 set_method_param_type(tp, 0, uint_tp);
416 set_method_param_type(tp, 1, uint_tp);
417 set_method_res_type(tp, 0, uint_tp);
419 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
420 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
421 rt_uDiv.mode = mode_T;
422 rt_uDiv.res_mode = mode_Iu;
423 rt_uDiv.mem_proj_nr = pn_Div_M;
424 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
425 rt_uDiv.exc_proj_nr = pn_Div_X_except;
426 rt_uDiv.exc_mem_proj_nr = pn_Div_M;
427 rt_uDiv.res_proj_nr = pn_Div_res;
429 set_entity_visibility(rt_uDiv.ent, ir_visibility_external);
431 map_Div->kind = INTRINSIC_INSTR;
432 map_Div->op = op_Div;
433 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
434 map_Div->ctx = &rt_uDiv;
436 /* ... nor a signed mod instruction ... */
438 i_instr_record *map_Mod = &records[n_records++].i_instr;
440 tp = new_type_method(2, 1);
441 set_method_param_type(tp, 0, int_tp);
442 set_method_param_type(tp, 1, int_tp);
443 set_method_res_type(tp, 0, int_tp);
445 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
446 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
447 rt_iMod.mode = mode_T;
448 rt_iMod.res_mode = mode_Is;
449 rt_iMod.mem_proj_nr = pn_Mod_M;
450 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
451 rt_iMod.exc_proj_nr = pn_Mod_X_except;
452 rt_iMod.exc_mem_proj_nr = pn_Mod_M;
453 rt_iMod.res_proj_nr = pn_Mod_res;
455 set_entity_visibility(rt_iMod.ent, ir_visibility_external);
457 map_Mod->kind = INTRINSIC_INSTR;
458 map_Mod->op = op_Mod;
459 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
460 map_Mod->ctx = &rt_iMod;
462 /* ... nor an unsigned mod. */
464 i_instr_record *map_Mod = &records[n_records++].i_instr;
466 tp = new_type_method(2, 1);
467 set_method_param_type(tp, 0, uint_tp);
468 set_method_param_type(tp, 1, uint_tp);
469 set_method_res_type(tp, 0, uint_tp);
471 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
472 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
473 rt_uMod.mode = mode_T;
474 rt_uMod.res_mode = mode_Iu;
475 rt_uMod.mem_proj_nr = pn_Mod_M;
476 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
477 rt_uMod.exc_proj_nr = pn_Mod_X_except;
478 rt_uMod.exc_mem_proj_nr = pn_Mod_M;
479 rt_uMod.res_proj_nr = pn_Mod_res;
481 set_entity_visibility(rt_uMod.ent, ir_visibility_external);
483 map_Mod->kind = INTRINSIC_INSTR;
484 map_Mod->op = op_Mod;
485 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
486 map_Mod->ctx = &rt_uMod;
490 lower_intrinsics(records, n_records, /*part_block_used=*/0);
493 const arch_isa_if_t arm_isa_if;
494 static arm_isa_t arm_isa_template = {
496 &arm_isa_if, /* isa interface */
497 &arm_gp_regs[REG_SP], /* stack pointer */
498 &arm_gp_regs[REG_R11], /* base pointer */
499 &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */
500 -1, /* stack direction */
501 2, /* power of two stack alignment for calls, 2^2 == 4 */
502 NULL, /* main environment */
504 5, /* reload costs */
505 true, /* we do have custom abi handling */
507 ARM_FPU_ARCH_FPE, /* FPU architecture */
508 NULL, /* current code generator */
512 * Initializes the backend ISA and opens the output file.
514 static arch_env_t *arm_init(FILE *file_handle)
516 static int inited = 0;
522 isa = XMALLOC(arm_isa_t);
523 memcpy(isa, &arm_isa_template, sizeof(*isa));
528 be_emit_init(file_handle);
530 arm_create_opcodes(&arm_irn_ops);
531 arm_handle_intrinsics();
533 be_gas_emit_types = false;
535 /* needed for the debug support */
536 be_gas_emit_switch_section(GAS_SECTION_TEXT);
537 be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
538 be_emit_write_line();
547 * Closes the output file and frees the ISA structure.
549 static void arm_done(void *self)
551 arm_isa_t *isa = self;
553 be_gas_emit_decls(isa->base.main_env);
561 * Report the number of register classes.
562 * If we don't have fp instructions, report only GP
563 * here to speed up register allocation (and makes dumps
564 * smaller and more readable).
566 static unsigned arm_get_n_reg_class(void)
572 * Return the register class with requested index.
574 static const arch_register_class_t *arm_get_reg_class(unsigned i)
576 assert(i < N_CLASSES);
577 return &arm_reg_classes[i];
581 * Get the register class which shall be used to store a value of a given mode.
582 * @param self The this pointer.
583 * @param mode The mode in question.
584 * @return A register class which can hold values of the given mode.
586 static const arch_register_class_t *arm_get_reg_class_for_mode(const ir_mode *mode)
588 if (mode_is_float(mode))
589 return &arm_reg_classes[CLASS_arm_fpa];
591 return &arm_reg_classes[CLASS_arm_gp];
594 static int arm_to_appear_in_schedule(void *block_env, const ir_node *irn)
597 if (!is_arm_irn(irn))
604 * Initializes the code generator interface.
606 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self)
609 return &arm_code_gen_if;
612 list_sched_selector_t arm_sched_selector;
615 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
617 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector)
620 memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
621 /* arm_sched_selector.exectime = arm_sched_exectime; */
622 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
623 return &arm_sched_selector;
627 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self)
634 * Returns the necessary byte alignment for storing a register of given class.
636 static int arm_get_reg_class_alignment(const arch_register_class_t *cls)
639 /* ARM is a 32 bit CPU, no need for other alignment */
643 static const be_execution_unit_t ***arm_get_allowed_execution_units(const ir_node *irn)
647 panic("Unimplemented arm_get_allowed_execution_units()");
650 static const be_machine_t *arm_get_machine(const void *self)
654 panic("Unimplemented arm_get_machine()");
658 * Return irp irgs in the desired order.
660 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list)
668 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
669 * @return 1 if allowed, 0 otherwise
671 static int arm_is_mux_allowed(ir_node *sel, ir_node *mux_false,
681 static asm_constraint_flags_t arm_parse_asm_constraint(const char **c)
683 /* asm not supported */
685 return ASM_CONSTRAINT_FLAG_INVALID;
688 static int arm_is_valid_clobber(const char *clobber)
695 * Returns the libFirm configuration parameter for this backend.
697 static const backend_params *arm_get_libfirm_params(void)
699 static const ir_settings_if_conv_t ifconv = {
700 4, /* maxdepth, doesn't matter for Psi-conversion */
701 arm_is_mux_allowed /* allows or disallows Mux creation for given selector */
703 static ir_settings_arch_dep_t ad = {
705 1, /* Muls are fast enough on ARM but ... */
706 31, /* ... one shift would be possible better */
707 NULL, /* no evaluator function */
708 0, /* SMUL is needed, only in Arch M */
709 0, /* UMUL is needed, only in Arch M */
710 32, /* SMUL & UMUL available for 32 bit */
712 static backend_params p = {
713 1, /* need dword lowering */
714 0, /* don't support inline assembler yet */
715 NULL, /* will be set later */
716 NULL, /* but yet no creator function */
717 NULL, /* context for create_intrinsic_fkt */
718 NULL, /* ifconv_info will be set below */
719 NULL, /* float arithmetic mode (TODO) */
720 0, /* no trampoline support: size 0 */
721 0, /* no trampoline support: align 0 */
722 NULL, /* no trampoline support: no trampoline builder */
723 4 /* alignment of stack parameter */
727 p.if_conv_info = &ifconv;
731 /* fpu set architectures. */
732 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
733 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
734 { "fpe", ARM_FPU_ARCH_FPE },
735 { "fpa", ARM_FPU_ARCH_FPA },
736 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
737 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
738 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
742 static lc_opt_enum_int_var_t arch_fpu_var = {
743 &arm_isa_template.fpu_arch, arm_fpu_items
746 static const lc_opt_table_entry_t arm_options[] = {
747 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
751 const arch_isa_if_t arm_isa_if = {
754 NULL, /* handle_intrinsics */
757 arm_get_reg_class_for_mode,
759 arm_get_code_generator_if,
760 arm_get_list_sched_selector,
761 arm_get_ilp_sched_selector,
762 arm_get_reg_class_alignment,
763 arm_get_libfirm_params,
764 arm_get_allowed_execution_units,
767 NULL, /* mark remat */
768 arm_parse_asm_constraint,
772 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);
773 void be_init_arch_arm(void)
775 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
776 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
778 lc_opt_add_table(arm_grp, arm_options);
780 be_register_isa_if("arm", &arm_isa_if);
782 arm_init_transform();