1 /* The main arm backend driver file. */
9 #include <libcore/lc_opts.h>
10 #include <libcore/lc_opts_enum.h>
11 #endif /* WITH_LIBCORE */
13 #include "pseudo_irg.h"
19 #include "lower_intrinsics.h"
24 #include "../bearch.h" /* the general register allocator interface */
25 #include "../benode_t.h"
26 #include "../belower.h"
27 #include "../besched_t.h"
31 #include "bearch_arm_t.h"
33 #include "arm_new_nodes.h" /* arm nodes interface */
34 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
35 #include "arm_gen_decls.h" /* interface declaration emitter */
36 #include "arm_transform.h"
37 #include "arm_emitter.h"
38 #include "arm_map_regs.h"
40 #define DEBUG_MODULE "firm.be.arm.isa"
42 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
43 static set *cur_reg_set = NULL;
45 /**************************************************
48 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
49 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
50 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
51 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
54 **************************************************/
56 static ir_node *my_skip_proj(const ir_node *n) {
63 * Return register requirements for a arm node.
64 * If the node returns a tuple (mode_T) then the proj's
65 * will be asked for this information.
67 static const arch_register_req_t *arm_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
68 const arm_register_req_t *irn_req;
69 long node_pos = pos == -1 ? 0 : pos;
70 ir_mode *mode = get_irn_mode(irn);
71 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
73 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
74 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
78 if (mode == mode_T && pos < 0) {
79 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
83 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
86 /* in case of a proj, we need to get the correct OUT slot */
87 /* of the node corresponding to the proj number */
89 node_pos = arm_translate_proj_pos(irn);
95 irn = my_skip_proj(irn);
97 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
100 /* get requirements for our own nodes */
101 if (is_arm_irn(irn)) {
103 irn_req = get_arm_in_req(irn, pos);
106 irn_req = get_arm_out_req(irn, node_pos);
109 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
111 memcpy(req, &(irn_req->req), sizeof(*req));
113 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
114 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
115 req->other_same = get_irn_n(irn, irn_req->same_pos);
118 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
119 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
120 req->other_different = get_irn_n(irn, irn_req->different_pos);
123 /* get requirements for FIRM nodes */
125 /* treat Phi like Const with default requirements */
127 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
129 if (mode_is_float(mode)) {
130 memcpy(req, &(arm_default_req_arm_fpa.req), sizeof(*req));
132 else if (mode_is_int(mode) || mode_is_reference(mode)) {
133 memcpy(req, &(arm_default_req_arm_gp.req), sizeof(*req));
135 else if (mode == mode_T || mode == mode_M) {
136 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
140 assert(0 && "unsupported Phi-Mode");
144 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
152 static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
157 if (get_irn_mode(irn) == mode_X) {
161 pos = arm_translate_proj_pos(irn);
162 irn = my_skip_proj(irn);
165 if (is_arm_irn(irn)) {
166 const arch_register_t **slots;
168 slots = get_arm_slots(irn);
172 /* here we set the registers for the Phi nodes */
173 arm_set_firm_reg(irn, reg, cur_reg_set);
177 static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) {
179 const arch_register_t *reg = NULL;
183 if (get_irn_mode(irn) == mode_X) {
187 pos = arm_translate_proj_pos(irn);
188 irn = my_skip_proj(irn);
191 if (is_arm_irn(irn)) {
192 const arch_register_t **slots;
193 slots = get_arm_slots(irn);
197 reg = arm_get_firm_reg(irn, cur_reg_set);
203 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
204 irn = my_skip_proj(irn);
207 return arch_irn_class_branch;
209 else if (is_arm_irn(irn)) {
210 return arch_irn_class_normal;
216 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
217 irn = my_skip_proj(irn);
219 if (is_arm_irn(irn)) {
220 return get_arm_flags(irn);
222 else if (is_Unknown(irn)) {
223 return arch_irn_flags_ignore;
229 static entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
230 /* TODO: return the entity assigned to the frame */
235 * This function is called by the generic backend to correct offsets for
236 * nodes accessing the stack.
238 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
239 /* TODO: correct offset if irn accesses the stack */
242 /* fill register allocator interface */
244 static const arch_irn_ops_if_t arm_irn_ops_if = {
250 arm_get_frame_entity,
255 arm_irn_ops_t arm_irn_ops = {
262 /**************************************************
265 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
266 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
267 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
268 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
271 **************************************************/
274 * Transforms the standard Firm graph into
277 static void arm_prepare_graph(void *self) {
278 arm_code_gen_t *cg = self;
280 arm_register_transformers();
281 irg_walk_blkwise_graph(cg->irg, arm_move_consts, arm_transform_node, cg);
287 * Called immediately before emit phase.
289 static void arm_finish_irg(ir_graph *irg, arm_code_gen_t *cg) {
290 /* TODO: - fix offsets for nodes accessing stack
297 * These are some hooks which must be filled but are probably not needed.
299 static void arm_before_sched(void *self) {
300 /* Some stuff you need to do after scheduling but before register allocation */
303 static void arm_before_ra(void *self) {
304 /* Some stuff you need to do immediately after register allocation */
309 * Emits the code, closes the output file and frees
310 * the code generator interface.
312 static void arm_emit_and_done(void *self) {
313 arm_code_gen_t *cg = self;
314 ir_graph *irg = cg->irg;
315 FILE *out = cg->isa->out;
317 if (cg->emit_decls) {
322 arm_finish_irg(irg, cg);
323 dump_ir_block_graph_sched(irg, "-arm-finished");
324 arm_gen_routine(out, irg, cg);
328 /* de-allocate code generator */
329 del_set(cg->reg_set);
334 * Move a double floating point value into an integer register.
335 * Place the move operation into block bl.
337 * Handle some special cases here:
338 * 1.) A constant: simply split into two
339 * 2.) A load: siply split into two
341 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
342 ir_node **resH, ir_node **resL) {
344 tarval *tv = get_Const_tarval(arg);
347 /* get the upper 32 bits */
348 v = get_tarval_sub_bits(tv, 7);
349 v = (v << 8) | get_tarval_sub_bits(tv, 6);
350 v = (v << 8) | get_tarval_sub_bits(tv, 5);
351 v = (v << 8) | get_tarval_sub_bits(tv, 4);
352 *resH = new_Const_long(mode_Is, v);
354 /* get the lower 32 bits */
355 v = get_tarval_sub_bits(tv, 3);
356 v = (v << 8) | get_tarval_sub_bits(tv, 2);
357 v = (v << 8) | get_tarval_sub_bits(tv, 1);
358 v = (v << 8) | get_tarval_sub_bits(tv, 0);
359 *resL = new_Const_long(mode_Is, v);
361 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
362 /* FIXME: handling of low/high depends on LE/BE here */
366 ir_graph *irg = current_ir_graph;
369 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
371 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
372 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
373 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
379 * Move a single floating point value into an integer register.
380 * Place the move operation into block bl.
382 * Handle some special cases here:
383 * 1.) A constant: simply move
384 * 2.) A load: siply load
386 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) {
388 tarval *tv = get_Const_tarval(arg);
391 /* get the lower 32 bits */
392 v = get_tarval_sub_bits(tv, 3);
393 v = (v << 8) | get_tarval_sub_bits(tv, 2);
394 v = (v << 8) | get_tarval_sub_bits(tv, 1);
395 v = (v << 8) | get_tarval_sub_bits(tv, 0);
396 return new_Const_long(mode_Is, v);
398 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
401 load = skip_Proj(arg);
408 * Convert the arguments of a call to support the
409 * ARM calling convention of general purpose AND floating
412 static void handle_calls(ir_node *call, void *env)
414 arm_code_gen_t *cg = env;
415 int i, j, n, size, idx, flag, n_param, n_res;
416 ir_type *mtp, *new_mtd, *new_tp[5];
417 ir_node *new_in[5], **in;
423 /* check, if we need conversions */
424 n = get_Call_n_params(call);
425 mtp = get_Call_type(call);
426 assert(get_method_n_params(mtp) == n);
428 /* it's always enough to handle the first 4 parameters */
431 flag = size = idx = 0;
432 bl = get_nodes_block(call);
433 for (i = 0; i < n; ++i) {
434 ir_type *param_tp = get_method_param_type(mtp, i);
436 if (is_compound_type(param_tp)) {
437 /* an aggregate parameter: bad case */
441 /* a primitive parameter */
442 ir_mode *mode = get_type_mode(param_tp);
444 if (mode_is_float(mode)) {
445 if (get_mode_size_bits(mode) > 32) {
446 ir_node *mem = get_Call_mem(call);
448 /* Beware: ARM wants the high part first */
450 new_tp[idx] = cg->int_tp;
451 new_tp[idx+1] = cg->int_tp;
452 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
454 set_Call_mem(call, mem);
458 new_tp[idx] = cg->int_tp;
459 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
466 new_tp[idx] = param_tp;
467 new_in[idx] = get_Call_param(call, i);
476 /* if flag is NOT set, no need to translate the method type */
480 /* construct a new method type */
482 n_param = get_method_n_params(mtp) - n + idx;
483 n_res = get_method_n_ress(mtp);
484 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
486 for (i = 0; i < idx; ++i)
487 set_method_param_type(new_mtd, i, new_tp[i]);
488 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
489 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
490 for (i = 0; i < n_res; ++i)
491 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
493 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
494 set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp));
496 if (is_lowered_type(mtp)) {
497 mtp = get_associated_type(mtp);
499 set_lowered_type(mtp, new_mtd);
501 set_Call_type(call, new_mtd);
503 /* calculate new in array of the Call */
504 NEW_ARR_A(ir_node *, in, n_param + 2);
505 for (i = 0; i < idx; ++i)
506 in[2 + i] = new_in[i];
507 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
508 in[2 + j++] = get_Call_param(call, i);
510 in[0] = get_Call_mem(call);
511 in[1] = get_Call_ptr(call);
513 /* finally, change the call inputs */
514 set_irn_in(call, n_param + 2, in);
518 * Handle graph transformations before the abi converter does its work.
520 static void arm_before_abi(void *self) {
521 arm_code_gen_t *cg = self;
523 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
526 static void *arm_cg_init(const be_irg_t *birg);
528 static const arch_code_generator_if_t arm_code_gen_if = {
530 arm_before_abi, /* before abi introduce */
532 arm_before_sched, /* before scheduling hook */
533 arm_before_ra, /* before register allocation hook */
534 NULL, /* after register allocation */
539 * Initializes the code generator.
541 static void *arm_cg_init(const be_irg_t *birg) {
542 static ir_type *int_tp = NULL;
543 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
547 /* create an integer type with machine size */
548 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
551 cg = xmalloc(sizeof(*cg));
552 cg->impl = &arm_code_gen_if;
554 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
555 cg->arch_env = birg->main_env->arch_env;
561 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
565 if (isa->num_codegens > 1)
570 cur_reg_set = cg->reg_set;
574 /* enter the current code generator */
577 return (arch_code_generator_t *)cg;
582 * Maps all intrinsic calls that the backend support
583 * and map all instructions the backend did not support
586 static void arm_handle_intrinsics(void) {
587 ir_type *tp, *int_tp, *uint_tp;
591 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
593 int_tp = new_type_primitive(ID("int"), mode_Is);
594 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
596 /* ARM has neither a signed div instruction ... */
599 i_instr_record *map_Div = &records[n_records++].i_instr;
601 tp = new_type_method(ID("rt_iDiv"), 2, 1);
602 set_method_param_type(tp, 0, int_tp);
603 set_method_param_type(tp, 1, int_tp);
604 set_method_res_type(tp, 0, int_tp);
606 rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
607 rt_Div.mode = mode_T;
608 rt_Div.mem_proj_nr = pn_Div_M;
609 rt_Div.exc_proj_nr = pn_Div_X_except;
610 rt_Div.exc_mem_proj_nr = pn_Div_M;
611 rt_Div.res_proj_nr = pn_Div_res;
613 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
615 map_Div->kind = INTRINSIC_INSTR;
616 map_Div->op = op_Div;
617 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
618 map_Div->ctx = &rt_Div;
620 /* ... nor a signed div instruction ... */
623 i_instr_record *map_Div = &records[n_records++].i_instr;
625 tp = new_type_method(ID("rt_uDiv"), 2, 1);
626 set_method_param_type(tp, 0, uint_tp);
627 set_method_param_type(tp, 1, uint_tp);
628 set_method_res_type(tp, 0, uint_tp);
630 rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
631 rt_Div.mode = mode_T;
632 rt_Div.mem_proj_nr = pn_Div_M;
633 rt_Div.exc_proj_nr = pn_Div_X_except;
634 rt_Div.exc_mem_proj_nr = pn_Div_M;
635 rt_Div.res_proj_nr = pn_Div_res;
637 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
639 map_Div->kind = INTRINSIC_INSTR;
640 map_Div->op = op_Div;
641 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
642 map_Div->ctx = &rt_Div;
644 /* ... nor a signed mod instruction ... */
647 i_instr_record *map_Mod = &records[n_records++].i_instr;
649 tp = new_type_method(ID("rt_iMod"), 2, 1);
650 set_method_param_type(tp, 0, int_tp);
651 set_method_param_type(tp, 1, int_tp);
652 set_method_res_type(tp, 0, int_tp);
654 rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
655 rt_Mod.mode = mode_T;
656 rt_Mod.mem_proj_nr = pn_Mod_M;
657 rt_Mod.exc_proj_nr = pn_Mod_X_except;
658 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
659 rt_Mod.res_proj_nr = pn_Mod_res;
661 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
663 map_Mod->kind = INTRINSIC_INSTR;
664 map_Mod->op = op_Mod;
665 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
666 map_Mod->ctx = &rt_Mod;
668 /* ... nor a unsigned mod. */
671 i_instr_record *map_Mod = &records[n_records++].i_instr;
673 tp = new_type_method(ID("rt_uMod"), 2, 1);
674 set_method_param_type(tp, 0, uint_tp);
675 set_method_param_type(tp, 1, uint_tp);
676 set_method_res_type(tp, 0, uint_tp);
678 rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
679 rt_Mod.mode = mode_T;
680 rt_Mod.mem_proj_nr = pn_Mod_M;
681 rt_Mod.exc_proj_nr = pn_Mod_X_except;
682 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
683 rt_Mod.res_proj_nr = pn_Mod_res;
685 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
687 map_Mod->kind = INTRINSIC_INSTR;
688 map_Mod->op = op_Mod;
689 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
690 map_Mod->ctx = &rt_Mod;
694 lower_intrinsics(records, n_records);
697 /*****************************************************************
698 * ____ _ _ _____ _____
699 * | _ \ | | | | |_ _|/ ____| /\
700 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
701 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
702 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
703 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
705 *****************************************************************/
707 static arm_isa_t arm_isa_template = {
708 &arm_isa_if, /* isa interface */
709 &arm_gp_regs[REG_SP], /* stack pointer */
710 &arm_gp_regs[REG_R11], /* base pointer */
711 -1, /* stack direction */
712 0, /* number of codegenerator objects */
713 0, /* use generic register names instead of SP, LR, PC */
714 NULL, /* current code generator */
715 NULL, /* output file */
716 ARM_FPU_ARCH_FPE, /* FPU architecture */
720 * Initializes the backend ISA and opens the output file.
722 static void *arm_init(FILE *file_handle) {
723 static int inited = 0;
729 isa = xmalloc(sizeof(*isa));
730 memcpy(isa, &arm_isa_template, sizeof(*isa));
732 arm_register_init(isa);
733 if (isa->gen_reg_names) {
734 /* patch register names */
735 arm_gp_regs[REG_R11].name = "r11";
736 arm_gp_regs[REG_SP].name = "r13";
737 arm_gp_regs[REG_LR].name = "r14";
738 arm_gp_regs[REG_PC].name = "r15";
742 isa->out = file_handle;
744 arm_create_opcodes();
745 arm_handle_intrinsics();
746 arm_switch_section(NULL, NO_SECTION);
755 * frees the ISA structure.
757 static void arm_done(void *self) {
763 * Report the number of register classes.
764 * If we don't have fp instructions, report only GP
765 * here to speed up register allocation (and makes dumps
766 * smaller and more readable).
768 static int arm_get_n_reg_class(const void *self) {
769 const arm_isa_t *isa = self;
771 return isa->cg->have_fp ? 2 : 1;
775 * Return the register class with requested index.
777 static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
778 return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa];
782 * Get the register class which shall be used to store a value of a given mode.
783 * @param self The this pointer.
784 * @param mode The mode in question.
785 * @return A register class which can hold values of the given mode.
787 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
788 if (mode_is_float(mode))
789 return &arm_reg_classes[CLASS_arm_fpa];
791 return &arm_reg_classes[CLASS_arm_gp];
795 * Produces the type which sits between the stack args and the locals on the stack.
796 * it will contain the return address and space to store the old base pointer.
797 * @return The Firm type modelling the ABI between type.
799 static ir_type *arm_get_between_type(void *self) {
800 static ir_type *between_type = NULL;
801 static entity *old_bp_ent = NULL;
804 entity *ret_addr_ent;
805 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
806 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
808 between_type = new_type_class(new_id_from_str("arm_between_type"));
809 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
810 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
812 set_entity_offset_bytes(old_bp_ent, 0);
813 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
814 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
822 be_abi_call_flags_bits_t flags;
823 const arch_env_t *arch_env;
824 const arch_isa_t *isa;
828 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
830 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
831 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
832 env->flags = fl.bits;
834 env->arch_env = arch_env;
835 env->isa = arch_env->isa;
839 static void arm_abi_dont_save_regs(void *self, pset *s)
841 arm_abi_env_t *env = self;
842 if (env->flags.try_omit_fp)
843 pset_insert_ptr(s, env->isa->bp);
849 * Build the ARM prolog
851 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
852 ir_node *keep, *store;
853 arm_abi_env_t *env = self;
854 ir_graph *irg = env->irg;
855 ir_node *block = get_irg_start_block(irg);
856 // ir_node *regs[16];
858 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
859 static const arm_register_req_t *fp_req[] = {
860 &arm_default_req_arm_gp_r11
863 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
864 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
865 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
866 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
867 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
868 // ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]);
869 // ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]);
870 // ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]);
871 // ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]);
873 if(env->flags.try_omit_fp)
876 ip = be_new_Copy(gp, irg, block, sp );
877 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
878 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
880 // if (r0) regs[n_regs++] = r0;
881 // if (r1) regs[n_regs++] = r1;
882 // if (r2) regs[n_regs++] = r2;
883 // if (r3) regs[n_regs++] = r3;
884 // sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
885 // set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
886 // arch_set_irn_register(env->arch_env, sp, env->isa->sp);
887 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
888 set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
889 // arch_set_irn_register(env->arch_env, store, env->isa->sp);
891 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
892 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
893 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
895 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
896 be_node_set_reg_class(keep, 1, gp);
897 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
898 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
900 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
901 new_tarval_from_long(4, get_irn_mode(fp)));
902 set_arm_req_out_all(fp, fp_req);
903 //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
904 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
906 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
907 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
908 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2);
909 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3);
910 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
911 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
912 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
913 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
914 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
919 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
920 arm_abi_env_t *env = self;
921 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
922 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
923 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
924 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
925 static const arm_register_req_t *sub12_req[] = {
926 &arm_default_req_arm_gp_sp
929 // TODO: Activate Omit fp in epilogue
930 if(env->flags.try_omit_fp) {
931 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
933 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
934 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
935 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
936 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
938 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
939 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
940 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
944 tarval *tv = new_tarval_from_long(12,mode_Iu);
945 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
946 set_arm_req_out_all(sub12_node, sub12_req);
947 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
948 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
949 set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
950 set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
951 set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
952 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
953 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
954 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
955 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
956 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
957 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
958 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
960 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
961 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
962 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
963 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
966 static const be_abi_callbacks_t arm_abi_callbacks = {
969 arm_get_between_type,
970 arm_abi_dont_save_regs,
977 * Get the ABI restrictions for procedure calls.
978 * @param self The this pointer.
979 * @param method_type The type of the method (procedure) in question.
980 * @param abi The abi object to be modified
982 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
986 int n = get_method_n_params(method_type);
987 be_abi_call_flags_t flags = {
989 0, /* store from left to right */
990 0, /* store arguments sequential */
991 1, /* try to omit the frame pointer */
992 1, /* the function can use any register as frame pointer */
993 1 /* a call can take the callee's address as an immediate */
997 /* set stack parameter passing style */
998 be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
1000 for (i = 0; i < n; i++) {
1001 /* reg = get reg for param i; */
1002 /* be_abi_call_param_reg(abi, i, reg); */
1005 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1007 be_abi_call_param_stack(abi, i, 4, 0, 0);
1010 /* default: return value is in R0 resp. F0 */
1011 assert(get_method_n_ress(method_type) < 2);
1012 if (get_method_n_ress(method_type) > 0) {
1013 tp = get_method_res_type(method_type, 0);
1014 mode = get_type_mode(tp);
1016 be_abi_call_res_reg(abi, 0,
1017 mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]);
1021 static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1022 return &arm_irn_ops;
1025 const arch_irn_handler_t arm_irn_handler = {
1029 const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
1030 return &arm_irn_handler;
1033 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1034 return is_arm_irn(irn);
1038 * Initializes the code generator interface.
1040 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1041 return &arm_code_gen_if;
1044 list_sched_selector_t arm_sched_selector;
1047 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1049 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self) {
1050 memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1051 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1052 return &arm_sched_selector;
1056 * Returns the necessary byte alignment for storing a register of given class.
1058 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1059 ir_mode *mode = arch_register_class_mode(cls);
1060 return get_mode_size_bytes(mode);
1064 * Returns the libFirm configuration parameter for this backend.
1066 static const backend_params *arm_get_libfirm_params(void) {
1067 static arch_dep_params_t ad = {
1069 0, /* Muls are fast enough on ARM */
1070 31, /* shift would be ok */
1071 0, /* SMUL is needed, only in Arch M*/
1072 0, /* UMUL is needed, only in Arch M */
1073 32, /* SMUL & UMUL available for 32 bit */
1075 static backend_params p = {
1076 NULL, /* no additional opcodes */
1077 NULL, /* will be set later */
1078 1, /* need dword lowering */
1079 NULL, /* but yet no creator function */
1088 /* fpu set architectures. */
1089 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1090 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1091 { "fpe", ARM_FPU_ARCH_FPE },
1092 { "fpa", ARM_FPU_ARCH_FPA },
1093 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1094 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1095 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1099 static lc_opt_enum_int_var_t arch_fpu_var = {
1100 &arm_isa_template.fpu_arch, arm_fpu_items
1103 static const lc_opt_table_entry_t arm_options[] = {
1104 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1105 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1110 * Register command line options for the ARM backend.
1114 * arm-fpuunit=unit select the floating point unit
1115 * arm-gen_reg_names use generic register names instead of SP, LR, PC
1117 static void arm_register_options(lc_opt_entry_t *ent)
1119 lc_opt_entry_t *be_grp_arm = lc_opt_get_grp(ent, "arm");
1120 lc_opt_add_table(be_grp_arm, arm_options);
1122 #endif /* WITH_LIBCORE */
1124 const arch_isa_if_t arm_isa_if = {
1127 arm_get_n_reg_class,
1129 arm_get_reg_class_for_mode,
1131 arm_get_irn_handler,
1132 arm_get_code_generator_if,
1133 arm_get_list_sched_selector,
1134 arm_get_reg_class_alignment,
1135 arm_get_libfirm_params,
1137 arm_register_options