2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist
28 #include "lc_opts_enum.h"
36 #include "iroptimize.h"
38 #include "lower_calls.h"
53 #include "bespillslots.h"
54 #include "bespillutil.h"
56 #include "belistsched.h"
60 #include "bearch_arm_t.h"
62 #include "arm_new_nodes.h"
63 #include "gen_arm_regalloc_if.h"
64 #include "arm_transform.h"
65 #include "arm_optimize.h"
66 #include "arm_emitter.h"
67 #include "arm_map_regs.h"
69 static ir_entity *arm_get_frame_entity(const ir_node *irn)
71 const arm_attr_t *attr = get_arm_attr_const(irn);
73 if (is_arm_FrameAddr(irn)) {
74 const arm_SymConst_attr_t *frame_attr = get_arm_SymConst_attr_const(irn);
75 return frame_attr->entity;
77 if (attr->is_load_store) {
78 const arm_load_store_attr_t *load_store_attr
79 = get_arm_load_store_attr_const(irn);
80 if (load_store_attr->is_frame_entity) {
81 return load_store_attr->entity;
88 * This function is called by the generic backend to correct offsets for
89 * nodes accessing the stack.
91 static void arm_set_stack_bias(ir_node *irn, int bias)
93 if (is_arm_FrameAddr(irn)) {
94 arm_SymConst_attr_t *attr = get_arm_SymConst_attr(irn);
95 attr->fp_offset += bias;
97 arm_load_store_attr_t *attr = get_arm_load_store_attr(irn);
98 assert(attr->base.is_load_store);
103 static int arm_get_sp_bias(const ir_node *irn)
105 /* We don't have any nodes changing the stack pointer.
106 We probably want to support post-/pre increment/decrement later */
111 /* fill register allocator interface */
113 static const arch_irn_ops_t arm_irn_ops = {
114 arm_get_frame_entity,
117 NULL, /* get_inverse */
118 NULL, /* get_op_estimated_cost */
119 NULL, /* possible_memory_operand */
120 NULL, /* perform_memory_operand */
124 * Transforms the standard Firm graph into
127 static void arm_prepare_graph(ir_graph *irg)
129 /* transform nodes into assembler instructions */
130 arm_transform_graph(irg);
132 /* do local optimizations (mainly CSE) */
133 local_optimize_graph(irg);
135 /* do code placement, to optimize the position of constants */
139 static void arm_collect_frame_entity_nodes(ir_node *node, void *data)
141 be_fec_env_t *env = (be_fec_env_t*)data;
145 const arm_load_store_attr_t *attr;
147 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
148 mode = get_irn_mode(node);
149 align = get_mode_size_bytes(mode);
150 be_node_needs_frame_entity(env, node, mode, align);
154 switch (get_arm_irn_opcode(node)) {
162 attr = get_arm_load_store_attr_const(node);
163 entity = attr->entity;
164 mode = attr->load_store_mode;
165 align = get_mode_size_bytes(mode);
168 if (!attr->is_frame_entity)
170 be_node_needs_frame_entity(env, node, mode, align);
173 static void arm_set_frame_entity(ir_node *node, ir_entity *entity)
175 if (is_be_node(node)) {
176 be_node_set_frame_entity(node, entity);
178 arm_load_store_attr_t *attr = get_arm_load_store_attr(node);
179 attr->entity = entity;
183 static void transform_Reload(ir_node *node)
185 ir_node *block = get_nodes_block(node);
186 dbg_info *dbgi = get_irn_dbg_info(node);
187 ir_node *ptr = get_irn_n(node, n_be_Reload_frame);
188 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
189 ir_mode *mode = get_irn_mode(node);
190 ir_entity *entity = be_get_frame_entity(node);
191 const arch_register_t *reg;
195 ir_node *sched_point = sched_prev(node);
197 load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true);
198 sched_add_after(sched_point, load);
201 proj = new_rd_Proj(dbgi, load, mode, pn_arm_Ldr_res);
203 reg = arch_get_irn_register(node);
204 arch_set_irn_register(proj, reg);
206 exchange(node, proj);
209 static void transform_Spill(ir_node *node)
211 ir_node *block = get_nodes_block(node);
212 dbg_info *dbgi = get_irn_dbg_info(node);
213 ir_node *ptr = get_irn_n(node, n_be_Spill_frame);
214 ir_graph *irg = get_irn_irg(node);
215 ir_node *mem = get_irg_no_mem(irg);
216 ir_node *val = get_irn_n(node, n_be_Spill_val);
217 ir_mode *mode = get_irn_mode(val);
218 ir_entity *entity = be_get_frame_entity(node);
219 ir_node *sched_point;
222 sched_point = sched_prev(node);
223 store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0,
227 sched_add_after(sched_point, store);
229 exchange(node, store);
232 static void arm_after_ra_walker(ir_node *block, void *data)
234 ir_node *node, *prev;
237 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
238 prev = sched_prev(node);
240 if (be_is_Reload(node)) {
241 transform_Reload(node);
242 } else if (be_is_Spill(node)) {
243 transform_Spill(node);
249 * Called immediately before emit phase.
251 static void arm_finish_irg(ir_graph *irg)
253 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
254 bool at_begin = stack_layout->sp_relative ? true : false;
255 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
257 irg_walk_graph(irg, NULL, arm_collect_frame_entity_nodes, fec_env);
258 be_assign_entities(fec_env, arm_set_frame_entity, at_begin);
259 be_free_frame_entity_coalescer(fec_env);
261 irg_block_walk_graph(irg, NULL, arm_after_ra_walker, NULL);
263 /* fix stack entity offsets */
264 be_abi_fix_stack_nodes(irg);
265 be_abi_fix_stack_bias(irg);
267 /* do peephole optimizations and fix stack offsets */
268 arm_peephole_optimization(irg);
271 static void arm_before_ra(ir_graph *irg)
273 be_sched_fix_flags(irg, &arm_reg_classes[CLASS_arm_flags], NULL, NULL);
277 * Initializes the code generator.
279 static void arm_init_graph(ir_graph *irg)
286 * Maps all intrinsic calls that the backend support
287 * and map all instructions the backend did not support
290 static void arm_handle_intrinsics(void)
292 ir_type *tp, *int_tp, *uint_tp;
296 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
298 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
300 int_tp = get_type_for_mode(mode_Is);
301 uint_tp = get_type_for_mode(mode_Iu);
303 /* ARM has neither a signed div instruction ... */
305 i_instr_record *map_Div = &records[n_records++].i_instr;
307 tp = new_type_method(2, 1);
308 set_method_param_type(tp, 0, int_tp);
309 set_method_param_type(tp, 1, int_tp);
310 set_method_res_type(tp, 0, int_tp);
312 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
313 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
314 rt_iDiv.mode = mode_T;
315 rt_iDiv.res_mode = mode_Is;
316 rt_iDiv.mem_proj_nr = pn_Div_M;
317 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
318 rt_iDiv.exc_proj_nr = pn_Div_X_except;
319 rt_iDiv.res_proj_nr = pn_Div_res;
321 add_entity_linkage(rt_iDiv.ent, IR_LINKAGE_CONSTANT);
322 set_entity_visibility(rt_iDiv.ent, ir_visibility_external);
324 map_Div->kind = INTRINSIC_INSTR;
325 map_Div->op = op_Div;
326 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
327 map_Div->ctx = &rt_iDiv;
329 /* ... nor an unsigned div instruction ... */
331 i_instr_record *map_Div = &records[n_records++].i_instr;
333 tp = new_type_method(2, 1);
334 set_method_param_type(tp, 0, uint_tp);
335 set_method_param_type(tp, 1, uint_tp);
336 set_method_res_type(tp, 0, uint_tp);
338 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
339 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
340 rt_uDiv.mode = mode_T;
341 rt_uDiv.res_mode = mode_Iu;
342 rt_uDiv.mem_proj_nr = pn_Div_M;
343 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
344 rt_uDiv.exc_proj_nr = pn_Div_X_except;
345 rt_uDiv.res_proj_nr = pn_Div_res;
347 set_entity_visibility(rt_uDiv.ent, ir_visibility_external);
349 map_Div->kind = INTRINSIC_INSTR;
350 map_Div->op = op_Div;
351 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
352 map_Div->ctx = &rt_uDiv;
354 /* ... nor a signed mod instruction ... */
356 i_instr_record *map_Mod = &records[n_records++].i_instr;
358 tp = new_type_method(2, 1);
359 set_method_param_type(tp, 0, int_tp);
360 set_method_param_type(tp, 1, int_tp);
361 set_method_res_type(tp, 0, int_tp);
363 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
364 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
365 rt_iMod.mode = mode_T;
366 rt_iMod.res_mode = mode_Is;
367 rt_iMod.mem_proj_nr = pn_Mod_M;
368 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
369 rt_iMod.exc_proj_nr = pn_Mod_X_except;
370 rt_iMod.res_proj_nr = pn_Mod_res;
372 set_entity_visibility(rt_iMod.ent, ir_visibility_external);
374 map_Mod->kind = INTRINSIC_INSTR;
375 map_Mod->op = op_Mod;
376 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
377 map_Mod->ctx = &rt_iMod;
379 /* ... nor an unsigned mod. */
381 i_instr_record *map_Mod = &records[n_records++].i_instr;
383 tp = new_type_method(2, 1);
384 set_method_param_type(tp, 0, uint_tp);
385 set_method_param_type(tp, 1, uint_tp);
386 set_method_res_type(tp, 0, uint_tp);
388 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
389 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
390 rt_uMod.mode = mode_T;
391 rt_uMod.res_mode = mode_Iu;
392 rt_uMod.mem_proj_nr = pn_Mod_M;
393 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
394 rt_uMod.exc_proj_nr = pn_Mod_X_except;
395 rt_uMod.res_proj_nr = pn_Mod_res;
397 set_entity_visibility(rt_uMod.ent, ir_visibility_external);
399 map_Mod->kind = INTRINSIC_INSTR;
400 map_Mod->op = op_Mod;
401 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
402 map_Mod->ctx = &rt_uMod;
406 lower_intrinsics(records, n_records, /*part_block_used=*/0);
409 extern const arch_isa_if_t arm_isa_if;
410 static arm_isa_t arm_isa_template = {
412 &arm_isa_if, /* isa interface */
417 &arm_registers[REG_SP], /* stack pointer */
418 &arm_registers[REG_R11], /* base pointer */
419 &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */
420 2, /* power of two stack alignment for calls, 2^2 == 4 */
421 NULL, /* main environment */
423 5, /* reload costs */
424 true, /* we do have custom abi handling */
426 ARM_FPU_ARCH_FPE, /* FPU architecture */
429 static void arm_init(void)
433 arm_create_opcodes(&arm_irn_ops);
436 static void arm_finish(void)
441 static arch_env_t *arm_begin_codegeneration(const be_main_env_t *env)
443 arm_isa_t *isa = XMALLOC(arm_isa_t);
444 *isa = arm_isa_template;
446 be_gas_emit_types = false;
448 be_emit_init(env->file_handle);
449 be_gas_begin_compilation_unit(env);
455 * Closes the output file and frees the ISA structure.
457 static void arm_end_codegeneration(void *self)
459 arm_isa_t *isa = (arm_isa_t*)self;
461 be_gas_end_compilation_unit(isa->base.main_env);
468 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
469 * @return 1 if allowed, 0 otherwise
471 static int arm_is_mux_allowed(ir_node *sel, ir_node *mux_false,
480 static asm_constraint_flags_t arm_parse_asm_constraint(const char **c)
482 /* asm not supported */
484 return ASM_CONSTRAINT_FLAG_INVALID;
487 static int arm_is_valid_clobber(const char *clobber)
493 static void arm_lower_for_target(void)
495 size_t i, n_irgs = get_irp_n_irgs();
497 /* lower compound param handling */
498 lower_calls_with_compounds(LF_RETURN_HIDDEN);
500 for (i = 0; i < n_irgs; ++i) {
501 ir_graph *irg = get_irp_irg(i);
502 lower_switch(irg, 4, 256, false);
505 for (i = 0; i < n_irgs; ++i) {
506 ir_graph *irg = get_irp_irg(i);
507 /* Turn all small CopyBs into loads/stores and all bigger CopyBs into
509 * TODO: These constants need arm-specific tuning. */
510 lower_CopyB(irg, 31, 32, false);
515 * Returns the libFirm configuration parameter for this backend.
517 static const backend_params *arm_get_libfirm_params(void)
519 static ir_settings_arch_dep_t ad = {
521 1, /* Muls are fast enough on ARM but ... */
522 31, /* ... one shift would be possible better */
523 NULL, /* no evaluator function */
524 0, /* SMUL is needed, only in Arch M */
525 0, /* UMUL is needed, only in Arch M */
526 32, /* SMUL & UMUL available for 32 bit */
528 static backend_params p = {
529 0, /* don't support inline assembler yet */
530 1, /* support Rotl nodes */
532 1, /* modulo shift efficient */
533 0, /* non-modulo shift not efficient */
534 &ad, /* will be set later */
535 arm_is_mux_allowed, /* allow_ifconv function */
536 32, /* machine size */
537 NULL, /* float arithmetic mode (TODO) */
538 NULL, /* long long type */
539 NULL, /* unsigned long long type */
540 NULL, /* long double type */
541 0, /* no trampoline support: size 0 */
542 0, /* no trampoline support: align 0 */
543 NULL, /* no trampoline support: no trampoline builder */
544 4 /* alignment of stack parameter */
550 /* fpu set architectures. */
551 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
552 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
553 { "fpe", ARM_FPU_ARCH_FPE },
554 { "fpa", ARM_FPU_ARCH_FPA },
555 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
556 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
557 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
561 static lc_opt_enum_int_var_t arch_fpu_var = {
562 &arm_isa_template.fpu_arch, arm_fpu_items
565 static const lc_opt_table_entry_t arm_options[] = {
566 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
570 const arch_isa_if_t arm_isa_if = {
573 arm_get_libfirm_params,
574 arm_lower_for_target,
575 arm_parse_asm_constraint,
576 arm_is_valid_clobber,
578 arm_begin_codegeneration,
579 arm_end_codegeneration,
581 NULL, /* get call abi */
582 NULL, /* mark remat */
583 NULL, /* get_pic_base */
586 NULL, /* register_saved_by */
588 arm_handle_intrinsics, /* handle_intrinsics */
589 NULL, /* before_abi */
596 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm)
597 void be_init_arch_arm(void)
599 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
600 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
602 lc_opt_add_table(arm_grp, arm_options);
604 be_register_isa_if("arm", &arm_isa_if);
606 arm_init_transform();