1 /* The main arm backend driver file. */
8 #include <libcore/lc_opts.h>
9 #include <libcore/lc_opts_enum.h>
11 #include "pseudo_irg.h"
17 #include "lower_intrinsics.h"
22 #include "../bearch.h" /* the general register allocator interface */
23 #include "../benode_t.h"
24 #include "../belower.h"
25 #include "../besched_t.h"
28 #include "../bemachine.h"
29 #include "../beilpsched.h"
30 #include "../bemodule.h"
32 #include "bearch_arm_t.h"
34 #include "arm_new_nodes.h" /* arm nodes interface */
35 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
36 #include "arm_gen_decls.h" /* interface declaration emitter */
37 #include "arm_transform.h"
38 #include "arm_emitter.h"
39 #include "arm_map_regs.h"
41 #define DEBUG_MODULE "firm.be.arm.isa"
43 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
44 static set *cur_reg_set = NULL;
46 /**************************************************
49 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
50 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
51 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
52 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
55 **************************************************/
58 * Return register requirements for a arm node.
59 * If the node returns a tuple (mode_T) then the proj's
60 * will be asked for this information.
63 arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node,
65 long node_pos = pos == -1 ? 0 : pos;
66 ir_mode *mode = get_irn_mode(node);
67 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
69 if (is_Block(node) || mode == mode_X || mode == mode_M) {
70 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", node));
71 return arch_no_register_req;
74 if (mode == mode_T && pos < 0) {
75 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", node));
76 return arch_no_register_req;
79 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, node));
82 /* in case of a proj, we need to get the correct OUT slot */
83 /* of the node corresponding to the proj number */
85 node_pos = arm_translate_proj_pos(node);
91 node = skip_Proj_const(node);
93 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", node, node_pos));
96 /* get requirements for our own nodes */
97 if (is_arm_irn(node)) {
98 const arch_register_req_t *req;
100 req = get_arm_in_req(node, pos);
102 req = get_arm_out_req(node, node_pos);
105 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", node, pos));
109 /* unknown should be tranformed by now */
110 assert(!is_Unknown(node));
111 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", node));
113 return arch_no_register_req;
116 static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
121 if (get_irn_mode(irn) == mode_X) {
125 pos = arm_translate_proj_pos(irn);
126 irn = skip_Proj(irn);
129 if (is_arm_irn(irn)) {
130 const arch_register_t **slots;
132 slots = get_arm_slots(irn);
136 /* here we set the registers for the Phi nodes */
137 arm_set_firm_reg(irn, reg, cur_reg_set);
141 static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) {
143 const arch_register_t *reg = NULL;
147 if (get_irn_mode(irn) == mode_X) {
151 pos = arm_translate_proj_pos(irn);
152 irn = skip_Proj_const(irn);
155 if (is_arm_irn(irn)) {
156 const arch_register_t **slots;
157 slots = get_arm_slots(irn);
161 reg = arm_get_firm_reg(irn, cur_reg_set);
167 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
168 irn = skip_Proj_const(irn);
171 return arch_irn_class_branch;
173 else if (is_arm_irn(irn)) {
174 return arch_irn_class_normal;
180 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
181 irn = skip_Proj_const(irn);
183 if (is_arm_irn(irn)) {
184 return get_arm_flags(irn);
186 else if (is_Unknown(irn)) {
187 return arch_irn_flags_ignore;
193 static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
194 /* TODO: return the entity assigned to the frame */
198 static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
199 /* TODO: set the entity assigned to the frame */
203 * This function is called by the generic backend to correct offsets for
204 * nodes accessing the stack.
206 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
207 /* TODO: correct offset if irn accesses the stack */
210 static int arm_get_sp_bias(const void *self, const ir_node *irn) {
214 /* fill register allocator interface */
216 static const arch_irn_ops_if_t arm_irn_ops_if = {
222 arm_get_frame_entity,
223 arm_set_frame_entity,
226 NULL, /* get_inverse */
227 NULL, /* get_op_estimated_cost */
228 NULL, /* possible_memory_operand */
229 NULL, /* perform_memory_operand */
232 arm_irn_ops_t arm_irn_ops = {
239 /**************************************************
242 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
243 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
244 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
245 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
248 **************************************************/
251 * Transforms the standard Firm graph into
254 static void arm_prepare_graph(void *self) {
255 arm_code_gen_t *cg = self;
257 arm_register_transformers();
258 irg_walk_blkwise_graph(cg->irg, arm_move_consts, arm_transform_node, cg);
264 * Called immediately before emit phase.
266 static void arm_finish_irg(void *self) {
267 /* TODO: - fix offsets for nodes accessing stack
274 * These are some hooks which must be filled but are probably not needed.
276 static void arm_before_sched(void *self) {
277 /* Some stuff you need to do after scheduling but before register allocation */
280 static void arm_before_ra(void *self) {
281 /* Some stuff you need to do immediately after register allocation */
286 * Emits the code, closes the output file and frees
287 * the code generator interface.
289 static void arm_emit_and_done(void *self) {
290 arm_code_gen_t *cg = self;
291 ir_graph *irg = cg->irg;
292 FILE *out = cg->isa->out;
294 if (cg->emit_decls) {
299 dump_ir_block_graph_sched(irg, "-arm-finished");
300 arm_gen_routine(out, irg, cg);
304 /* de-allocate code generator */
305 del_set(cg->reg_set);
310 * Move a double floating point value into an integer register.
311 * Place the move operation into block bl.
313 * Handle some special cases here:
314 * 1.) A constant: simply split into two
315 * 2.) A load: siply split into two
317 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
318 ir_node **resH, ir_node **resL) {
320 tarval *tv = get_Const_tarval(arg);
323 /* get the upper 32 bits */
324 v = get_tarval_sub_bits(tv, 7);
325 v = (v << 8) | get_tarval_sub_bits(tv, 6);
326 v = (v << 8) | get_tarval_sub_bits(tv, 5);
327 v = (v << 8) | get_tarval_sub_bits(tv, 4);
328 *resH = new_Const_long(mode_Is, v);
330 /* get the lower 32 bits */
331 v = get_tarval_sub_bits(tv, 3);
332 v = (v << 8) | get_tarval_sub_bits(tv, 2);
333 v = (v << 8) | get_tarval_sub_bits(tv, 1);
334 v = (v << 8) | get_tarval_sub_bits(tv, 0);
335 *resL = new_Const_long(mode_Is, v);
337 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
338 /* FIXME: handling of low/high depends on LE/BE here */
342 ir_graph *irg = current_ir_graph;
345 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
347 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
348 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
349 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
355 * Move a single floating point value into an integer register.
356 * Place the move operation into block bl.
358 * Handle some special cases here:
359 * 1.) A constant: simply move
360 * 2.) A load: siply load
362 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) {
364 tarval *tv = get_Const_tarval(arg);
367 /* get the lower 32 bits */
368 v = get_tarval_sub_bits(tv, 3);
369 v = (v << 8) | get_tarval_sub_bits(tv, 2);
370 v = (v << 8) | get_tarval_sub_bits(tv, 1);
371 v = (v << 8) | get_tarval_sub_bits(tv, 0);
372 return new_Const_long(mode_Is, v);
374 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
377 load = skip_Proj(arg);
384 * Convert the arguments of a call to support the
385 * ARM calling convention of general purpose AND floating
388 static void handle_calls(ir_node *call, void *env)
390 arm_code_gen_t *cg = env;
391 int i, j, n, size, idx, flag, n_param, n_res;
392 ir_type *mtp, *new_mtd, *new_tp[5];
393 ir_node *new_in[5], **in;
399 /* check, if we need conversions */
400 n = get_Call_n_params(call);
401 mtp = get_Call_type(call);
402 assert(get_method_n_params(mtp) == n);
404 /* it's always enough to handle the first 4 parameters */
407 flag = size = idx = 0;
408 bl = get_nodes_block(call);
409 for (i = 0; i < n; ++i) {
410 ir_type *param_tp = get_method_param_type(mtp, i);
412 if (is_compound_type(param_tp)) {
413 /* an aggregate parameter: bad case */
417 /* a primitive parameter */
418 ir_mode *mode = get_type_mode(param_tp);
420 if (mode_is_float(mode)) {
421 if (get_mode_size_bits(mode) > 32) {
422 ir_node *mem = get_Call_mem(call);
424 /* Beware: ARM wants the high part first */
426 new_tp[idx] = cg->int_tp;
427 new_tp[idx+1] = cg->int_tp;
428 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
430 set_Call_mem(call, mem);
434 new_tp[idx] = cg->int_tp;
435 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
442 new_tp[idx] = param_tp;
443 new_in[idx] = get_Call_param(call, i);
452 /* if flag is NOT set, no need to translate the method type */
456 /* construct a new method type */
458 n_param = get_method_n_params(mtp) - n + idx;
459 n_res = get_method_n_ress(mtp);
460 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
462 for (i = 0; i < idx; ++i)
463 set_method_param_type(new_mtd, i, new_tp[i]);
464 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
465 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
466 for (i = 0; i < n_res; ++i)
467 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
469 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
470 set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp));
472 if (is_lowered_type(mtp)) {
473 mtp = get_associated_type(mtp);
475 set_lowered_type(mtp, new_mtd);
477 set_Call_type(call, new_mtd);
479 /* calculate new in array of the Call */
480 NEW_ARR_A(ir_node *, in, n_param + 2);
481 for (i = 0; i < idx; ++i)
482 in[2 + i] = new_in[i];
483 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
484 in[2 + j++] = get_Call_param(call, i);
486 in[0] = get_Call_mem(call);
487 in[1] = get_Call_ptr(call);
489 /* finally, change the call inputs */
490 set_irn_in(call, n_param + 2, in);
494 * Handle graph transformations before the abi converter does its work.
496 static void arm_before_abi(void *self) {
497 arm_code_gen_t *cg = self;
499 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
502 static void *arm_cg_init(be_irg_t *birg);
504 static const arch_code_generator_if_t arm_code_gen_if = {
506 arm_before_abi, /* before abi introduce */
509 arm_before_sched, /* before scheduling hook */
510 arm_before_ra, /* before register allocation hook */
511 NULL, /* after register allocation */
517 * Initializes the code generator.
519 static void *arm_cg_init(be_irg_t *birg) {
520 static ir_type *int_tp = NULL;
521 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
525 /* create an integer type with machine size */
526 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
529 cg = xmalloc(sizeof(*cg));
530 cg->impl = &arm_code_gen_if;
532 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
533 cg->arch_env = birg->main_env->arch_env;
539 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
543 if (isa->num_codegens > 1)
548 cur_reg_set = cg->reg_set;
552 /* enter the current code generator */
555 return (arch_code_generator_t *)cg;
560 * Maps all intrinsic calls that the backend support
561 * and map all instructions the backend did not support
564 static void arm_handle_intrinsics(void) {
565 ir_type *tp, *int_tp, *uint_tp;
569 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
571 int_tp = new_type_primitive(ID("int"), mode_Is);
572 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
574 /* ARM has neither a signed div instruction ... */
577 i_instr_record *map_Div = &records[n_records++].i_instr;
579 tp = new_type_method(ID("rt_iDiv"), 2, 1);
580 set_method_param_type(tp, 0, int_tp);
581 set_method_param_type(tp, 1, int_tp);
582 set_method_res_type(tp, 0, int_tp);
584 rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
585 rt_Div.mode = mode_T;
586 rt_Div.mem_proj_nr = pn_Div_M;
587 rt_Div.exc_proj_nr = pn_Div_X_except;
588 rt_Div.exc_mem_proj_nr = pn_Div_M;
589 rt_Div.res_proj_nr = pn_Div_res;
591 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
593 map_Div->kind = INTRINSIC_INSTR;
594 map_Div->op = op_Div;
595 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
596 map_Div->ctx = &rt_Div;
598 /* ... nor a signed div instruction ... */
601 i_instr_record *map_Div = &records[n_records++].i_instr;
603 tp = new_type_method(ID("rt_uDiv"), 2, 1);
604 set_method_param_type(tp, 0, uint_tp);
605 set_method_param_type(tp, 1, uint_tp);
606 set_method_res_type(tp, 0, uint_tp);
608 rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
609 rt_Div.mode = mode_T;
610 rt_Div.mem_proj_nr = pn_Div_M;
611 rt_Div.exc_proj_nr = pn_Div_X_except;
612 rt_Div.exc_mem_proj_nr = pn_Div_M;
613 rt_Div.res_proj_nr = pn_Div_res;
615 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
617 map_Div->kind = INTRINSIC_INSTR;
618 map_Div->op = op_Div;
619 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
620 map_Div->ctx = &rt_Div;
622 /* ... nor a signed mod instruction ... */
625 i_instr_record *map_Mod = &records[n_records++].i_instr;
627 tp = new_type_method(ID("rt_iMod"), 2, 1);
628 set_method_param_type(tp, 0, int_tp);
629 set_method_param_type(tp, 1, int_tp);
630 set_method_res_type(tp, 0, int_tp);
632 rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
633 rt_Mod.mode = mode_T;
634 rt_Mod.mem_proj_nr = pn_Mod_M;
635 rt_Mod.exc_proj_nr = pn_Mod_X_except;
636 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
637 rt_Mod.res_proj_nr = pn_Mod_res;
639 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
641 map_Mod->kind = INTRINSIC_INSTR;
642 map_Mod->op = op_Mod;
643 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
644 map_Mod->ctx = &rt_Mod;
646 /* ... nor a unsigned mod. */
649 i_instr_record *map_Mod = &records[n_records++].i_instr;
651 tp = new_type_method(ID("rt_uMod"), 2, 1);
652 set_method_param_type(tp, 0, uint_tp);
653 set_method_param_type(tp, 1, uint_tp);
654 set_method_res_type(tp, 0, uint_tp);
656 rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
657 rt_Mod.mode = mode_T;
658 rt_Mod.mem_proj_nr = pn_Mod_M;
659 rt_Mod.exc_proj_nr = pn_Mod_X_except;
660 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
661 rt_Mod.res_proj_nr = pn_Mod_res;
663 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
665 map_Mod->kind = INTRINSIC_INSTR;
666 map_Mod->op = op_Mod;
667 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
668 map_Mod->ctx = &rt_Mod;
672 lower_intrinsics(records, n_records);
675 /*****************************************************************
676 * ____ _ _ _____ _____
677 * | _ \ | | | | |_ _|/ ____| /\
678 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
679 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
680 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
681 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
683 *****************************************************************/
685 static arm_isa_t arm_isa_template = {
686 &arm_isa_if, /* isa interface */
687 &arm_gp_regs[REG_SP], /* stack pointer */
688 &arm_gp_regs[REG_R11], /* base pointer */
689 -1, /* stack direction */
690 0, /* number of codegenerator objects */
691 0, /* use generic register names instead of SP, LR, PC */
692 NULL, /* current code generator */
693 NULL, /* output file */
694 ARM_FPU_ARCH_FPE, /* FPU architecture */
698 * Initializes the backend ISA and opens the output file.
700 static void *arm_init(FILE *file_handle) {
701 static int inited = 0;
707 isa = xmalloc(sizeof(*isa));
708 memcpy(isa, &arm_isa_template, sizeof(*isa));
710 arm_register_init(isa);
711 if (isa->gen_reg_names) {
712 /* patch register names */
713 arm_gp_regs[REG_R11].name = "r11";
714 arm_gp_regs[REG_SP].name = "r13";
715 arm_gp_regs[REG_LR].name = "r14";
716 arm_gp_regs[REG_PC].name = "r15";
720 isa->out = file_handle;
722 arm_create_opcodes();
723 arm_handle_intrinsics();
724 arm_switch_section(NULL, NO_SECTION);
733 * frees the ISA structure.
735 static void arm_done(void *self) {
741 * Report the number of register classes.
742 * If we don't have fp instructions, report only GP
743 * here to speed up register allocation (and makes dumps
744 * smaller and more readable).
746 static int arm_get_n_reg_class(const void *self) {
747 const arm_isa_t *isa = self;
749 return isa->cg->have_fp ? 2 : 1;
753 * Return the register class with requested index.
755 static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
756 return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa];
760 * Get the register class which shall be used to store a value of a given mode.
761 * @param self The this pointer.
762 * @param mode The mode in question.
763 * @return A register class which can hold values of the given mode.
765 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
766 if (mode_is_float(mode))
767 return &arm_reg_classes[CLASS_arm_fpa];
769 return &arm_reg_classes[CLASS_arm_gp];
773 * Produces the type which sits between the stack args and the locals on the stack.
774 * it will contain the return address and space to store the old base pointer.
775 * @return The Firm type modelling the ABI between type.
777 static ir_type *arm_get_between_type(void *self) {
778 static ir_type *between_type = NULL;
779 static ir_entity *old_bp_ent = NULL;
782 ir_entity *ret_addr_ent;
783 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
784 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
786 between_type = new_type_class(new_id_from_str("arm_between_type"));
787 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
788 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
790 set_entity_offset(old_bp_ent, 0);
791 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
792 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
800 be_abi_call_flags_bits_t flags;
801 const arch_env_t *arch_env;
802 const arch_isa_t *isa;
806 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
808 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
809 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
810 env->flags = fl.bits;
812 env->arch_env = arch_env;
813 env->isa = arch_env->isa;
817 static void arm_abi_dont_save_regs(void *self, pset *s)
819 arm_abi_env_t *env = self;
820 if (env->flags.try_omit_fp)
821 pset_insert_ptr(s, env->isa->bp);
827 * Build the ARM prolog
829 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
830 ir_node *keep, *store;
831 arm_abi_env_t *env = self;
832 ir_graph *irg = env->irg;
833 ir_node *block = get_irg_start_block(irg);
834 // ir_node *regs[16];
836 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
838 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
839 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
840 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
841 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
842 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
843 // ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]);
844 // ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]);
845 // ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]);
846 // ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]);
848 if(env->flags.try_omit_fp)
851 ip = be_new_Copy(gp, irg, block, sp );
852 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
853 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
855 // if (r0) regs[n_regs++] = r0;
856 // if (r1) regs[n_regs++] = r1;
857 // if (r2) regs[n_regs++] = r2;
858 // if (r3) regs[n_regs++] = r3;
859 // sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
860 // set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
861 // arch_set_irn_register(env->arch_env, sp, env->isa->sp);
862 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
864 // set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
865 // arch_set_irn_register(env->arch_env, store, env->isa->sp);
867 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
868 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
869 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
871 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
872 be_node_set_reg_class(keep, 1, gp);
873 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
874 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
876 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
877 new_tarval_from_long(4, get_irn_mode(fp)));
879 //set_arm_req_out_all(fp, fp_req);
880 //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
881 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
883 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
884 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
885 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2);
886 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3);
887 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
888 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
889 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
890 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
891 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
896 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
897 arm_abi_env_t *env = self;
898 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
899 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
900 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
901 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
903 // TODO: Activate Omit fp in epilogue
904 if(env->flags.try_omit_fp) {
905 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
906 add_irn_dep(curr_sp, *mem);
908 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
909 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
910 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
911 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
913 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
914 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
915 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
919 tarval *tv = new_tarval_from_long(12,mode_Iu);
920 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
922 //set_arm_req_out_all(sub12_node, sub12_req);
923 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
924 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
926 //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
927 //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
928 //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
929 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
930 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
931 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
932 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
933 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
934 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
935 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
937 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
938 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
939 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
940 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
943 static const be_abi_callbacks_t arm_abi_callbacks = {
946 arm_get_between_type,
947 arm_abi_dont_save_regs,
954 * Get the ABI restrictions for procedure calls.
955 * @param self The this pointer.
956 * @param method_type The type of the method (procedure) in question.
957 * @param abi The abi object to be modified
959 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
963 int n = get_method_n_params(method_type);
964 be_abi_call_flags_t flags = {
966 0, /* store from left to right */
967 0, /* store arguments sequential */
968 1, /* try to omit the frame pointer */
969 1, /* the function can use any register as frame pointer */
970 1 /* a call can take the callee's address as an immediate */
974 /* set stack parameter passing style */
975 be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
977 for (i = 0; i < n; i++) {
978 /* reg = get reg for param i; */
979 /* be_abi_call_param_reg(abi, i, reg); */
982 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
984 be_abi_call_param_stack(abi, i, 4, 0, 0);
987 /* default: return value is in R0 resp. F0 */
988 assert(get_method_n_ress(method_type) < 2);
989 if (get_method_n_ress(method_type) > 0) {
990 tp = get_method_res_type(method_type, 0);
991 mode = get_type_mode(tp);
993 be_abi_call_res_reg(abi, 0,
994 mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]);
998 static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1002 const arch_irn_handler_t arm_irn_handler = {
1006 const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
1007 return &arm_irn_handler;
1010 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1011 return is_arm_irn(irn);
1015 * Initializes the code generator interface.
1017 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1018 return &arm_code_gen_if;
1021 list_sched_selector_t arm_sched_selector;
1024 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1026 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1027 memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1028 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1029 return &arm_sched_selector;
1032 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
1037 * Returns the necessary byte alignment for storing a register of given class.
1039 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1040 ir_mode *mode = arch_register_class_mode(cls);
1041 return get_mode_size_bytes(mode);
1044 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1050 static const be_machine_t *arm_get_machine(const void *self) {
1057 * Return irp irgs in the desired order.
1059 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
1064 * Returns the libFirm configuration parameter for this backend.
1066 static const backend_params *arm_get_libfirm_params(void) {
1067 static arch_dep_params_t ad = {
1069 0, /* Muls are fast enough on ARM */
1070 31, /* shift would be ok */
1071 0, /* SMUL is needed, only in Arch M*/
1072 0, /* UMUL is needed, only in Arch M */
1073 32, /* SMUL & UMUL available for 32 bit */
1075 static backend_params p = {
1076 NULL, /* no additional opcodes */
1077 NULL, /* will be set later */
1078 1, /* need dword lowering */
1079 NULL, /* but yet no creator function */
1080 NULL, /* context for create_intrinsic_fkt */
1087 /* fpu set architectures. */
1088 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1089 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1090 { "fpe", ARM_FPU_ARCH_FPE },
1091 { "fpa", ARM_FPU_ARCH_FPA },
1092 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1093 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1094 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1098 static lc_opt_enum_int_var_t arch_fpu_var = {
1099 &arm_isa_template.fpu_arch, arm_fpu_items
1102 static const lc_opt_table_entry_t arm_options[] = {
1103 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1104 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1108 const arch_isa_if_t arm_isa_if = {
1111 arm_get_n_reg_class,
1113 arm_get_reg_class_for_mode,
1115 arm_get_irn_handler,
1116 arm_get_code_generator_if,
1117 arm_get_list_sched_selector,
1118 arm_get_ilp_sched_selector,
1119 arm_get_reg_class_alignment,
1120 arm_get_libfirm_params,
1121 arm_get_allowed_execution_units,
1126 void be_init_arch_arm(void)
1128 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1129 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1131 lc_opt_add_table(arm_grp, arm_options);
1133 be_register_isa_if("arm", &arm_isa_if);
1136 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);