2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist
28 #include "lc_opts_enum.h"
36 #include "iroptimize.h"
38 #include "lower_calls.h"
53 #include "bespillslots.h"
54 #include "bespillutil.h"
56 #include "belistsched.h"
60 #include "bearch_arm_t.h"
62 #include "arm_new_nodes.h"
63 #include "gen_arm_regalloc_if.h"
64 #include "arm_transform.h"
65 #include "arm_optimize.h"
66 #include "arm_emitter.h"
67 #include "arm_map_regs.h"
69 static arch_irn_class_t arm_classify(const ir_node *irn)
72 /* TODO: we should mark reload/spill instructions and classify them here */
73 return arch_irn_class_none;
76 static ir_entity *arm_get_frame_entity(const ir_node *irn)
78 const arm_attr_t *attr = get_arm_attr_const(irn);
80 if (is_arm_FrameAddr(irn)) {
81 const arm_SymConst_attr_t *frame_attr = get_arm_SymConst_attr_const(irn);
82 return frame_attr->entity;
84 if (attr->is_load_store) {
85 const arm_load_store_attr_t *load_store_attr
86 = get_arm_load_store_attr_const(irn);
87 if (load_store_attr->is_frame_entity) {
88 return load_store_attr->entity;
95 * This function is called by the generic backend to correct offsets for
96 * nodes accessing the stack.
98 static void arm_set_stack_bias(ir_node *irn, int bias)
100 if (is_arm_FrameAddr(irn)) {
101 arm_SymConst_attr_t *attr = get_arm_SymConst_attr(irn);
102 attr->fp_offset += bias;
104 arm_load_store_attr_t *attr = get_arm_load_store_attr(irn);
105 assert(attr->base.is_load_store);
106 attr->offset += bias;
110 static int arm_get_sp_bias(const ir_node *irn)
112 /* We don't have any nodes changing the stack pointer.
113 We probably want to support post-/pre increment/decrement later */
118 /* fill register allocator interface */
120 static const arch_irn_ops_t arm_irn_ops = {
122 arm_get_frame_entity,
125 NULL, /* get_inverse */
126 NULL, /* get_op_estimated_cost */
127 NULL, /* possible_memory_operand */
128 NULL, /* perform_memory_operand */
132 * Transforms the standard Firm graph into
135 static void arm_prepare_graph(ir_graph *irg)
137 /* transform nodes into assembler instructions */
138 arm_transform_graph(irg);
140 /* do local optimizations (mainly CSE) */
141 local_optimize_graph(irg);
143 /* do code placement, to optimize the position of constants */
147 static void arm_collect_frame_entity_nodes(ir_node *node, void *data)
149 be_fec_env_t *env = (be_fec_env_t*)data;
153 const arm_load_store_attr_t *attr;
155 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
156 mode = get_irn_mode(node);
157 align = get_mode_size_bytes(mode);
158 be_node_needs_frame_entity(env, node, mode, align);
162 switch (get_arm_irn_opcode(node)) {
170 attr = get_arm_load_store_attr_const(node);
171 entity = attr->entity;
172 mode = attr->load_store_mode;
173 align = get_mode_size_bytes(mode);
176 if (!attr->is_frame_entity)
178 be_node_needs_frame_entity(env, node, mode, align);
181 static void arm_set_frame_entity(ir_node *node, ir_entity *entity)
183 if (is_be_node(node)) {
184 be_node_set_frame_entity(node, entity);
186 arm_load_store_attr_t *attr = get_arm_load_store_attr(node);
187 attr->entity = entity;
191 static void transform_Reload(ir_node *node)
193 ir_node *block = get_nodes_block(node);
194 dbg_info *dbgi = get_irn_dbg_info(node);
195 ir_node *ptr = get_irn_n(node, n_be_Reload_frame);
196 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
197 ir_mode *mode = get_irn_mode(node);
198 ir_entity *entity = be_get_frame_entity(node);
199 const arch_register_t *reg;
203 ir_node *sched_point = sched_prev(node);
205 load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true);
206 sched_add_after(sched_point, load);
209 proj = new_rd_Proj(dbgi, load, mode, pn_arm_Ldr_res);
211 reg = arch_get_irn_register(node);
212 arch_set_irn_register(proj, reg);
214 exchange(node, proj);
217 static void transform_Spill(ir_node *node)
219 ir_node *block = get_nodes_block(node);
220 dbg_info *dbgi = get_irn_dbg_info(node);
221 ir_node *ptr = get_irn_n(node, n_be_Spill_frame);
222 ir_graph *irg = get_irn_irg(node);
223 ir_node *mem = get_irg_no_mem(irg);
224 ir_node *val = get_irn_n(node, n_be_Spill_val);
225 ir_mode *mode = get_irn_mode(val);
226 ir_entity *entity = be_get_frame_entity(node);
227 ir_node *sched_point;
230 sched_point = sched_prev(node);
231 store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0,
235 sched_add_after(sched_point, store);
237 exchange(node, store);
240 static void arm_after_ra_walker(ir_node *block, void *data)
242 ir_node *node, *prev;
245 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
246 prev = sched_prev(node);
248 if (be_is_Reload(node)) {
249 transform_Reload(node);
250 } else if (be_is_Spill(node)) {
251 transform_Spill(node);
257 * Called immediately before emit phase.
259 static void arm_finish_irg(ir_graph *irg)
261 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
262 bool at_begin = stack_layout->sp_relative ? true : false;
263 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
265 irg_walk_graph(irg, NULL, arm_collect_frame_entity_nodes, fec_env);
266 be_assign_entities(fec_env, arm_set_frame_entity, at_begin);
267 be_free_frame_entity_coalescer(fec_env);
269 irg_block_walk_graph(irg, NULL, arm_after_ra_walker, NULL);
271 /* fix stack entity offsets */
272 be_abi_fix_stack_nodes(irg);
273 be_abi_fix_stack_bias(irg);
275 /* do peephole optimizations and fix stack offsets */
276 arm_peephole_optimization(irg);
279 static void arm_before_ra(ir_graph *irg)
281 be_sched_fix_flags(irg, &arm_reg_classes[CLASS_arm_flags], NULL, NULL);
285 * Initializes the code generator.
287 static void arm_init_graph(ir_graph *irg)
294 * Maps all intrinsic calls that the backend support
295 * and map all instructions the backend did not support
298 static void arm_handle_intrinsics(void)
300 ir_type *tp, *int_tp, *uint_tp;
304 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
306 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
308 int_tp = get_type_for_mode(mode_Is);
309 uint_tp = get_type_for_mode(mode_Iu);
311 /* ARM has neither a signed div instruction ... */
313 i_instr_record *map_Div = &records[n_records++].i_instr;
315 tp = new_type_method(2, 1);
316 set_method_param_type(tp, 0, int_tp);
317 set_method_param_type(tp, 1, int_tp);
318 set_method_res_type(tp, 0, int_tp);
320 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
321 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
322 rt_iDiv.mode = mode_T;
323 rt_iDiv.res_mode = mode_Is;
324 rt_iDiv.mem_proj_nr = pn_Div_M;
325 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
326 rt_iDiv.exc_proj_nr = pn_Div_X_except;
327 rt_iDiv.res_proj_nr = pn_Div_res;
329 add_entity_linkage(rt_iDiv.ent, IR_LINKAGE_CONSTANT);
330 set_entity_visibility(rt_iDiv.ent, ir_visibility_external);
332 map_Div->kind = INTRINSIC_INSTR;
333 map_Div->op = op_Div;
334 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
335 map_Div->ctx = &rt_iDiv;
337 /* ... nor an unsigned div instruction ... */
339 i_instr_record *map_Div = &records[n_records++].i_instr;
341 tp = new_type_method(2, 1);
342 set_method_param_type(tp, 0, uint_tp);
343 set_method_param_type(tp, 1, uint_tp);
344 set_method_res_type(tp, 0, uint_tp);
346 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
347 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
348 rt_uDiv.mode = mode_T;
349 rt_uDiv.res_mode = mode_Iu;
350 rt_uDiv.mem_proj_nr = pn_Div_M;
351 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
352 rt_uDiv.exc_proj_nr = pn_Div_X_except;
353 rt_uDiv.res_proj_nr = pn_Div_res;
355 set_entity_visibility(rt_uDiv.ent, ir_visibility_external);
357 map_Div->kind = INTRINSIC_INSTR;
358 map_Div->op = op_Div;
359 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
360 map_Div->ctx = &rt_uDiv;
362 /* ... nor a signed mod instruction ... */
364 i_instr_record *map_Mod = &records[n_records++].i_instr;
366 tp = new_type_method(2, 1);
367 set_method_param_type(tp, 0, int_tp);
368 set_method_param_type(tp, 1, int_tp);
369 set_method_res_type(tp, 0, int_tp);
371 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
372 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
373 rt_iMod.mode = mode_T;
374 rt_iMod.res_mode = mode_Is;
375 rt_iMod.mem_proj_nr = pn_Mod_M;
376 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
377 rt_iMod.exc_proj_nr = pn_Mod_X_except;
378 rt_iMod.res_proj_nr = pn_Mod_res;
380 set_entity_visibility(rt_iMod.ent, ir_visibility_external);
382 map_Mod->kind = INTRINSIC_INSTR;
383 map_Mod->op = op_Mod;
384 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
385 map_Mod->ctx = &rt_iMod;
387 /* ... nor an unsigned mod. */
389 i_instr_record *map_Mod = &records[n_records++].i_instr;
391 tp = new_type_method(2, 1);
392 set_method_param_type(tp, 0, uint_tp);
393 set_method_param_type(tp, 1, uint_tp);
394 set_method_res_type(tp, 0, uint_tp);
396 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
397 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
398 rt_uMod.mode = mode_T;
399 rt_uMod.res_mode = mode_Iu;
400 rt_uMod.mem_proj_nr = pn_Mod_M;
401 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
402 rt_uMod.exc_proj_nr = pn_Mod_X_except;
403 rt_uMod.res_proj_nr = pn_Mod_res;
405 set_entity_visibility(rt_uMod.ent, ir_visibility_external);
407 map_Mod->kind = INTRINSIC_INSTR;
408 map_Mod->op = op_Mod;
409 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
410 map_Mod->ctx = &rt_uMod;
414 lower_intrinsics(records, n_records, /*part_block_used=*/0);
417 extern const arch_isa_if_t arm_isa_if;
418 static arm_isa_t arm_isa_template = {
420 &arm_isa_if, /* isa interface */
425 &arm_registers[REG_SP], /* stack pointer */
426 &arm_registers[REG_R11], /* base pointer */
427 &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */
428 2, /* power of two stack alignment for calls, 2^2 == 4 */
429 NULL, /* main environment */
431 5, /* reload costs */
432 true, /* we do have custom abi handling */
434 ARM_FPU_ARCH_FPE, /* FPU architecture */
438 * Initializes the backend ISA and opens the output file.
440 static arch_env_t *arm_init(const be_main_env_t *env)
442 arm_isa_t *isa = XMALLOC(arm_isa_t);
443 *isa = arm_isa_template;
447 arm_create_opcodes(&arm_irn_ops);
448 arm_handle_intrinsics();
450 be_gas_emit_types = false;
452 be_emit_init(env->file_handle);
453 be_gas_begin_compilation_unit(env);
461 * Closes the output file and frees the ISA structure.
463 static void arm_done(void *self)
465 arm_isa_t *isa = (arm_isa_t*)self;
467 be_gas_end_compilation_unit(isa->base.main_env);
474 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
475 * @return 1 if allowed, 0 otherwise
477 static int arm_is_mux_allowed(ir_node *sel, ir_node *mux_false,
486 static asm_constraint_flags_t arm_parse_asm_constraint(const char **c)
488 /* asm not supported */
490 return ASM_CONSTRAINT_FLAG_INVALID;
493 static int arm_is_valid_clobber(const char *clobber)
499 static void arm_lower_for_target(void)
501 size_t i, n_irgs = get_irp_n_irgs();
503 /* lower compound param handling */
504 lower_calls_with_compounds(LF_RETURN_HIDDEN);
506 for (i = 0; i < n_irgs; ++i) {
507 ir_graph *irg = get_irp_irg(i);
508 lower_switch(irg, 4, 256, false);
511 for (i = 0; i < n_irgs; ++i) {
512 ir_graph *irg = get_irp_irg(i);
513 /* Turn all small CopyBs into loads/stores and all bigger CopyBs into
515 * TODO: These constants need arm-specific tuning. */
516 lower_CopyB(irg, 31, 32, false);
521 * Returns the libFirm configuration parameter for this backend.
523 static const backend_params *arm_get_libfirm_params(void)
525 static ir_settings_arch_dep_t ad = {
527 1, /* Muls are fast enough on ARM but ... */
528 31, /* ... one shift would be possible better */
529 NULL, /* no evaluator function */
530 0, /* SMUL is needed, only in Arch M */
531 0, /* UMUL is needed, only in Arch M */
532 32, /* SMUL & UMUL available for 32 bit */
534 static backend_params p = {
535 0, /* don't support inline assembler yet */
536 1, /* support Rotl nodes */
538 1, /* modulo shift efficient */
539 0, /* non-modulo shift not efficient */
540 &ad, /* will be set later */
541 arm_is_mux_allowed, /* allow_ifconv function */
542 32, /* machine size */
543 NULL, /* float arithmetic mode (TODO) */
544 NULL, /* long long type */
545 NULL, /* unsigned long long type */
546 NULL, /* long double type */
547 0, /* no trampoline support: size 0 */
548 0, /* no trampoline support: align 0 */
549 NULL, /* no trampoline support: no trampoline builder */
550 4 /* alignment of stack parameter */
556 /* fpu set architectures. */
557 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
558 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
559 { "fpe", ARM_FPU_ARCH_FPE },
560 { "fpa", ARM_FPU_ARCH_FPA },
561 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
562 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
563 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
567 static lc_opt_enum_int_var_t arch_fpu_var = {
568 &arm_isa_template.fpu_arch, arm_fpu_items
571 static const lc_opt_table_entry_t arm_options[] = {
572 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
576 const arch_isa_if_t arm_isa_if = {
578 arm_lower_for_target,
580 NULL, /* handle_intrinsics */
582 arm_get_libfirm_params,
583 NULL, /* mark remat */
584 arm_parse_asm_constraint,
585 arm_is_valid_clobber,
588 NULL, /* get_pic_base */
589 NULL, /* before_abi */
594 NULL, /* register_saved_by */
599 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm)
600 void be_init_arch_arm(void)
602 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
603 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
605 lc_opt_add_table(arm_grp, arm_options);
607 be_register_isa_if("arm", &arm_isa_if);
609 arm_init_transform();