1 /* The main arm backend driver file. */
8 #include "pseudo_irg.h"
14 #include "lower_intrinsics.h"
19 #include "../bearch.h" /* the general register allocator interface */
20 #include "../benode_t.h"
21 #include "../belower.h"
22 #include "../besched_t.h"
26 #include "bearch_arm_t.h"
28 #include "arm_new_nodes.h" /* arm nodes interface */
29 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
30 #include "arm_gen_decls.h" /* interface declaration emitter */
31 #include "arm_transform.h"
32 #include "arm_emitter.h"
33 #include "arm_map_regs.h"
35 #define DEBUG_MODULE "firm.be.arm.isa"
37 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
38 static set *cur_reg_set = NULL;
40 /**************************************************
43 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
44 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
45 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
46 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
49 **************************************************/
51 static ir_node *my_skip_proj(const ir_node *n) {
58 * Return register requirements for a arm node.
59 * If the node returns a tuple (mode_T) then the proj's
60 * will be asked for this information.
62 static const arch_register_req_t *arm_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
63 const arm_register_req_t *irn_req;
64 long node_pos = pos == -1 ? 0 : pos;
65 ir_mode *mode = get_irn_mode(irn);
66 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
68 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
69 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
73 if (mode == mode_T && pos < 0) {
74 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
78 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
81 /* in case of a proj, we need to get the correct OUT slot */
82 /* of the node corresponding to the proj number */
84 node_pos = arm_translate_proj_pos(irn);
90 irn = my_skip_proj(irn);
92 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
95 /* get requirements for our own nodes */
96 if (is_arm_irn(irn)) {
98 irn_req = get_arm_in_req(irn, pos);
101 irn_req = get_arm_out_req(irn, node_pos);
104 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
106 memcpy(req, &(irn_req->req), sizeof(*req));
108 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
109 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
110 req->other_same = get_irn_n(irn, irn_req->same_pos);
113 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
114 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
115 req->other_different = get_irn_n(irn, irn_req->different_pos);
118 /* get requirements for FIRM nodes */
120 /* treat Phi like Const with default requirements */
122 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
124 if (mode_is_float(mode)) {
125 memcpy(req, &(arm_default_req_arm_fp.req), sizeof(*req));
127 else if (mode_is_int(mode) || mode_is_reference(mode)) {
128 memcpy(req, &(arm_default_req_arm_gp.req), sizeof(*req));
130 else if (mode == mode_T || mode == mode_M) {
131 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
135 assert(0 && "unsupported Phi-Mode");
139 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
147 static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
152 if (get_irn_mode(irn) == mode_X) {
156 pos = arm_translate_proj_pos(irn);
157 irn = my_skip_proj(irn);
160 if (is_arm_irn(irn)) {
161 const arch_register_t **slots;
163 slots = get_arm_slots(irn);
167 /* here we set the registers for the Phi nodes */
168 arm_set_firm_reg(irn, reg, cur_reg_set);
172 static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) {
174 const arch_register_t *reg = NULL;
178 if (get_irn_mode(irn) == mode_X) {
182 pos = arm_translate_proj_pos(irn);
183 irn = my_skip_proj(irn);
186 if (is_arm_irn(irn)) {
187 const arch_register_t **slots;
188 slots = get_arm_slots(irn);
192 reg = arm_get_firm_reg(irn, cur_reg_set);
198 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
199 irn = my_skip_proj(irn);
202 return arch_irn_class_branch;
204 else if (is_arm_irn(irn)) {
205 return arch_irn_class_normal;
211 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
212 irn = my_skip_proj(irn);
214 if (is_arm_irn(irn)) {
215 return get_arm_flags(irn);
217 else if (is_Unknown(irn)) {
218 return arch_irn_flags_ignore;
224 static entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
225 /* TODO: return the entity assigned to the frame */
230 * This function is called by the generic backend to correct offsets for
231 * nodes accessing the stack.
233 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
234 /* TODO: correct offset if irn accesses the stack */
237 /* fill register allocator interface */
239 static const arch_irn_ops_if_t arm_irn_ops_if = {
245 arm_get_frame_entity,
249 arm_irn_ops_t arm_irn_ops = {
256 /**************************************************
259 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
260 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
261 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
262 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
265 **************************************************/
268 * Transforms the standard Firm graph into
271 static void arm_prepare_graph(void *self) {
272 arm_code_gen_t *cg = self;
274 arm_register_transformers();
275 irg_walk_blkwise_graph(cg->irg, arm_move_consts, arm_transform_node, cg);
281 * Called immediately before emit phase.
283 static void arm_finish_irg(ir_graph *irg, arm_code_gen_t *cg) {
284 /* TODO: - fix offsets for nodes accessing stack
291 * These are some hooks which must be filled but are probably not needed.
293 static void arm_before_sched(void *self) {
294 /* Some stuff you need to do after scheduling but before register allocation */
297 static void arm_before_ra(void *self) {
298 /* Some stuff you need to do immediately after register allocation */
303 * Emits the code, closes the output file and frees
304 * the code generator interface.
306 static void arm_emit_and_done(void *self) {
307 arm_code_gen_t *cg = self;
308 ir_graph *irg = cg->irg;
311 if (cg->emit_decls) {
312 arm_gen_decls(cg->out);
316 arm_finish_irg(irg, cg);
317 dump_ir_block_graph_sched(irg, "-arm-finished");
318 arm_gen_routine(out, irg, cg);
322 /* de-allocate code generator */
323 del_set(cg->reg_set);
327 enum convert_which { low, high };
330 * Move an floating point value to a integer register.
331 * Place the move operation into block bl.
333 static ir_node *convert_to_int(ir_node *bl, ir_node *arg, enum convert_which which) {
338 * Convert the arguments of a call to support the
339 * ARM calling convention of general purpose AND floating
342 static void handle_calls(ir_node *call, void *env)
344 arm_code_gen_t *cg = env;
345 int i, j, n, size, idx, flag, n_param, n_res;
346 ir_type *mtp, *new_mtd, *new_tp[5];
347 ir_node *new_in[5], **in;
353 /* check, if we need conversions */
354 n = get_Call_n_params(call);
355 mtp = get_Call_type(call);
356 assert(get_method_n_params(mtp) == n);
358 /* it's always enough to handle the first 4 parameters */
361 flag = size = idx = 0;
362 bl = get_nodes_block(call);
363 for (i = 0; i < n; ++i) {
364 ir_type *param_tp = get_method_param_type(mtp, i);
366 if (is_compound_type(param_tp)) {
367 /* an aggregate parameter: bad case */
371 /* a primitive parameter */
372 ir_mode *mode = get_type_mode(param_tp);
374 if (mode_is_float(mode)) {
375 if (get_mode_size_bits(mode) > 32) {
377 new_tp[idx] = cg->int_tp;
378 new_in[idx] = convert_to_int(bl, get_Call_param(call, i), low);
380 new_tp[idx] = cg->int_tp;
381 new_in[idx] = convert_to_int(bl, get_Call_param(call, i), high);
386 new_tp[idx] = cg->int_tp;
387 new_in[idx] = convert_to_int(bl, get_Call_param(call, i), low);
394 new_tp[idx] = param_tp;
395 new_in[idx] = get_Call_param(call, i);
404 /* if flag is NOT set, no need to translate the method type */
408 /* construct a new method type */
410 n_param = get_method_n_params(mtp) - n + idx;
411 n_res = get_method_n_ress(mtp);
412 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
414 for (i = 0; i < idx; ++i)
415 set_method_param_type(new_mtd, i, new_tp[i]);
416 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
417 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
418 for (i = 0; i < n_res; ++i)
419 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
421 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
422 set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp));
424 if (is_lowered_type(mtp)) {
425 mtp = get_associated_type(mtp);
427 set_lowered_type(mtp, new_mtd);
429 set_Call_type(call, new_mtd);
431 /* calculate new in array of the Call */
432 NEW_ARR_A(ir_node *, in, n_param + 2);
433 for (i = 0; i < idx; ++i)
434 in[2 + i] = new_in[i];
435 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
436 in[2 + j++] = get_Call_param(call, i);
438 in[0] = get_Call_mem(call);
439 in[1] = get_Call_ptr(call);
441 /* finally, change the call inputs */
442 set_irn_in(call, n_param + 2, in);
446 * Handle graph transformations before the abi converter does it's work
448 static void arm_before_abi(void *self) {
449 arm_code_gen_t *cg = self;
451 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
454 static void *arm_cg_init(FILE *F, const be_irg_t *birg);
456 static const arch_code_generator_if_t arm_code_gen_if = {
458 arm_before_abi, /* before abi introduce */
460 arm_before_sched, /* before scheduling hook */
461 arm_before_ra, /* before register allocation hook */
462 NULL, /* after register allocation */
467 * Initializes the code generator.
469 static void *arm_cg_init(FILE *F, const be_irg_t *birg) {
470 static ir_type *int_tp = NULL;
471 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
475 /* create an integer type with machine size */
476 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
479 cg = xmalloc(sizeof(*cg));
480 cg->impl = &arm_code_gen_if;
482 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
484 cg->arch_env = birg->main_env->arch_env;
488 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
492 if (isa->num_codegens > 1)
497 cur_reg_set = cg->reg_set;
501 /* enter the current code generator */
504 return (arch_code_generator_t *)cg;
509 * Maps all intrinsic calls that the backend support
510 * and map all instructions the backend did not support
513 static void arm_global_init(void) {
514 ir_type *tp, *int_tp, *uint_tp;
518 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
520 int_tp = new_type_primitive(ID("int"), mode_Is);
521 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
523 /* ARM has neither a signed div instruction ... */
526 i_instr_record *map_Div = &records[n_records++].i_instr;
528 tp = new_type_method(ID("rt_iDiv"), 2, 1);
529 set_method_param_type(tp, 0, int_tp);
530 set_method_param_type(tp, 1, int_tp);
531 set_method_res_type(tp, 0, int_tp);
533 rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
534 rt_Div.mode = mode_T;
535 rt_Div.mem_proj_nr = pn_Div_M;
536 rt_Div.exc_proj_nr = pn_Div_X_except;
537 rt_Div.exc_mem_proj_nr = pn_Div_M;
538 rt_Div.res_proj_nr = pn_Div_res;
540 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
542 map_Div->kind = INTRINSIC_INSTR;
543 map_Div->op = op_Div;
544 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
545 map_Div->ctx = &rt_Div;
547 /* ... nor a signed div instruction ... */
550 i_instr_record *map_Div = &records[n_records++].i_instr;
552 tp = new_type_method(ID("rt_uDiv"), 2, 1);
553 set_method_param_type(tp, 0, uint_tp);
554 set_method_param_type(tp, 1, uint_tp);
555 set_method_res_type(tp, 0, uint_tp);
557 rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
558 rt_Div.mode = mode_T;
559 rt_Div.mem_proj_nr = pn_Div_M;
560 rt_Div.exc_proj_nr = pn_Div_X_except;
561 rt_Div.exc_mem_proj_nr = pn_Div_M;
562 rt_Div.res_proj_nr = pn_Div_res;
564 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
566 map_Div->kind = INTRINSIC_INSTR;
567 map_Div->op = op_Div;
568 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
569 map_Div->ctx = &rt_Div;
571 /* ... nor a signed mod instruction ... */
574 i_instr_record *map_Mod = &records[n_records++].i_instr;
576 tp = new_type_method(ID("rt_iMod"), 2, 1);
577 set_method_param_type(tp, 0, int_tp);
578 set_method_param_type(tp, 1, int_tp);
579 set_method_res_type(tp, 0, int_tp);
581 rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
582 rt_Mod.mode = mode_T;
583 rt_Mod.mem_proj_nr = pn_Mod_M;
584 rt_Mod.exc_proj_nr = pn_Mod_X_except;
585 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
586 rt_Mod.res_proj_nr = pn_Mod_res;
588 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
590 map_Mod->kind = INTRINSIC_INSTR;
591 map_Mod->op = op_Mod;
592 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
593 map_Mod->ctx = &rt_Mod;
595 /* ... nor a unsigned mod. */
598 i_instr_record *map_Mod = &records[n_records++].i_instr;
600 tp = new_type_method(ID("rt_uMod"), 2, 1);
601 set_method_param_type(tp, 0, uint_tp);
602 set_method_param_type(tp, 1, uint_tp);
603 set_method_res_type(tp, 0, uint_tp);
605 rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
606 rt_Mod.mode = mode_T;
607 rt_Mod.mem_proj_nr = pn_Mod_M;
608 rt_Mod.exc_proj_nr = pn_Mod_X_except;
609 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
610 rt_Mod.res_proj_nr = pn_Mod_res;
612 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
614 map_Mod->kind = INTRINSIC_INSTR;
615 map_Mod->op = op_Mod;
616 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
617 map_Mod->ctx = &rt_Mod;
621 lower_intrinsics(records, n_records);
624 /*****************************************************************
625 * ____ _ _ _____ _____
626 * | _ \ | | | | |_ _|/ ____| /\
627 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
628 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
629 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
630 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
632 *****************************************************************/
634 static arm_isa_t arm_isa_template = {
635 &arm_isa_if, /* isa interface */
636 &arm_gp_regs[REG_SP], /* stack pointer */
637 &arm_gp_regs[REG_R11], /* base pointer */
638 -1, /* stack direction */
639 0, /* number of codegenerator objects */
640 0, /* use generic register names instead of SP, LR, PC */
641 NULL /* current code generator */
645 * Initializes the backend ISA and opens the output file.
647 static void *arm_init(void) {
648 static int inited = 0;
654 isa = xmalloc(sizeof(*isa));
655 memcpy(isa, &arm_isa_template, sizeof(*isa));
657 arm_register_init(isa);
658 if (isa->gen_reg_names) {
659 /* patch register names */
660 arm_gp_regs[REG_R11].name = "r11";
661 arm_gp_regs[REG_SP].name = "r13";
662 arm_gp_regs[REG_LR].name = "r14";
663 arm_gp_regs[REG_PC].name = "r15";
668 arm_create_opcodes();
670 arm_switch_section(NULL, NO_SECTION);
679 * frees the ISA structure.
681 static void arm_done(void *self) {
687 * Report the number of register classes.
688 * If we don't have fp instructions, report only GP
689 * here to speed up register allocation (and makes dumps
690 * smaller and more readable).
692 static int arm_get_n_reg_class(const void *self) {
693 const arm_isa_t *isa = self;
695 return isa->cg->have_fp ? 2 : 1;
699 * Return the register class with requested index.
701 static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
702 return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fp];
706 * Get the register class which shall be used to store a value of a given mode.
707 * @param self The this pointer.
708 * @param mode The mode in question.
709 * @return A register class which can hold values of the given mode.
711 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
712 if (mode_is_float(mode))
713 return &arm_reg_classes[CLASS_arm_fp];
715 return &arm_reg_classes[CLASS_arm_gp];
719 * Produces the type which sits between the stack args and the locals on the stack.
720 * it will contain the return address and space to store the old base pointer.
721 * @return The Firm type modelling the ABI between type.
723 static ir_type *arm_get_between_type(void *self) {
724 static ir_type *between_type = NULL;
725 static entity *old_bp_ent = NULL;
728 entity *ret_addr_ent;
729 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
730 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
732 between_type = new_type_class(new_id_from_str("arm_between_type"));
733 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
734 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
736 set_entity_offset_bytes(old_bp_ent, 0);
737 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
738 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
746 be_abi_call_flags_bits_t flags;
747 const arch_env_t *arch_env;
748 const arch_isa_t *isa;
752 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
754 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
755 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
756 env->flags = fl.bits;
758 env->arch_env = arch_env;
759 env->isa = arch_env->isa;
763 static void arm_abi_dont_save_regs(void *self, pset *s)
765 arm_abi_env_t *env = self;
766 if(env->flags.try_omit_fp)
767 pset_insert_ptr(s, env->isa->bp);
773 * Build the ARM prolog
775 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
776 ir_node *keep, *store;
777 arm_abi_env_t *env = self;
778 ir_graph *irg = env->irg;
779 ir_node *block = get_irg_start_block(irg);
780 // ir_node *regs[16];
782 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
783 static const arm_register_req_t *fp_req[] = {
784 &arm_default_req_arm_gp_r11
787 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
788 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
789 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
790 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
791 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
792 // ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]);
793 // ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]);
794 // ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]);
795 // ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]);
797 if(env->flags.try_omit_fp)
800 ip = be_new_Copy(gp, irg, block, sp );
801 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
802 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
804 // if (r0) regs[n_regs++] = r0;
805 // if (r1) regs[n_regs++] = r1;
806 // if (r2) regs[n_regs++] = r2;
807 // if (r3) regs[n_regs++] = r3;
808 // sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
809 // set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
810 // arch_set_irn_register(env->arch_env, sp, env->isa->sp);
811 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem, mode_T);
812 set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
813 // arch_set_irn_register(env->arch_env, store, env->isa->sp);
815 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, 0);
816 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
817 *mem = new_r_Proj(irg, block, store, mode_M, 1);
819 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
820 be_node_set_reg_class(keep, 1, gp);
821 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
822 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
824 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
825 new_tarval_from_long(4, get_irn_mode(fp)));
826 set_arm_req_out_all(fp, fp_req);
827 //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
828 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
830 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
831 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
832 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2);
833 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3);
834 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
835 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
836 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
837 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
838 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
843 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
844 arm_abi_env_t *env = self;
845 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
846 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
847 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
848 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
849 static const arm_register_req_t *sub12_req[] = {
850 &arm_default_req_arm_gp_sp
853 // TODO: Activate Omit fp in epilogue
854 if(env->flags.try_omit_fp) {
855 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
857 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
858 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
859 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
860 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
862 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
863 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
864 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
868 tarval *tv = new_tarval_from_long(12,mode_Iu);
869 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
870 set_arm_req_out_all(sub12_node, sub12_req);
871 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
872 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem, mode_T );
873 set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
874 set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
875 set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
876 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, 0);
877 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, 1);
878 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, 2);
879 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, 3);
880 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
881 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
882 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
884 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
885 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
886 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
887 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
890 static const be_abi_callbacks_t arm_abi_callbacks = {
893 arm_get_between_type,
894 arm_abi_dont_save_regs,
901 * Get the ABI restrictions for procedure calls.
902 * @param self The this pointer.
903 * @param method_type The type of the method (procedure) in question.
904 * @param abi The abi object to be modified
906 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
910 int n = get_method_n_params(method_type);
911 be_abi_call_flags_t flags = {
913 0, /* store from left to right */
914 0, /* store arguments sequential */
915 1, /* try to omit the frame pointer */
916 1, /* the function can use any register as frame pointer */
917 1 /* a call can take the callee's address as an immediate */
921 /* set stack parameter passing style */
922 be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
924 for (i = 0; i < n; i++) {
925 /* reg = get reg for param i; */
926 /* be_abi_call_param_reg(abi, i, reg); */
929 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
931 be_abi_call_param_stack(abi, i, 4, 0, 0);
934 /* default: return value is in R0 resp. F0 */
935 assert(get_method_n_ress(method_type) < 2);
936 if (get_method_n_ress(method_type) > 0) {
937 tp = get_method_res_type(method_type, 0);
938 mode = get_type_mode(tp);
940 be_abi_call_res_reg(abi, 0,
941 mode_is_float(mode) ? &arm_fp_regs[REG_F0] : &arm_gp_regs[REG_R0]);
945 static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
949 const arch_irn_handler_t arm_irn_handler = {
953 const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
954 return &arm_irn_handler;
957 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
958 return is_arm_irn(irn);
962 * Initializes the code generator interface.
964 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
965 return &arm_code_gen_if;
968 list_sched_selector_t arm_sched_selector;
971 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
973 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self) {
974 memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
975 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
976 return &arm_sched_selector;
980 * Returns the necessary byte alignment for storing a register of given class.
982 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
983 ir_mode *mode = arch_register_class_mode(cls);
984 return get_mode_size_bytes(mode);
988 static const lc_opt_table_entry_t arm_options[] = {
989 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
994 * Register command line options for the ARM backend.
998 * arm-gen_reg_names use generic register names instead of SP, LR, PC
1000 static void arm_register_options(lc_opt_entry_t *ent)
1002 lc_opt_entry_t *be_grp_arm = lc_opt_get_grp(ent, "arm");
1003 lc_opt_add_table(be_grp_arm, arm_options);
1005 #endif /* WITH_LIBCORE */
1007 const arch_isa_if_t arm_isa_if = {
1010 arm_get_n_reg_class,
1012 arm_get_reg_class_for_mode,
1014 arm_get_irn_handler,
1015 arm_get_code_generator_if,
1016 arm_get_list_sched_selector,
1017 arm_get_reg_class_alignment,
1019 arm_register_options