2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Oliver Richter, Tobias Gneist
30 #include <libcore/lc_opts.h>
31 #include <libcore/lc_opts_enum.h>
33 #include "pseudo_irg.h"
44 #include "../bearch_t.h" /* the general register allocator interface */
45 #include "../benode_t.h"
46 #include "../belower.h"
47 #include "../besched_t.h"
50 #include "../bemachine.h"
51 #include "../beilpsched.h"
52 #include "../bemodule.h"
53 #include "../beirg_t.h"
54 #include "../bespillslots.h"
55 #include "../begnuas.h"
57 #include "bearch_arm_t.h"
59 #include "arm_new_nodes.h" /* arm nodes interface */
60 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
61 #include "arm_transform.h"
62 #include "arm_emitter.h"
63 #include "arm_map_regs.h"
65 #define DEBUG_MODULE "firm.be.arm.isa"
67 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
68 static set *cur_reg_set = NULL;
70 /**************************************************
73 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
74 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
75 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
76 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
79 **************************************************/
82 * Return register requirements for a arm node.
83 * If the node returns a tuple (mode_T) then the proj's
84 * will be asked for this information.
87 arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node,
89 long node_pos = pos == -1 ? 0 : pos;
90 ir_mode *mode = get_irn_mode(node);
91 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
93 if (is_Block(node) || mode == mode_X || mode == mode_M) {
94 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", node));
95 return arch_no_register_req;
98 if (mode == mode_T && pos < 0) {
99 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", node));
100 return arch_no_register_req;
103 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, node));
106 /* in case of a proj, we need to get the correct OUT slot */
107 /* of the node corresponding to the proj number */
109 node_pos = arm_translate_proj_pos(node);
115 node = skip_Proj_const(node);
117 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", node, node_pos));
120 /* get requirements for our own nodes */
121 if (is_arm_irn(node)) {
122 const arch_register_req_t *req;
124 req = get_arm_in_req(node, pos);
126 req = get_arm_out_req(node, node_pos);
129 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", node, pos));
133 /* unknown should be tranformed by now */
134 assert(!is_Unknown(node));
135 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", node));
137 return arch_no_register_req;
140 static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
145 if (get_irn_mode(irn) == mode_X) {
149 pos = arm_translate_proj_pos(irn);
150 irn = skip_Proj(irn);
153 if (is_arm_irn(irn)) {
154 const arch_register_t **slots;
156 slots = get_arm_slots(irn);
160 /* here we set the registers for the Phi nodes */
161 arm_set_firm_reg(irn, reg, cur_reg_set);
165 static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) {
167 const arch_register_t *reg = NULL;
171 if (get_irn_mode(irn) == mode_X) {
175 pos = arm_translate_proj_pos(irn);
176 irn = skip_Proj_const(irn);
179 if (is_arm_irn(irn)) {
180 const arch_register_t **slots;
181 slots = get_arm_slots(irn);
185 reg = arm_get_firm_reg(irn, cur_reg_set);
191 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
192 irn = skip_Proj_const(irn);
195 return arch_irn_class_branch;
197 else if (is_arm_irn(irn)) {
198 return arch_irn_class_normal;
204 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
205 irn = skip_Proj_const(irn);
207 if (is_arm_irn(irn)) {
208 return get_arm_flags(irn);
210 else if (is_Unknown(irn)) {
211 return arch_irn_flags_ignore;
217 static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
218 /* TODO: return the entity assigned to the frame */
222 static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
223 /* TODO: set the entity assigned to the frame */
227 * This function is called by the generic backend to correct offsets for
228 * nodes accessing the stack.
230 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
231 /* TODO: correct offset if irn accesses the stack */
234 static int arm_get_sp_bias(const void *self, const ir_node *irn) {
238 /* fill register allocator interface */
240 static const arch_irn_ops_if_t arm_irn_ops_if = {
246 arm_get_frame_entity,
247 arm_set_frame_entity,
250 NULL, /* get_inverse */
251 NULL, /* get_op_estimated_cost */
252 NULL, /* possible_memory_operand */
253 NULL, /* perform_memory_operand */
256 arm_irn_ops_t arm_irn_ops = {
263 /**************************************************
266 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
267 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
268 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
269 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
272 **************************************************/
275 * Transforms the standard Firm graph into
278 static void arm_prepare_graph(void *self) {
279 arm_code_gen_t *cg = self;
281 arm_register_transformers();
282 irg_walk_blkwise_graph(cg->irg, arm_move_consts, arm_transform_node, cg);
288 * Called immediately before emit phase.
290 static void arm_finish_irg(void *self) {
291 /* TODO: - fix offsets for nodes accessing stack
298 * These are some hooks which must be filled but are probably not needed.
300 static void arm_before_sched(void *self) {
301 /* Some stuff you need to do after scheduling but before register allocation */
304 static void arm_before_ra(void *self) {
305 /* Some stuff you need to do immediately after register allocation */
309 * We transform Spill and Reload here. This needs to be done before
310 * stack biasing otherwise we would miss the corrected offset for these nodes.
312 static void arm_after_ra(void *self) {
313 arm_code_gen_t *cg = self;
314 be_coalesce_spillslots(cg->birg);
318 * Emits the code, closes the output file and frees
319 * the code generator interface.
321 static void arm_emit_and_done(void *self) {
322 arm_code_gen_t *cg = self;
323 ir_graph *irg = cg->irg;
325 arm_gen_routine(cg, irg);
329 /* de-allocate code generator */
330 del_set(cg->reg_set);
335 * Move a double floating point value into an integer register.
336 * Place the move operation into block bl.
338 * Handle some special cases here:
339 * 1.) A constant: simply split into two
340 * 2.) A load: simply split into two
342 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
343 ir_node **resH, ir_node **resL) {
345 tarval *tv = get_Const_tarval(arg);
348 /* get the upper 32 bits */
349 v = get_tarval_sub_bits(tv, 7);
350 v = (v << 8) | get_tarval_sub_bits(tv, 6);
351 v = (v << 8) | get_tarval_sub_bits(tv, 5);
352 v = (v << 8) | get_tarval_sub_bits(tv, 4);
353 *resH = new_Const_long(mode_Is, v);
355 /* get the lower 32 bits */
356 v = get_tarval_sub_bits(tv, 3);
357 v = (v << 8) | get_tarval_sub_bits(tv, 2);
358 v = (v << 8) | get_tarval_sub_bits(tv, 1);
359 v = (v << 8) | get_tarval_sub_bits(tv, 0);
360 *resL = new_Const_long(mode_Is, v);
362 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
363 /* FIXME: handling of low/high depends on LE/BE here */
367 ir_graph *irg = current_ir_graph;
370 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
372 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
373 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
374 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
380 * Move a single floating point value into an integer register.
381 * Place the move operation into block bl.
383 * Handle some special cases here:
384 * 1.) A constant: simply move
385 * 2.) A load: simply load
387 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) {
389 tarval *tv = get_Const_tarval(arg);
392 /* get the lower 32 bits */
393 v = get_tarval_sub_bits(tv, 3);
394 v = (v << 8) | get_tarval_sub_bits(tv, 2);
395 v = (v << 8) | get_tarval_sub_bits(tv, 1);
396 v = (v << 8) | get_tarval_sub_bits(tv, 0);
397 return new_Const_long(mode_Is, v);
399 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
402 load = skip_Proj(arg);
409 * Convert the arguments of a call to support the
410 * ARM calling convention of general purpose AND floating
413 static void handle_calls(ir_node *call, void *env)
415 arm_code_gen_t *cg = env;
416 int i, j, n, size, idx, flag, n_param, n_res;
417 ir_type *mtp, *new_mtd, *new_tp[5];
418 ir_node *new_in[5], **in;
424 /* check, if we need conversions */
425 n = get_Call_n_params(call);
426 mtp = get_Call_type(call);
427 assert(get_method_n_params(mtp) == n);
429 /* it's always enough to handle the first 4 parameters */
432 flag = size = idx = 0;
433 bl = get_nodes_block(call);
434 for (i = 0; i < n; ++i) {
435 ir_type *param_tp = get_method_param_type(mtp, i);
437 if (is_compound_type(param_tp)) {
438 /* an aggregate parameter: bad case */
442 /* a primitive parameter */
443 ir_mode *mode = get_type_mode(param_tp);
445 if (mode_is_float(mode)) {
446 if (get_mode_size_bits(mode) > 32) {
447 ir_node *mem = get_Call_mem(call);
449 /* Beware: ARM wants the high part first */
451 new_tp[idx] = cg->int_tp;
452 new_tp[idx+1] = cg->int_tp;
453 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
455 set_Call_mem(call, mem);
459 new_tp[idx] = cg->int_tp;
460 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
467 new_tp[idx] = param_tp;
468 new_in[idx] = get_Call_param(call, i);
477 /* if flag is NOT set, no need to translate the method type */
481 /* construct a new method type */
483 n_param = get_method_n_params(mtp) - n + idx;
484 n_res = get_method_n_ress(mtp);
485 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
487 for (i = 0; i < idx; ++i)
488 set_method_param_type(new_mtd, i, new_tp[i]);
489 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
490 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
491 for (i = 0; i < n_res; ++i)
492 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
494 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
495 set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp));
497 if (is_lowered_type(mtp)) {
498 mtp = get_associated_type(mtp);
500 set_lowered_type(mtp, new_mtd);
502 set_Call_type(call, new_mtd);
504 /* calculate new in array of the Call */
505 NEW_ARR_A(ir_node *, in, n_param + 2);
506 for (i = 0; i < idx; ++i)
507 in[2 + i] = new_in[i];
508 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
509 in[2 + j++] = get_Call_param(call, i);
511 in[0] = get_Call_mem(call);
512 in[1] = get_Call_ptr(call);
514 /* finally, change the call inputs */
515 set_irn_in(call, n_param + 2, in);
519 * Handle graph transformations before the abi converter does its work.
521 static void arm_before_abi(void *self) {
522 arm_code_gen_t *cg = self;
524 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
527 static void *arm_cg_init(be_irg_t *birg);
529 static const arch_code_generator_if_t arm_code_gen_if = {
531 arm_before_abi, /* before abi introduce */
534 arm_before_sched, /* before scheduling hook */
535 arm_before_ra, /* before register allocation hook */
542 * Initializes the code generator.
544 static void *arm_cg_init(be_irg_t *birg) {
545 static ir_type *int_tp = NULL;
546 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
550 /* create an integer type with machine size */
551 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
554 cg = xmalloc(sizeof(*cg));
555 cg->impl = &arm_code_gen_if;
557 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
558 cg->arch_env = birg->main_env->arch_env;
564 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
566 cur_reg_set = cg->reg_set;
570 /* enter the current code generator */
573 return (arch_code_generator_t *)cg;
578 * Maps all intrinsic calls that the backend support
579 * and map all instructions the backend did not support
582 static void arm_handle_intrinsics(void) {
583 ir_type *tp, *int_tp, *uint_tp;
587 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
589 int_tp = new_type_primitive(ID("int"), mode_Is);
590 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
592 /* ARM has neither a signed div instruction ... */
595 i_instr_record *map_Div = &records[n_records++].i_instr;
597 tp = new_type_method(ID("rt_iDiv"), 2, 1);
598 set_method_param_type(tp, 0, int_tp);
599 set_method_param_type(tp, 1, int_tp);
600 set_method_res_type(tp, 0, int_tp);
602 rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
603 rt_Div.mode = mode_T;
604 rt_Div.res_mode = mode_Is;
605 rt_Div.mem_proj_nr = pn_Div_M;
606 rt_Div.regular_proj_nr = pn_Div_X_regular;
607 rt_Div.exc_proj_nr = pn_Div_X_except;
608 rt_Div.exc_mem_proj_nr = pn_Div_M;
609 rt_Div.res_proj_nr = pn_Div_res;
611 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
613 map_Div->kind = INTRINSIC_INSTR;
614 map_Div->op = op_Div;
615 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
616 map_Div->ctx = &rt_Div;
618 /* ... nor an unsigned div instruction ... */
621 i_instr_record *map_Div = &records[n_records++].i_instr;
623 tp = new_type_method(ID("rt_uDiv"), 2, 1);
624 set_method_param_type(tp, 0, uint_tp);
625 set_method_param_type(tp, 1, uint_tp);
626 set_method_res_type(tp, 0, uint_tp);
628 rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
629 rt_Div.mode = mode_T;
630 rt_Div.res_mode = mode_Iu;
631 rt_Div.mem_proj_nr = pn_Div_M;
632 rt_Div.regular_proj_nr = pn_Div_X_regular;
633 rt_Div.exc_proj_nr = pn_Div_X_except;
634 rt_Div.exc_mem_proj_nr = pn_Div_M;
635 rt_Div.res_proj_nr = pn_Div_res;
637 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
639 map_Div->kind = INTRINSIC_INSTR;
640 map_Div->op = op_Div;
641 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
642 map_Div->ctx = &rt_Div;
644 /* ... nor a signed mod instruction ... */
647 i_instr_record *map_Mod = &records[n_records++].i_instr;
649 tp = new_type_method(ID("rt_iMod"), 2, 1);
650 set_method_param_type(tp, 0, int_tp);
651 set_method_param_type(tp, 1, int_tp);
652 set_method_res_type(tp, 0, int_tp);
654 rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
655 rt_Mod.mode = mode_T;
656 rt_Mod.res_mode = mode_Is;
657 rt_Mod.mem_proj_nr = pn_Mod_M;
658 rt_Mod.regular_proj_nr = pn_Mod_X_regular;
659 rt_Mod.exc_proj_nr = pn_Mod_X_except;
660 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
661 rt_Mod.res_proj_nr = pn_Mod_res;
663 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
665 map_Mod->kind = INTRINSIC_INSTR;
666 map_Mod->op = op_Mod;
667 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
668 map_Mod->ctx = &rt_Mod;
670 /* ... nor an unsigned mod. */
673 i_instr_record *map_Mod = &records[n_records++].i_instr;
675 tp = new_type_method(ID("rt_uMod"), 2, 1);
676 set_method_param_type(tp, 0, uint_tp);
677 set_method_param_type(tp, 1, uint_tp);
678 set_method_res_type(tp, 0, uint_tp);
680 rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
681 rt_Mod.mode = mode_T;
682 rt_Mod.res_mode = mode_Iu;
683 rt_Mod.mem_proj_nr = pn_Mod_M;
684 rt_Mod.regular_proj_nr = pn_Mod_X_regular;
685 rt_Mod.exc_proj_nr = pn_Mod_X_except;
686 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
687 rt_Mod.res_proj_nr = pn_Mod_res;
689 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
691 map_Mod->kind = INTRINSIC_INSTR;
692 map_Mod->op = op_Mod;
693 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
694 map_Mod->ctx = &rt_Mod;
698 lower_intrinsics(records, n_records);
701 /*****************************************************************
702 * ____ _ _ _____ _____
703 * | _ \ | | | | |_ _|/ ____| /\
704 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
705 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
706 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
707 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
709 *****************************************************************/
711 static arm_isa_t arm_isa_template = {
713 &arm_isa_if, /* isa interface */
714 &arm_gp_regs[REG_SP], /* stack pointer */
715 &arm_gp_regs[REG_R11], /* base pointer */
716 -1, /* stack direction */
717 NULL, /* main environment */
719 5, /* reload costs */
721 0, /* use generic register names instead of SP, LR, PC */
722 ARM_FPU_ARCH_FPE, /* FPU architecture */
723 NULL, /* current code generator */
724 { NULL, }, /* emitter environment */
728 * Initializes the backend ISA and opens the output file.
730 static void *arm_init(FILE *file_handle) {
731 static int inited = 0;
737 isa = xmalloc(sizeof(*isa));
738 memcpy(isa, &arm_isa_template, sizeof(*isa));
740 arm_register_init(isa);
743 be_emit_init_env(&isa->emit, file_handle);
745 arm_create_opcodes();
746 arm_handle_intrinsics();
748 /* we mark referenced global entities, so we can only emit those which
749 * are actually referenced. (Note: you mustn't use the type visited flag
750 * elsewhere in the backend)
752 inc_master_type_visited();
761 * Closes the output file and frees the ISA structure.
763 static void arm_done(void *self) {
764 arm_isa_t *isa = self;
766 be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
768 be_emit_destroy_env(&isa->emit);
774 * Report the number of register classes.
775 * If we don't have fp instructions, report only GP
776 * here to speed up register allocation (and makes dumps
777 * smaller and more readable).
779 static int arm_get_n_reg_class(const void *self) {
780 const arm_isa_t *isa = self;
782 return isa->cg->have_fp ? 2 : 1;
786 * Return the register class with requested index.
788 static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
789 return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa];
793 * Get the register class which shall be used to store a value of a given mode.
794 * @param self The this pointer.
795 * @param mode The mode in question.
796 * @return A register class which can hold values of the given mode.
798 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
799 if (mode_is_float(mode))
800 return &arm_reg_classes[CLASS_arm_fpa];
802 return &arm_reg_classes[CLASS_arm_gp];
806 * Produces the type which sits between the stack args and the locals on the stack.
807 * it will contain the return address and space to store the old base pointer.
808 * @return The Firm type modelling the ABI between type.
810 static ir_type *arm_get_between_type(void *self) {
811 static ir_type *between_type = NULL;
812 static ir_entity *old_bp_ent = NULL;
815 ir_entity *ret_addr_ent;
816 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
817 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
819 between_type = new_type_class(new_id_from_str("arm_between_type"));
820 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
821 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
823 set_entity_offset(old_bp_ent, 0);
824 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
825 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
833 be_abi_call_flags_bits_t flags;
834 const arch_env_t *arch_env;
835 const arch_isa_t *isa;
839 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
841 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
842 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
843 env->flags = fl.bits;
845 env->arch_env = arch_env;
846 env->isa = arch_env->isa;
850 static void arm_abi_dont_save_regs(void *self, pset *s)
852 arm_abi_env_t *env = self;
853 if (env->flags.try_omit_fp)
854 pset_insert_ptr(s, env->isa->bp);
860 * Build the ARM prolog
862 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
863 ir_node *keep, *store;
864 arm_abi_env_t *env = self;
865 ir_graph *irg = env->irg;
866 ir_node *block = get_irg_start_block(irg);
867 // ir_node *regs[16];
869 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
871 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
872 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
873 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
874 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
875 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
876 // ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]);
877 // ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]);
878 // ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]);
879 // ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]);
881 if(env->flags.try_omit_fp)
884 ip = be_new_Copy(gp, irg, block, sp );
885 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
886 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
888 // if (r0) regs[n_regs++] = r0;
889 // if (r1) regs[n_regs++] = r1;
890 // if (r2) regs[n_regs++] = r2;
891 // if (r3) regs[n_regs++] = r3;
892 // sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
893 // set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
894 // arch_set_irn_register(env->arch_env, sp, env->isa->sp);
895 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
897 // set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
898 // arch_set_irn_register(env->arch_env, store, env->isa->sp);
900 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
901 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
902 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
904 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
905 be_node_set_reg_class(keep, 1, gp);
906 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
907 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
909 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
910 new_tarval_from_long(4, get_irn_mode(fp)));
912 //set_arm_req_out_all(fp, fp_req);
913 //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
914 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
916 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
917 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
918 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2);
919 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3);
920 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
921 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
922 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
923 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
924 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
929 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
930 arm_abi_env_t *env = self;
931 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
932 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
933 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
934 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
936 // TODO: Activate Omit fp in epilogue
937 if(env->flags.try_omit_fp) {
938 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
939 add_irn_dep(curr_sp, *mem);
941 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
942 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
943 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
944 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
946 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
947 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
948 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
949 be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
953 tarval *tv = new_tarval_from_long(12,mode_Iu);
954 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
956 //set_arm_req_out_all(sub12_node, sub12_req);
957 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
958 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
960 //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
961 //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
962 //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
963 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
964 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
965 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
966 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
967 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
968 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
969 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
971 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
972 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
973 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
974 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
977 static const be_abi_callbacks_t arm_abi_callbacks = {
980 arm_get_between_type,
981 arm_abi_dont_save_regs,
988 * Get the ABI restrictions for procedure calls.
989 * @param self The this pointer.
990 * @param method_type The type of the method (procedure) in question.
991 * @param abi The abi object to be modified
993 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
997 int n = get_method_n_params(method_type);
998 be_abi_call_flags_t flags = {
1000 0, /* store from left to right */
1001 0, /* store arguments sequential */
1002 1, /* try to omit the frame pointer */
1003 1, /* the function can use any register as frame pointer */
1004 1 /* a call can take the callee's address as an immediate */
1008 /* set stack parameter passing style */
1009 be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
1011 for (i = 0; i < n; i++) {
1012 /* reg = get reg for param i; */
1013 /* be_abi_call_param_reg(abi, i, reg); */
1016 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1018 be_abi_call_param_stack(abi, i, 4, 0, 0);
1021 /* default: return value is in R0 resp. F0 */
1022 assert(get_method_n_ress(method_type) < 2);
1023 if (get_method_n_ress(method_type) > 0) {
1024 tp = get_method_res_type(method_type, 0);
1025 mode = get_type_mode(tp);
1027 be_abi_call_res_reg(abi, 0,
1028 mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]);
1032 static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1033 return &arm_irn_ops;
1036 const arch_irn_handler_t arm_irn_handler = {
1040 const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
1041 return &arm_irn_handler;
1044 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1045 if(!is_arm_irn(irn))
1052 * Initializes the code generator interface.
1054 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1055 return &arm_code_gen_if;
1058 list_sched_selector_t arm_sched_selector;
1061 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1063 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1064 memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1065 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1066 return &arm_sched_selector;
1069 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
1074 * Returns the necessary byte alignment for storing a register of given class.
1076 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1077 ir_mode *mode = arch_register_class_mode(cls);
1078 return get_mode_size_bytes(mode);
1081 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1087 static const be_machine_t *arm_get_machine(const void *self) {
1094 * Return irp irgs in the desired order.
1096 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
1101 * Returns the libFirm configuration parameter for this backend.
1103 static const backend_params *arm_get_libfirm_params(void) {
1104 static arch_dep_params_t ad = {
1106 1, /* Muls are fast enough on ARM but ... */
1107 1, /* ... one shift would be possible better */
1108 0, /* SMUL is needed, only in Arch M*/
1109 0, /* UMUL is needed, only in Arch M */
1110 32, /* SMUL & UMUL available for 32 bit */
1112 static backend_params p = {
1113 1, /* need dword lowering */
1114 0, /* don't support inline assembler yet */
1115 0, /* no different calling conventions */
1116 NULL, /* no additional opcodes */
1117 NULL, /* will be set later */
1118 NULL, /* but yet no creator function */
1119 NULL, /* context for create_intrinsic_fkt */
1120 NULL, /* no if conversion settings */
1127 /* fpu set architectures. */
1128 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1129 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1130 { "fpe", ARM_FPU_ARCH_FPE },
1131 { "fpa", ARM_FPU_ARCH_FPA },
1132 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1133 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1134 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1138 static lc_opt_enum_int_var_t arch_fpu_var = {
1139 &arm_isa_template.fpu_arch, arm_fpu_items
1142 static const lc_opt_table_entry_t arm_options[] = {
1143 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1144 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1148 const arch_isa_if_t arm_isa_if = {
1151 arm_get_n_reg_class,
1153 arm_get_reg_class_for_mode,
1155 arm_get_irn_handler,
1156 arm_get_code_generator_if,
1157 arm_get_list_sched_selector,
1158 arm_get_ilp_sched_selector,
1159 arm_get_reg_class_alignment,
1160 arm_get_libfirm_params,
1161 arm_get_allowed_execution_units,
1166 void be_init_arch_arm(void)
1168 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1169 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1171 lc_opt_add_table(arm_grp, arm_options);
1173 be_register_isa_if("arm", &arm_isa_if);
1176 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);