2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist
29 #include "lc_opts_enum.h"
37 #include "iroptimize.h"
47 #include "../bearch.h"
48 #include "../benode.h"
49 #include "../belower.h"
50 #include "../besched.h"
52 #include "../bemachine.h"
53 #include "../beilpsched.h"
54 #include "../bemodule.h"
56 #include "../bespillslots.h"
57 #include "../begnuas.h"
58 #include "../belistsched.h"
59 #include "../beflags.h"
61 #include "bearch_arm_t.h"
63 #include "arm_new_nodes.h"
64 #include "gen_arm_regalloc_if.h"
65 #include "arm_transform.h"
66 #include "arm_optimize.h"
67 #include "arm_emitter.h"
68 #include "arm_map_regs.h"
70 static arch_irn_class_t arm_classify(const ir_node *irn)
73 /* TODO: we should mark reload/spill instructions and classify them here */
77 static ir_entity *arm_get_frame_entity(const ir_node *irn)
79 const arm_attr_t *attr = get_arm_attr_const(irn);
81 if (is_arm_FrameAddr(irn)) {
82 const arm_SymConst_attr_t *attr = get_irn_generic_attr_const(irn);
85 if (attr->is_load_store) {
86 const arm_load_store_attr_t *load_store_attr
87 = get_arm_load_store_attr_const(irn);
88 if (load_store_attr->is_frame_entity) {
89 return load_store_attr->entity;
96 * This function is called by the generic backend to correct offsets for
97 * nodes accessing the stack.
99 static void arm_set_stack_bias(ir_node *irn, int bias)
101 if (is_arm_FrameAddr(irn)) {
102 arm_SymConst_attr_t *attr = get_irn_generic_attr(irn);
103 attr->fp_offset += bias;
105 arm_load_store_attr_t *attr = get_arm_load_store_attr(irn);
106 assert(attr->base.is_load_store);
107 attr->offset += bias;
111 static int arm_get_sp_bias(const ir_node *irn)
113 /* We don't have any nodes changing the stack pointer.
114 We probably want to support post-/pre increment/decrement later */
119 /* fill register allocator interface */
121 static const arch_irn_ops_t arm_irn_ops = {
124 arm_get_frame_entity,
127 NULL, /* get_inverse */
128 NULL, /* get_op_estimated_cost */
129 NULL, /* possible_memory_operand */
130 NULL, /* perform_memory_operand */
134 * Transforms the standard Firm graph into
137 static void arm_prepare_graph(void *self)
139 arm_code_gen_t *cg = self;
141 /* transform nodes into assembler instructions */
142 arm_transform_graph(cg);
144 /* do local optimizations (mainly CSE) */
145 local_optimize_graph(cg->irg);
148 dump_ir_graph(cg->irg, "transformed");
150 /* do code placement, to optimize the position of constants */
154 dump_ir_graph(cg->irg, "place");
158 * Called immediately before emit phase.
160 static void arm_finish_irg(void *self)
162 arm_code_gen_t *cg = self;
164 /* do peephole optimizations and fix stack offsets */
165 arm_peephole_optimization(cg);
168 static void arm_before_ra(void *self)
170 arm_code_gen_t *cg = self;
172 be_sched_fix_flags(cg->irg, &arm_reg_classes[CLASS_arm_flags],
176 static void transform_Reload(ir_node *node)
178 ir_node *block = get_nodes_block(node);
179 dbg_info *dbgi = get_irn_dbg_info(node);
180 ir_node *ptr = get_irn_n(node, be_pos_Reload_frame);
181 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
182 ir_mode *mode = get_irn_mode(node);
183 ir_entity *entity = be_get_frame_entity(node);
184 const arch_register_t *reg;
188 ir_node *sched_point = sched_prev(node);
190 load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true);
191 sched_add_after(sched_point, load);
194 proj = new_rd_Proj(dbgi, load, mode, pn_arm_Ldr_res);
196 reg = arch_get_irn_register(node);
197 arch_set_irn_register(proj, reg);
199 exchange(node, proj);
202 static void transform_Spill(ir_node *node)
204 ir_node *block = get_nodes_block(node);
205 dbg_info *dbgi = get_irn_dbg_info(node);
206 ir_node *ptr = get_irn_n(node, be_pos_Spill_frame);
207 ir_node *mem = new_NoMem();
208 ir_node *val = get_irn_n(node, be_pos_Spill_val);
209 ir_mode *mode = get_irn_mode(val);
210 ir_entity *entity = be_get_frame_entity(node);
211 ir_node *sched_point;
214 sched_point = sched_prev(node);
215 store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0,
219 sched_add_after(sched_point, store);
221 exchange(node, store);
224 static void arm_after_ra_walker(ir_node *block, void *data)
226 ir_node *node, *prev;
229 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
230 prev = sched_prev(node);
232 if (be_is_Reload(node)) {
233 transform_Reload(node);
234 } else if (be_is_Spill(node)) {
235 transform_Spill(node);
240 static void arm_collect_frame_entity_nodes(ir_node *node, void *data)
242 be_fec_env_t *env = data;
246 const arm_load_store_attr_t *attr;
248 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
249 mode = get_irn_mode(node);
250 align = get_mode_size_bytes(mode);
251 be_node_needs_frame_entity(env, node, mode, align);
255 switch (get_arm_irn_opcode(node)) {
263 attr = get_arm_load_store_attr_const(node);
264 entity = attr->entity;
265 mode = attr->load_store_mode;
266 align = get_mode_size_bytes(mode);
269 if (!attr->is_frame_entity)
271 be_node_needs_frame_entity(env, node, mode, align);
274 static void arm_set_frame_entity(ir_node *node, ir_entity *entity)
276 if (is_be_node(node)) {
277 be_node_set_frame_entity(node, entity);
279 arm_load_store_attr_t *attr = get_arm_load_store_attr(node);
280 attr->entity = entity;
284 static void arm_after_ra(void *self)
286 arm_code_gen_t *cg = self;
287 ir_graph *irg = cg->irg;
289 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
291 irg_walk_graph(irg, NULL, arm_collect_frame_entity_nodes, fec_env);
292 be_assign_entities(fec_env, arm_set_frame_entity);
293 be_free_frame_entity_coalescer(fec_env);
295 irg_block_walk_graph(cg->irg, NULL, arm_after_ra_walker, NULL);
299 * Emits the code, closes the output file and frees
300 * the code generator interface.
302 static void arm_emit_and_done(void *self)
304 arm_code_gen_t *cg = self;
305 ir_graph *irg = cg->irg;
307 arm_gen_routine(cg, irg);
309 /* de-allocate code generator */
314 static void *arm_cg_init(ir_graph *irg);
316 static const arch_code_generator_if_t arm_code_gen_if = {
318 NULL, /* get_pic_base */
319 NULL, /* before abi introduce */
322 arm_before_ra, /* before register allocation hook */
329 * Initializes the code generator.
331 static void *arm_cg_init(ir_graph *irg)
333 arm_isa_t *isa = (arm_isa_t*) be_get_irg_arch_env(irg);
336 cg = XMALLOCZ(arm_code_gen_t);
337 cg->impl = &arm_code_gen_if;
340 cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
342 /* enter the current code generator */
345 return (arch_code_generator_t *)cg;
350 * Maps all intrinsic calls that the backend support
351 * and map all instructions the backend did not support
354 static void arm_handle_intrinsics(void)
356 ir_type *tp, *int_tp, *uint_tp;
360 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
362 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
364 int_tp = get_type_for_mode(mode_Is);
365 uint_tp = get_type_for_mode(mode_Iu);
367 /* ARM has neither a signed div instruction ... */
369 i_instr_record *map_Div = &records[n_records++].i_instr;
371 tp = new_type_method(2, 1);
372 set_method_param_type(tp, 0, int_tp);
373 set_method_param_type(tp, 1, int_tp);
374 set_method_res_type(tp, 0, int_tp);
376 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
377 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
378 rt_iDiv.mode = mode_T;
379 rt_iDiv.res_mode = mode_Is;
380 rt_iDiv.mem_proj_nr = pn_Div_M;
381 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
382 rt_iDiv.exc_proj_nr = pn_Div_X_except;
383 rt_iDiv.exc_mem_proj_nr = pn_Div_M;
384 rt_iDiv.res_proj_nr = pn_Div_res;
386 add_entity_linkage(rt_iDiv.ent, IR_LINKAGE_CONSTANT);
387 set_entity_visibility(rt_iDiv.ent, ir_visibility_external);
389 map_Div->kind = INTRINSIC_INSTR;
390 map_Div->op = op_Div;
391 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
392 map_Div->ctx = &rt_iDiv;
394 /* ... nor an unsigned div instruction ... */
396 i_instr_record *map_Div = &records[n_records++].i_instr;
398 tp = new_type_method(2, 1);
399 set_method_param_type(tp, 0, uint_tp);
400 set_method_param_type(tp, 1, uint_tp);
401 set_method_res_type(tp, 0, uint_tp);
403 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
404 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
405 rt_uDiv.mode = mode_T;
406 rt_uDiv.res_mode = mode_Iu;
407 rt_uDiv.mem_proj_nr = pn_Div_M;
408 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
409 rt_uDiv.exc_proj_nr = pn_Div_X_except;
410 rt_uDiv.exc_mem_proj_nr = pn_Div_M;
411 rt_uDiv.res_proj_nr = pn_Div_res;
413 set_entity_visibility(rt_uDiv.ent, ir_visibility_external);
415 map_Div->kind = INTRINSIC_INSTR;
416 map_Div->op = op_Div;
417 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
418 map_Div->ctx = &rt_uDiv;
420 /* ... nor a signed mod instruction ... */
422 i_instr_record *map_Mod = &records[n_records++].i_instr;
424 tp = new_type_method(2, 1);
425 set_method_param_type(tp, 0, int_tp);
426 set_method_param_type(tp, 1, int_tp);
427 set_method_res_type(tp, 0, int_tp);
429 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
430 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
431 rt_iMod.mode = mode_T;
432 rt_iMod.res_mode = mode_Is;
433 rt_iMod.mem_proj_nr = pn_Mod_M;
434 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
435 rt_iMod.exc_proj_nr = pn_Mod_X_except;
436 rt_iMod.exc_mem_proj_nr = pn_Mod_M;
437 rt_iMod.res_proj_nr = pn_Mod_res;
439 set_entity_visibility(rt_iMod.ent, ir_visibility_external);
441 map_Mod->kind = INTRINSIC_INSTR;
442 map_Mod->op = op_Mod;
443 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
444 map_Mod->ctx = &rt_iMod;
446 /* ... nor an unsigned mod. */
448 i_instr_record *map_Mod = &records[n_records++].i_instr;
450 tp = new_type_method(2, 1);
451 set_method_param_type(tp, 0, uint_tp);
452 set_method_param_type(tp, 1, uint_tp);
453 set_method_res_type(tp, 0, uint_tp);
455 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
456 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
457 rt_uMod.mode = mode_T;
458 rt_uMod.res_mode = mode_Iu;
459 rt_uMod.mem_proj_nr = pn_Mod_M;
460 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
461 rt_uMod.exc_proj_nr = pn_Mod_X_except;
462 rt_uMod.exc_mem_proj_nr = pn_Mod_M;
463 rt_uMod.res_proj_nr = pn_Mod_res;
465 set_entity_visibility(rt_uMod.ent, ir_visibility_external);
467 map_Mod->kind = INTRINSIC_INSTR;
468 map_Mod->op = op_Mod;
469 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
470 map_Mod->ctx = &rt_uMod;
474 lower_intrinsics(records, n_records, /*part_block_used=*/0);
477 const arch_isa_if_t arm_isa_if;
478 static arm_isa_t arm_isa_template = {
480 &arm_isa_if, /* isa interface */
481 &arm_gp_regs[REG_SP], /* stack pointer */
482 &arm_gp_regs[REG_R11], /* base pointer */
483 &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */
484 -1, /* stack direction */
485 2, /* power of two stack alignment for calls, 2^2 == 4 */
486 NULL, /* main environment */
488 5, /* reload costs */
489 true, /* we do have custom abi handling */
491 ARM_FPU_ARCH_FPE, /* FPU architecture */
492 NULL, /* current code generator */
496 * Initializes the backend ISA and opens the output file.
498 static arch_env_t *arm_init(FILE *file_handle)
500 static int inited = 0;
506 isa = XMALLOC(arm_isa_t);
507 memcpy(isa, &arm_isa_template, sizeof(*isa));
512 be_emit_init(file_handle);
514 arm_create_opcodes(&arm_irn_ops);
515 arm_handle_intrinsics();
517 be_gas_emit_types = false;
519 /* needed for the debug support */
520 be_gas_emit_switch_section(GAS_SECTION_TEXT);
521 be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
522 be_emit_write_line();
531 * Closes the output file and frees the ISA structure.
533 static void arm_done(void *self)
535 arm_isa_t *isa = self;
537 be_gas_emit_decls(isa->base.main_env);
545 * Report the number of register classes.
546 * If we don't have fp instructions, report only GP
547 * here to speed up register allocation (and makes dumps
548 * smaller and more readable).
550 static unsigned arm_get_n_reg_class(void)
556 * Return the register class with requested index.
558 static const arch_register_class_t *arm_get_reg_class(unsigned i)
560 assert(i < N_CLASSES);
561 return &arm_reg_classes[i];
565 * Get the register class which shall be used to store a value of a given mode.
566 * @param self The this pointer.
567 * @param mode The mode in question.
568 * @return A register class which can hold values of the given mode.
570 static const arch_register_class_t *arm_get_reg_class_for_mode(const ir_mode *mode)
572 if (mode_is_float(mode))
573 return &arm_reg_classes[CLASS_arm_fpa];
575 return &arm_reg_classes[CLASS_arm_gp];
578 static int arm_to_appear_in_schedule(void *block_env, const ir_node *irn)
581 if (!is_arm_irn(irn))
588 * Initializes the code generator interface.
590 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self)
593 return &arm_code_gen_if;
596 list_sched_selector_t arm_sched_selector;
599 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
601 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector)
604 memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
605 /* arm_sched_selector.exectime = arm_sched_exectime; */
606 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
607 return &arm_sched_selector;
611 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self)
618 * Returns the necessary byte alignment for storing a register of given class.
620 static int arm_get_reg_class_alignment(const arch_register_class_t *cls)
623 /* ARM is a 32 bit CPU, no need for other alignment */
627 static const be_execution_unit_t ***arm_get_allowed_execution_units(const ir_node *irn)
631 panic("Unimplemented arm_get_allowed_execution_units()");
634 static const be_machine_t *arm_get_machine(const void *self)
638 panic("Unimplemented arm_get_machine()");
642 * Return irp irgs in the desired order.
644 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list)
652 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
653 * @return 1 if allowed, 0 otherwise
655 static int arm_is_mux_allowed(ir_node *sel, ir_node *mux_false,
665 static asm_constraint_flags_t arm_parse_asm_constraint(const char **c)
667 /* asm not supported */
669 return ASM_CONSTRAINT_FLAG_INVALID;
672 static int arm_is_valid_clobber(const char *clobber)
679 * Returns the libFirm configuration parameter for this backend.
681 static const backend_params *arm_get_libfirm_params(void)
683 static ir_settings_arch_dep_t ad = {
685 1, /* Muls are fast enough on ARM but ... */
686 31, /* ... one shift would be possible better */
687 NULL, /* no evaluator function */
688 0, /* SMUL is needed, only in Arch M */
689 0, /* UMUL is needed, only in Arch M */
690 32, /* SMUL & UMUL available for 32 bit */
692 static backend_params p = {
693 0, /* don't support inline assembler yet */
694 1, /* support Rotl nodes */
696 NULL, /* lowering function */
697 &ad, /* will be set later */
698 arm_is_mux_allowed, /* allow_ifconv function */
699 NULL, /* float arithmetic mode (TODO) */
700 0, /* no trampoline support: size 0 */
701 0, /* no trampoline support: align 0 */
702 NULL, /* no trampoline support: no trampoline builder */
703 4 /* alignment of stack parameter */
709 /* fpu set architectures. */
710 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
711 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
712 { "fpe", ARM_FPU_ARCH_FPE },
713 { "fpa", ARM_FPU_ARCH_FPA },
714 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
715 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
716 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
720 static lc_opt_enum_int_var_t arch_fpu_var = {
721 &arm_isa_template.fpu_arch, arm_fpu_items
724 static const lc_opt_table_entry_t arm_options[] = {
725 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
729 const arch_isa_if_t arm_isa_if = {
732 NULL, /* handle_intrinsics */
735 arm_get_reg_class_for_mode,
737 arm_get_code_generator_if,
738 arm_get_list_sched_selector,
739 arm_get_ilp_sched_selector,
740 arm_get_reg_class_alignment,
741 arm_get_libfirm_params,
742 arm_get_allowed_execution_units,
745 NULL, /* mark remat */
746 arm_parse_asm_constraint,
750 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);
751 void be_init_arch_arm(void)
753 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
754 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
756 lc_opt_add_table(arm_grp, arm_options);
758 be_register_isa_if("arm", &arm_isa_if);
760 arm_init_transform();