2 * This file is part of libFirm.
3 * Copyright (C) 2012 University of Karlsruhe.
8 * @brief The main arm backend driver file.
9 * @author Matthias Braun, Oliver Richter, Tobias Gneist
14 #include "lc_opts_enum.h"
22 #include "iroptimize.h"
24 #include "lower_calls.h"
39 #include "bespillslots.h"
40 #include "bespillutil.h"
42 #include "belistsched.h"
46 #include "bearch_arm_t.h"
48 #include "arm_new_nodes.h"
49 #include "gen_arm_regalloc_if.h"
50 #include "arm_transform.h"
51 #include "arm_optimize.h"
52 #include "arm_emitter.h"
53 #include "arm_map_regs.h"
55 static ir_entity *arm_get_frame_entity(const ir_node *irn)
57 const arm_attr_t *attr = get_arm_attr_const(irn);
59 if (is_arm_FrameAddr(irn)) {
60 const arm_SymConst_attr_t *frame_attr = get_arm_SymConst_attr_const(irn);
61 return frame_attr->entity;
63 if (attr->is_load_store) {
64 const arm_load_store_attr_t *load_store_attr
65 = get_arm_load_store_attr_const(irn);
66 if (load_store_attr->is_frame_entity) {
67 return load_store_attr->entity;
74 * This function is called by the generic backend to correct offsets for
75 * nodes accessing the stack.
77 static void arm_set_stack_bias(ir_node *irn, int bias)
79 if (is_arm_FrameAddr(irn)) {
80 arm_SymConst_attr_t *attr = get_arm_SymConst_attr(irn);
81 attr->fp_offset += bias;
83 arm_load_store_attr_t *attr = get_arm_load_store_attr(irn);
84 assert(attr->base.is_load_store);
89 static int arm_get_sp_bias(const ir_node *irn)
91 /* We don't have any nodes changing the stack pointer.
92 We probably want to support post-/pre increment/decrement later */
97 /* fill register allocator interface */
99 static const arch_irn_ops_t arm_irn_ops = {
100 arm_get_frame_entity,
103 NULL, /* get_op_estimated_cost */
104 NULL, /* possible_memory_operand */
105 NULL, /* perform_memory_operand */
109 * Transforms the standard Firm graph into
112 static void arm_prepare_graph(ir_graph *irg)
114 /* transform nodes into assembler instructions */
115 arm_transform_graph(irg);
117 /* do local optimizations (mainly CSE) */
118 local_optimize_graph(irg);
120 /* do code placement, to optimize the position of constants */
124 static void arm_collect_frame_entity_nodes(ir_node *node, void *data)
126 be_fec_env_t *env = (be_fec_env_t*)data;
130 const arm_load_store_attr_t *attr;
132 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
133 mode = get_irn_mode(node);
134 align = get_mode_size_bytes(mode);
135 be_node_needs_frame_entity(env, node, mode, align);
139 switch (get_arm_irn_opcode(node)) {
147 attr = get_arm_load_store_attr_const(node);
148 entity = attr->entity;
149 mode = attr->load_store_mode;
150 align = get_mode_size_bytes(mode);
153 if (!attr->is_frame_entity)
155 be_node_needs_frame_entity(env, node, mode, align);
158 static void arm_set_frame_entity(ir_node *node, ir_entity *entity)
160 if (is_be_node(node)) {
161 be_node_set_frame_entity(node, entity);
163 arm_load_store_attr_t *attr = get_arm_load_store_attr(node);
164 attr->entity = entity;
168 static void transform_Reload(ir_node *node)
170 ir_node *block = get_nodes_block(node);
171 dbg_info *dbgi = get_irn_dbg_info(node);
172 ir_node *ptr = get_irn_n(node, n_be_Reload_frame);
173 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
174 ir_mode *mode = get_irn_mode(node);
175 ir_entity *entity = be_get_frame_entity(node);
176 const arch_register_t *reg;
180 load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true);
181 sched_replace(node, load);
183 proj = new_rd_Proj(dbgi, load, mode, pn_arm_Ldr_res);
185 reg = arch_get_irn_register(node);
186 arch_set_irn_register(proj, reg);
188 exchange(node, proj);
191 static void transform_Spill(ir_node *node)
193 ir_node *block = get_nodes_block(node);
194 dbg_info *dbgi = get_irn_dbg_info(node);
195 ir_node *ptr = get_irn_n(node, n_be_Spill_frame);
196 ir_graph *irg = get_irn_irg(node);
197 ir_node *mem = get_irg_no_mem(irg);
198 ir_node *val = get_irn_n(node, n_be_Spill_val);
199 ir_mode *mode = get_irn_mode(val);
200 ir_entity *entity = be_get_frame_entity(node);
203 store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0,
205 sched_replace(node, store);
207 exchange(node, store);
210 static void arm_after_ra_walker(ir_node *block, void *data)
214 sched_foreach_reverse_safe(block, node) {
215 if (be_is_Reload(node)) {
216 transform_Reload(node);
217 } else if (be_is_Spill(node)) {
218 transform_Spill(node);
224 * Called immediately before emit phase.
226 static void arm_finish_irg(ir_graph *irg)
228 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
229 bool at_begin = stack_layout->sp_relative ? true : false;
230 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
232 irg_walk_graph(irg, NULL, arm_collect_frame_entity_nodes, fec_env);
233 be_assign_entities(fec_env, arm_set_frame_entity, at_begin);
234 be_free_frame_entity_coalescer(fec_env);
236 irg_block_walk_graph(irg, NULL, arm_after_ra_walker, NULL);
238 /* fix stack entity offsets */
239 be_abi_fix_stack_nodes(irg);
240 be_abi_fix_stack_bias(irg);
242 /* do peephole optimizations and fix stack offsets */
243 arm_peephole_optimization(irg);
246 static void arm_before_ra(ir_graph *irg)
248 be_sched_fix_flags(irg, &arm_reg_classes[CLASS_arm_flags], NULL, NULL);
252 * Maps all intrinsic calls that the backend support
253 * and map all instructions the backend did not support
256 static void arm_handle_intrinsics(void)
258 ir_type *tp, *int_tp, *uint_tp;
262 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
264 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
266 int_tp = get_type_for_mode(mode_Is);
267 uint_tp = get_type_for_mode(mode_Iu);
269 /* ARM has neither a signed div instruction ... */
271 i_instr_record *map_Div = &records[n_records++].i_instr;
273 tp = new_type_method(2, 1);
274 set_method_param_type(tp, 0, int_tp);
275 set_method_param_type(tp, 1, int_tp);
276 set_method_res_type(tp, 0, int_tp);
278 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
279 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
280 rt_iDiv.mode = mode_T;
281 rt_iDiv.res_mode = mode_Is;
282 rt_iDiv.mem_proj_nr = pn_Div_M;
283 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
284 rt_iDiv.exc_proj_nr = pn_Div_X_except;
285 rt_iDiv.res_proj_nr = pn_Div_res;
287 add_entity_linkage(rt_iDiv.ent, IR_LINKAGE_CONSTANT);
288 set_entity_visibility(rt_iDiv.ent, ir_visibility_external);
290 map_Div->kind = INTRINSIC_INSTR;
291 map_Div->op = op_Div;
292 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
293 map_Div->ctx = &rt_iDiv;
295 /* ... nor an unsigned div instruction ... */
297 i_instr_record *map_Div = &records[n_records++].i_instr;
299 tp = new_type_method(2, 1);
300 set_method_param_type(tp, 0, uint_tp);
301 set_method_param_type(tp, 1, uint_tp);
302 set_method_res_type(tp, 0, uint_tp);
304 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
305 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
306 rt_uDiv.mode = mode_T;
307 rt_uDiv.res_mode = mode_Iu;
308 rt_uDiv.mem_proj_nr = pn_Div_M;
309 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
310 rt_uDiv.exc_proj_nr = pn_Div_X_except;
311 rt_uDiv.res_proj_nr = pn_Div_res;
313 set_entity_visibility(rt_uDiv.ent, ir_visibility_external);
315 map_Div->kind = INTRINSIC_INSTR;
316 map_Div->op = op_Div;
317 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
318 map_Div->ctx = &rt_uDiv;
320 /* ... nor a signed mod instruction ... */
322 i_instr_record *map_Mod = &records[n_records++].i_instr;
324 tp = new_type_method(2, 1);
325 set_method_param_type(tp, 0, int_tp);
326 set_method_param_type(tp, 1, int_tp);
327 set_method_res_type(tp, 0, int_tp);
329 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
330 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
331 rt_iMod.mode = mode_T;
332 rt_iMod.res_mode = mode_Is;
333 rt_iMod.mem_proj_nr = pn_Mod_M;
334 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
335 rt_iMod.exc_proj_nr = pn_Mod_X_except;
336 rt_iMod.res_proj_nr = pn_Mod_res;
338 set_entity_visibility(rt_iMod.ent, ir_visibility_external);
340 map_Mod->kind = INTRINSIC_INSTR;
341 map_Mod->op = op_Mod;
342 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
343 map_Mod->ctx = &rt_iMod;
345 /* ... nor an unsigned mod. */
347 i_instr_record *map_Mod = &records[n_records++].i_instr;
349 tp = new_type_method(2, 1);
350 set_method_param_type(tp, 0, uint_tp);
351 set_method_param_type(tp, 1, uint_tp);
352 set_method_res_type(tp, 0, uint_tp);
354 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
355 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
356 rt_uMod.mode = mode_T;
357 rt_uMod.res_mode = mode_Iu;
358 rt_uMod.mem_proj_nr = pn_Mod_M;
359 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
360 rt_uMod.exc_proj_nr = pn_Mod_X_except;
361 rt_uMod.res_proj_nr = pn_Mod_res;
363 set_entity_visibility(rt_uMod.ent, ir_visibility_external);
365 map_Mod->kind = INTRINSIC_INSTR;
366 map_Mod->op = op_Mod;
367 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
368 map_Mod->ctx = &rt_uMod;
372 lower_intrinsics(records, n_records, /*part_block_used=*/0);
375 extern const arch_isa_if_t arm_isa_if;
376 static arm_isa_t arm_isa_template = {
378 &arm_isa_if, /* isa interface */
383 &arm_registers[REG_SP], /* stack pointer */
384 &arm_registers[REG_R11], /* base pointer */
385 2, /* power of two stack alignment for calls, 2^2 == 4 */
387 5, /* reload costs */
388 true, /* we do have custom abi handling */
390 ARM_FPU_ARCH_FPE, /* FPU architecture */
393 static void arm_init(void)
397 arm_create_opcodes(&arm_irn_ops);
400 static void arm_finish(void)
405 static arch_env_t *arm_begin_codegeneration(void)
407 arm_isa_t *isa = XMALLOC(arm_isa_t);
408 *isa = arm_isa_template;
410 be_gas_emit_types = false;
416 * Closes the output file and frees the ISA structure.
418 static void arm_end_codegeneration(void *self)
424 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
425 * @return 1 if allowed, 0 otherwise
427 static int arm_is_mux_allowed(ir_node *sel, ir_node *mux_false,
436 static asm_constraint_flags_t arm_parse_asm_constraint(const char **c)
438 /* asm not supported */
440 return ASM_CONSTRAINT_FLAG_INVALID;
443 static int arm_is_valid_clobber(const char *clobber)
449 static void arm_lower_for_target(void)
451 ir_mode *mode_gp = arm_reg_classes[CLASS_arm_gp].mode;
452 size_t i, n_irgs = get_irp_n_irgs();
454 /* lower compound param handling */
455 lower_calls_with_compounds(LF_RETURN_HIDDEN);
457 for (i = 0; i < n_irgs; ++i) {
458 ir_graph *irg = get_irp_irg(i);
459 lower_switch(irg, 4, 256, mode_gp);
462 for (i = 0; i < n_irgs; ++i) {
463 ir_graph *irg = get_irp_irg(i);
464 /* Turn all small CopyBs into loads/stores and all bigger CopyBs into
466 * TODO: These constants need arm-specific tuning. */
467 lower_CopyB(irg, 31, 32, false);
472 * Returns the libFirm configuration parameter for this backend.
474 static const backend_params *arm_get_libfirm_params(void)
476 static ir_settings_arch_dep_t ad = {
478 1, /* Muls are fast enough on ARM but ... */
479 31, /* ... one shift would be possible better */
480 NULL, /* no evaluator function */
481 0, /* SMUL is needed, only in Arch M */
482 0, /* UMUL is needed, only in Arch M */
483 32, /* SMUL & UMUL available for 32 bit */
485 static backend_params p = {
486 0, /* don't support inline assembler yet */
487 1, /* support Rotl nodes */
489 1, /* modulo shift efficient */
490 0, /* non-modulo shift not efficient */
491 &ad, /* will be set later */
492 arm_is_mux_allowed, /* allow_ifconv function */
493 32, /* machine size */
494 NULL, /* float arithmetic mode (TODO) */
495 NULL, /* long long type */
496 NULL, /* unsigned long long type */
497 NULL, /* long double type */
498 0, /* no trampoline support: size 0 */
499 0, /* no trampoline support: align 0 */
500 NULL, /* no trampoline support: no trampoline builder */
501 4 /* alignment of stack parameter */
507 /* fpu set architectures. */
508 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
509 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
510 { "fpe", ARM_FPU_ARCH_FPE },
511 { "fpa", ARM_FPU_ARCH_FPA },
512 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
513 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
514 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
518 static lc_opt_enum_int_var_t arch_fpu_var = {
519 &arm_isa_template.fpu_arch, arm_fpu_items
522 static const lc_opt_table_entry_t arm_options[] = {
523 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
527 const arch_isa_if_t arm_isa_if = {
530 arm_get_libfirm_params,
531 arm_lower_for_target,
532 arm_parse_asm_constraint,
533 arm_is_valid_clobber,
535 arm_begin_codegeneration,
536 arm_end_codegeneration,
538 NULL, /* get call abi */
539 NULL, /* mark remat */
540 NULL, /* get_pic_base */
543 NULL, /* register_saved_by */
545 arm_handle_intrinsics, /* handle_intrinsics */
546 NULL, /* before_abi */
553 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm)
554 void be_init_arch_arm(void)
556 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
557 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
559 lc_opt_add_table(arm_grp, arm_options);
561 be_register_isa_if("arm", &arm_isa_if);
563 arm_init_transform();