1 /* The main arm backend driver file. */
8 #include "pseudo_irg.h"
14 #include "lower_intrinsics.h"
19 #include "../bearch.h" /* the general register allocator interface */
20 #include "../benode_t.h"
21 #include "../belower.h"
22 #include "../besched_t.h"
26 #include "bearch_arm_t.h"
28 #include "arm_new_nodes.h" /* arm nodes interface */
29 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
30 #include "arm_gen_decls.h" /* interface declaration emitter */
31 #include "arm_transform.h"
32 #include "arm_emitter.h"
33 #include "arm_map_regs.h"
35 #define DEBUG_MODULE "firm.be.arm.isa"
37 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
38 static set *cur_reg_set = NULL;
40 /**************************************************
43 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
44 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
45 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
46 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
49 **************************************************/
51 static ir_node *my_skip_proj(const ir_node *n) {
58 * Return register requirements for a arm node.
59 * If the node returns a tuple (mode_T) then the proj's
60 * will be asked for this information.
62 static const arch_register_req_t *arm_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
63 const arm_register_req_t *irn_req;
64 long node_pos = pos == -1 ? 0 : pos;
65 ir_mode *mode = get_irn_mode(irn);
66 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
68 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
69 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
73 if (mode == mode_T && pos < 0) {
74 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
78 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
81 /* in case of a proj, we need to get the correct OUT slot */
82 /* of the node corresponding to the proj number */
84 node_pos = arm_translate_proj_pos(irn);
90 irn = my_skip_proj(irn);
92 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
95 /* get requirements for our own nodes */
96 if (is_arm_irn(irn)) {
98 irn_req = get_arm_in_req(irn, pos);
101 irn_req = get_arm_out_req(irn, node_pos);
104 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
106 memcpy(req, &(irn_req->req), sizeof(*req));
108 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
109 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
110 req->other_same = get_irn_n(irn, irn_req->same_pos);
113 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
114 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
115 req->other_different = get_irn_n(irn, irn_req->different_pos);
118 /* get requirements for FIRM nodes */
120 /* treat Phi like Const with default requirements */
122 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
124 if (mode_is_float(mode)) {
125 memcpy(req, &(arm_default_req_arm_floating_point.req), sizeof(*req));
127 else if (mode_is_int(mode) || mode_is_reference(mode)) {
128 memcpy(req, &(arm_default_req_arm_general_purpose.req), sizeof(*req));
130 else if (mode == mode_T || mode == mode_M) {
131 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
135 assert(0 && "unsupported Phi-Mode");
139 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
147 static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
152 if (get_irn_mode(irn) == mode_X) {
156 pos = arm_translate_proj_pos(irn);
157 irn = my_skip_proj(irn);
160 if (is_arm_irn(irn)) {
161 const arch_register_t **slots;
163 slots = get_arm_slots(irn);
167 /* here we set the registers for the Phi nodes */
168 arm_set_firm_reg(irn, reg, cur_reg_set);
172 static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) {
174 const arch_register_t *reg = NULL;
178 if (get_irn_mode(irn) == mode_X) {
182 pos = arm_translate_proj_pos(irn);
183 irn = my_skip_proj(irn);
186 if (is_arm_irn(irn)) {
187 const arch_register_t **slots;
188 slots = get_arm_slots(irn);
192 reg = arm_get_firm_reg(irn, cur_reg_set);
198 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
199 irn = my_skip_proj(irn);
202 return arch_irn_class_branch;
204 else if (is_arm_irn(irn)) {
205 return arch_irn_class_normal;
211 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
212 irn = my_skip_proj(irn);
214 if (is_arm_irn(irn)) {
215 return get_arm_flags(irn);
217 else if (is_Unknown(irn)) {
218 return arch_irn_flags_ignore;
224 static entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
225 /* TODO: return the entity assigned to the frame */
230 * This function is called by the generic backend to correct offsets for
231 * nodes accessing the stack.
233 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
234 /* TODO: correct offset if irn accesses the stack */
237 /* fill register allocator interface */
239 static const arch_irn_ops_if_t arm_irn_ops_if = {
245 arm_get_frame_entity,
249 arm_irn_ops_t arm_irn_ops = {
256 /**************************************************
259 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
260 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
261 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
262 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
265 **************************************************/
268 * Transforms the standard firm graph into
271 static void arm_prepare_graph(void *self) {
272 arm_code_gen_t *cg = self;
274 irg_walk_blkwise_graph(cg->irg, arm_move_consts, arm_transform_node, cg);
280 * Called immediately before emit phase.
282 static void arm_finish_irg(ir_graph *irg, arm_code_gen_t *cg) {
283 /* TODO: - fix offsets for nodes accessing stack
290 * These are some hooks which must be filled but are probably not needed.
292 static void arm_before_sched(void *self) {
293 /* Some stuff you need to do after scheduling but before register allocation */
296 static void arm_before_ra(void *self) {
297 /* Some stuff you need to do immediately after register allocation */
302 * Emits the code, closes the output file and frees
303 * the code generator interface.
305 static void arm_emit_and_done(void *self) {
306 arm_code_gen_t *cg = self;
307 ir_graph *irg = cg->irg;
310 if (cg->emit_decls) {
311 arm_gen_decls(cg->out);
315 arm_finish_irg(irg, cg);
316 dump_ir_block_graph_sched(irg, "-arm-finished");
317 arm_gen_routine(out, irg, cg);
321 /* de-allocate code generator */
322 del_set(cg->reg_set);
326 enum convert_which { low, high };
329 * Move an floating point value to a integer register.
330 * Place the move operation into block bl.
332 static ir_node *convert_to_int(ir_node *bl, ir_node *arg, enum convert_which which) {
337 * Convert the arguments of a call to support the
338 * ARM calling convention of general purpose AND floating
341 static void handle_calls(ir_node *call, void *env)
343 arm_code_gen_t *cg = env;
344 int i, j, n, size, idx, flag, n_param, n_res;
345 ir_type *mtp, *new_mtd, *new_tp[5];
346 ir_node *new_in[5], **in;
352 /* check, if we need conversions */
353 n = get_Call_n_params(call);
354 mtp = get_Call_type(call);
355 assert(get_method_n_params(mtp) == n);
357 /* it's always enough to handle the first 4 parameters */
360 flag = size = idx = 0;
361 bl = get_nodes_block(call);
362 for (i = 0; i < n; ++i) {
363 ir_type *param_tp = get_method_param_type(mtp, i);
365 if (is_compound_type(param_tp)) {
366 /* an aggregate parameter: bad case */
370 /* a primitive parameter */
371 ir_mode *mode = get_type_mode(param_tp);
373 if (mode_is_float(mode)) {
374 if (get_mode_size_bits(mode) > 32) {
376 new_tp[idx] = cg->int_tp;
377 new_in[idx] = convert_to_int(bl, get_Call_param(call, i), low);
379 new_tp[idx] = cg->int_tp;
380 new_in[idx] = convert_to_int(bl, get_Call_param(call, i), high);
385 new_tp[idx] = cg->int_tp;
386 new_in[idx] = convert_to_int(bl, get_Call_param(call, i), low);
393 new_tp[idx] = param_tp;
394 new_in[idx] = get_Call_param(call, i);
403 /* if flag is NOT set, no need to translate the method type */
407 /* construct a new method type */
409 n_param = get_method_n_params(mtp) - n + idx;
410 n_res = get_method_n_ress(mtp);
411 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
413 for (i = 0; i < idx; ++i)
414 set_method_param_type(new_mtd, i, new_tp[i]);
415 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
416 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
417 for (i = 0; i < n_res; ++i)
418 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
420 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
421 set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp));
423 if (is_lowered_type(mtp)) {
424 mtp = get_associated_type(mtp);
426 set_lowered_type(mtp, new_mtd);
428 set_Call_type(call, new_mtd);
430 /* calculate new in array of the Call */
431 NEW_ARR_A(ir_node *, in, n_param + 2);
432 for (i = 0; i < idx; ++i)
433 in[2 + i] = new_in[i];
434 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
435 in[2 + j++] = get_Call_param(call, i);
437 in[0] = get_Call_mem(call);
438 in[1] = get_Call_ptr(call);
440 /* finally, change the call inputs */
441 set_irn_in(call, n_param + 2, in);
445 * Handle graph transformations before the abi converter does it's work
447 static void arm_before_abi(void *self) {
448 arm_code_gen_t *cg = self;
450 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
453 static void *arm_cg_init(FILE *F, const be_irg_t *birg);
455 static const arch_code_generator_if_t arm_code_gen_if = {
457 arm_before_abi, /* before abi introduce */
459 arm_before_sched, /* before scheduling hook */
460 arm_before_ra, /* before register allocation hook */
461 NULL, /* after register allocation */
466 * Initializes the code generator.
468 static void *arm_cg_init(FILE *F, const be_irg_t *birg) {
469 static ir_type *int_tp = NULL;
470 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
474 /* create an integer type with machine size */
475 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
478 cg = xmalloc(sizeof(*cg));
479 cg->impl = &arm_code_gen_if;
481 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
483 cg->arch_env = birg->main_env->arch_env;
486 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
490 if (isa->num_codegens > 1)
495 cur_reg_set = cg->reg_set;
499 return (arch_code_generator_t *)cg;
504 * Maps all intrinsic calls that the backend support
505 * and map all instructions the backend did not support
508 void arm_global_init(void) {
509 ir_type *tp, *int_tp, *uint_tp;
513 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
515 int_tp = new_type_primitive(ID("int"), mode_Is);
516 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
520 i_instr_record *map_Div = &records[n_records++].i_instr;
522 tp = new_type_method(ID("rt_iDiv"), 2, 1);
523 set_method_param_type(tp, 0, int_tp);
524 set_method_param_type(tp, 1, int_tp);
525 set_method_res_type(tp, 0, int_tp);
527 rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
528 rt_Div.mode = mode_T;
529 rt_Div.mem_proj_nr = pn_Div_M;
530 rt_Div.exc_proj_nr = pn_Div_X_except;
531 rt_Div.exc_mem_proj_nr = pn_Div_M;
532 rt_Div.res_proj_nr = pn_Div_res;
534 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
536 map_Div->kind = INTRINSIC_INSTR;
537 map_Div->op = op_Div;
538 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
539 map_Div->ctx = &rt_Div;
543 i_instr_record *map_Div = &records[n_records++].i_instr;
545 tp = new_type_method(ID("rt_uDiv"), 2, 1);
546 set_method_param_type(tp, 0, uint_tp);
547 set_method_param_type(tp, 1, uint_tp);
548 set_method_res_type(tp, 0, uint_tp);
550 rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
551 rt_Div.mode = mode_T;
552 rt_Div.mem_proj_nr = pn_Div_M;
553 rt_Div.exc_proj_nr = pn_Div_X_except;
554 rt_Div.exc_mem_proj_nr = pn_Div_M;
555 rt_Div.res_proj_nr = pn_Div_res;
557 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
559 map_Div->kind = INTRINSIC_INSTR;
560 map_Div->op = op_Div;
561 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
562 map_Div->ctx = &rt_Div;
566 i_instr_record *map_Mod = &records[n_records++].i_instr;
568 tp = new_type_method(ID("rt_iMod"), 2, 1);
569 set_method_param_type(tp, 0, int_tp);
570 set_method_param_type(tp, 1, int_tp);
571 set_method_res_type(tp, 0, int_tp);
573 rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
574 rt_Mod.mode = mode_T;
575 rt_Mod.mem_proj_nr = pn_Mod_M;
576 rt_Mod.exc_proj_nr = pn_Mod_X_except;
577 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
578 rt_Mod.res_proj_nr = pn_Mod_res;
580 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
582 map_Mod->kind = INTRINSIC_INSTR;
583 map_Mod->op = op_Mod;
584 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
585 map_Mod->ctx = &rt_Mod;
589 i_instr_record *map_Mod = &records[n_records++].i_instr;
591 tp = new_type_method(ID("rt_uMod"), 2, 1);
592 set_method_param_type(tp, 0, uint_tp);
593 set_method_param_type(tp, 1, uint_tp);
594 set_method_res_type(tp, 0, uint_tp);
596 rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
597 rt_Mod.mode = mode_T;
598 rt_Mod.mem_proj_nr = pn_Mod_M;
599 rt_Mod.exc_proj_nr = pn_Mod_X_except;
600 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
601 rt_Mod.res_proj_nr = pn_Mod_res;
603 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
605 map_Mod->kind = INTRINSIC_INSTR;
606 map_Mod->op = op_Mod;
607 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
608 map_Mod->ctx = &rt_Mod;
612 lower_intrinsics(records, n_records);
615 /*****************************************************************
616 * ____ _ _ _____ _____
617 * | _ \ | | | | |_ _|/ ____| /\
618 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
619 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
620 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
621 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
623 *****************************************************************/
625 static arm_isa_t arm_isa_template = {
626 &arm_isa_if, /* isa interface */
627 &arm_general_purpose_regs[REG_R13], /* stack pointer */
628 &arm_general_purpose_regs[REG_R11], /* base pointer */
629 -1, /* stack direction */
630 0 /* number of codegenerator objects */
634 * Initializes the backend ISA and opens the output file.
636 static void *arm_init(void) {
637 static int inited = 0;
643 isa = xcalloc(1, sizeof(*isa));
644 memcpy(isa, &arm_isa_template, sizeof(*isa));
646 arm_register_init(isa);
647 arm_create_opcodes();
657 * Closes the output file and frees the ISA structure.
659 static void arm_done(void *self) {
665 static int arm_get_n_reg_class(const void *self) {
669 static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
670 assert(i >= 0 && i < N_CLASSES && "Invalid arm register class requested.");
671 return &arm_reg_classes[i];
677 * Get the register class which shall be used to store a value of a given mode.
678 * @param self The this pointer.
679 * @param mode The mode in question.
680 * @return A register class which can hold values of the given mode.
682 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
683 if (mode_is_float(mode))
684 return &arm_reg_classes[CLASS_arm_floating_point];
686 return &arm_reg_classes[CLASS_arm_general_purpose];
692 * Produces the type which sits between the stack args and the locals on the stack.
693 * it will contain the return address and space to store the old base pointer.
694 * @return The Firm type modelling the ABI between type.
696 static ir_type *arm_get_between_type(void *self) {
697 static ir_type *between_type = NULL;
698 static entity *old_bp_ent = NULL;
701 entity *ret_addr_ent;
702 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
703 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
705 between_type = new_type_class(new_id_from_str("arm_between_type"));
706 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
707 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
709 set_entity_offset_bytes(old_bp_ent, 0);
710 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
711 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
725 be_abi_call_flags_bits_t flags;
726 const arch_env_t *arch_env;
727 const arch_isa_t *isa;
731 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
733 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
734 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
735 env->flags = fl.bits;
737 env->arch_env = arch_env;
738 env->isa = arch_env->isa;
742 static void arm_abi_dont_save_regs(void *self, pset *s)
744 arm_abi_env_t *env = self;
745 if(env->flags.try_omit_fp)
746 pset_insert_ptr(s, env->isa->bp);
752 * Build the ARM prolog
754 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
755 ir_node *keep, *store;
756 arm_abi_env_t *env = self;
757 ir_graph *irg = env->irg;
758 ir_node *block = get_irg_start_block(irg);
759 // ir_node *regs[16];
761 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_general_purpose];
762 static const arm_register_req_t *fp_req[] = {
763 &arm_default_req_arm_general_purpose_r11
766 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
767 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R12]);
768 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
769 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R14]);
770 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R15]);
771 // ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R0]);
772 // ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R1]);
773 // ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R2]);
774 // ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R3]);
776 if(env->flags.try_omit_fp)
779 ip = be_new_Copy(gp, irg, block, sp );
780 arch_set_irn_register(env->arch_env, ip, &arm_general_purpose_regs[REG_R12]);
781 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_general_purpose_regs[REG_R12] );
783 // if (r0) regs[n_regs++] = r0;
784 // if (r1) regs[n_regs++] = r1;
785 // if (r2) regs[n_regs++] = r2;
786 // if (r3) regs[n_regs++] = r3;
787 // sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
788 // set_arm_req_out(sp, &arm_default_req_arm_general_purpose_r13, 0);
789 // arch_set_irn_register(env->arch_env, sp, env->isa->sp);
790 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem, mode_T);
791 set_arm_req_out(store, &arm_default_req_arm_general_purpose_r13, 0);
792 // arch_set_irn_register(env->arch_env, store, env->isa->sp);
794 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, 0);
795 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
796 *mem = new_r_Proj(irg, block, store, mode_M, 1);
798 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
799 be_node_set_reg_class(keep, 1, gp);
800 arch_set_irn_register(env->arch_env, keep, &arm_general_purpose_regs[REG_R12]);
801 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_general_purpose_regs[REG_R12] );
803 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp) );
804 set_arm_value(fp, new_tarval_from_long(4, mode_Iu));
805 set_arm_req_out_all(fp, fp_req);
806 //set_arm_req_out(fp, &arm_default_req_arm_general_purpose_r11, 0);
807 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
809 // be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R0], r0);
810 // be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R1], r1);
811 // be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R2], r2);
812 // be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R3], r3);
813 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
814 be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R12], keep);
815 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
816 be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R14], lr);
817 be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R15], pc);
822 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
823 arm_abi_env_t *env = self;
824 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
825 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
826 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R15]);
827 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R14]);
828 static const arm_register_req_t *sub12_req[] = {
829 &arm_default_req_arm_general_purpose_r13
832 // TODO: Activate Omit fp in epilogue
833 if(env->flags.try_omit_fp) {
834 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
836 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_general_purpose], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
837 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_general_purpose]);
838 arch_set_irn_register(env->arch_env, curr_lr, &arm_general_purpose_regs[REG_R14]);
839 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_general_purpose_regs[REG_R14] );
841 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_general_purpose], env->irg, bl, curr_lr );
842 arch_set_irn_register(env->arch_env, curr_pc, &arm_general_purpose_regs[REG_R15]);
843 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_general_purpose_regs[REG_R15] );
847 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu );
848 set_arm_value(sub12_node, new_tarval_from_long(12,mode_Iu));
849 set_arm_req_out_all(sub12_node, sub12_req);
850 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
851 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem, mode_T );
852 set_arm_req_out(load_node, &arm_default_req_arm_general_purpose_r11, 0);
853 set_arm_req_out(load_node, &arm_default_req_arm_general_purpose_r13, 1);
854 set_arm_req_out(load_node, &arm_default_req_arm_general_purpose_r15, 2);
855 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, 0);
856 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, 1);
857 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, 2);
858 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, 3);
859 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
860 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
861 arch_set_irn_register(env->arch_env, curr_pc, &arm_general_purpose_regs[REG_R15]);
863 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
864 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
865 be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R14], curr_lr);
866 be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R15], curr_pc);
869 static const be_abi_callbacks_t arm_abi_callbacks = {
872 arm_get_between_type,
873 arm_abi_dont_save_regs,
880 * Get the ABI restrictions for procedure calls.
881 * @param self The this pointer.
882 * @param method_type The type of the method (procedure) in question.
883 * @param abi The abi object to be modified
885 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
889 int n = get_method_n_params(method_type);
890 be_abi_call_flags_t flags = {
892 0, /* store from left to right */
893 0, /* store arguments sequential */
894 1, /* try to omit the frame pointer */
895 1, /* the function can use any register as frame pointer */
896 1 /* a call can take the callee's address as an immediate */
900 /* set stack parameter passing style */
901 be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
903 for (i = 0; i < n; i++) {
904 /* reg = get reg for param i; */
905 /* be_abi_call_param_reg(abi, i, reg); */
908 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
910 be_abi_call_param_stack(abi, i, 4, 0, 0);
913 /* default: return value is in R0 resp. F0 */
914 assert(get_method_n_ress(method_type) < 2);
915 if (get_method_n_ress(method_type) > 0) {
916 tp = get_method_res_type(method_type, 0);
917 mode = get_type_mode(tp);
919 be_abi_call_res_reg(abi, 0,
920 mode_is_float(mode) ? &arm_floating_point_regs[REG_F0] : &arm_general_purpose_regs[REG_R0]);
924 static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
928 const arch_irn_handler_t arm_irn_handler = {
932 const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
933 return &arm_irn_handler;
936 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
937 return is_arm_irn(irn);
941 * Initializes the code generator interface.
943 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
944 return &arm_code_gen_if;
947 list_sched_selector_t arm_sched_selector;
950 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
952 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self) {
953 memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
954 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
955 return &arm_sched_selector;
959 * Returns the necessary byte alignment for storing a register of given class.
961 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
962 ir_mode *mode = arch_register_class_mode(cls);
963 return get_mode_size_bytes(mode);
967 static void arm_register_options(lc_opt_entry_t *ent)
970 #endif /* WITH_LIBCORE */
972 const arch_isa_if_t arm_isa_if = {
974 arm_register_options,
980 arm_get_reg_class_for_mode,
983 arm_get_code_generator_if,
984 arm_get_list_sched_selector,
985 arm_get_reg_class_alignment