2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Oliver Richter, Tobias Gneist
31 #include "lc_opts_enum.h"
33 #include "pseudo_irg.h"
40 #include "iroptimize.h"
47 #include "../bearch_t.h" /* the general register allocator interface */
48 #include "../benode_t.h"
49 #include "../belower.h"
50 #include "../besched_t.h"
53 #include "../bemachine.h"
54 #include "../beilpsched.h"
55 #include "../bemodule.h"
56 #include "../beirg_t.h"
57 #include "../bespillslots.h"
58 #include "../begnuas.h"
60 #include "bearch_arm_t.h"
62 #include "arm_new_nodes.h" /* arm nodes interface */
63 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
64 #include "arm_transform.h"
65 #include "arm_emitter.h"
66 #include "arm_map_regs.h"
68 #define DEBUG_MODULE "firm.be.arm.isa"
70 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
71 static set *cur_reg_set = NULL;
73 /**************************************************
76 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
77 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
78 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
79 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
82 **************************************************/
85 * Return register requirements for a arm node.
86 * If the node returns a tuple (mode_T) then the proj's
87 * will be asked for this information.
89 static const arch_register_req_t *arm_get_irn_reg_req(const ir_node *node,
92 long node_pos = pos == -1 ? 0 : pos;
93 ir_mode *mode = get_irn_mode(node);
95 if (is_Block(node) || mode == mode_X) {
96 return arch_no_register_req;
99 if (mode == mode_T && pos < 0) {
100 return arch_no_register_req;
105 return arch_no_register_req;
108 return arch_no_register_req;
111 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
112 node = skip_Proj_const(node);
115 /* get requirements for our own nodes */
116 if (is_arm_irn(node)) {
117 const arch_register_req_t *req;
119 req = get_arm_in_req(node, pos);
121 req = get_arm_out_req(node, node_pos);
127 /* unknown should be transformed by now */
128 assert(!is_Unknown(node));
129 return arch_no_register_req;
132 static void arm_set_irn_reg(ir_node *irn, const arch_register_t *reg)
136 if (get_irn_mode(irn) == mode_X) {
141 pos = get_Proj_proj(irn);
142 irn = skip_Proj(irn);
145 if (is_arm_irn(irn)) {
146 const arch_register_t **slots;
148 slots = get_arm_slots(irn);
152 /* here we set the registers for the Phi nodes */
153 arm_set_firm_reg(irn, reg, cur_reg_set);
157 static const arch_register_t *arm_get_irn_reg(const ir_node *irn)
160 const arch_register_t *reg = NULL;
164 if (get_irn_mode(irn) == mode_X) {
168 pos = get_Proj_proj(irn);
169 irn = skip_Proj_const(irn);
172 if (is_arm_irn(irn)) {
173 const arch_register_t **slots;
174 slots = get_arm_slots(irn);
178 reg = arm_get_firm_reg(irn, cur_reg_set);
184 static arch_irn_class_t arm_classify(const ir_node *irn)
186 irn = skip_Proj_const(irn);
189 return arch_irn_class_branch;
191 else if (is_arm_irn(irn)) {
192 return arch_irn_class_normal;
198 static arch_irn_flags_t arm_get_flags(const ir_node *irn)
200 arch_irn_flags_t flags = arch_irn_flags_none;
202 if(is_Unknown(irn)) {
203 return arch_irn_flags_ignore;
206 if (is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
207 ir_node *pred = get_Proj_pred(irn);
208 if (is_arm_irn(pred)) {
209 flags = get_arm_out_flags(pred, get_Proj_proj(irn));
214 if (is_arm_irn(irn)) {
215 flags |= get_arm_flags(irn);
221 static ir_entity *arm_get_frame_entity(const ir_node *irn)
224 /* TODO: return the entity assigned to the frame */
228 static void arm_set_frame_entity(ir_node *irn, ir_entity *ent)
232 /* TODO: set the entity assigned to the frame */
236 * This function is called by the generic backend to correct offsets for
237 * nodes accessing the stack.
239 static void arm_set_stack_bias(ir_node *irn, int bias)
243 /* TODO: correct offset if irn accesses the stack */
246 static int arm_get_sp_bias(const ir_node *irn)
252 /* fill register allocator interface */
254 static const arch_irn_ops_t arm_irn_ops = {
260 arm_get_frame_entity,
261 arm_set_frame_entity,
264 NULL, /* get_inverse */
265 NULL, /* get_op_estimated_cost */
266 NULL, /* possible_memory_operand */
267 NULL, /* perform_memory_operand */
270 /**************************************************
273 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
274 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
275 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
276 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
279 **************************************************/
282 * Transforms the standard Firm graph into
285 static void arm_prepare_graph(void *self) {
286 arm_code_gen_t *cg = self;
288 /* transform nodes into assembler instructions */
289 arm_transform_graph(cg);
291 /* do local optimizations (mainly CSE) */
292 local_optimize_graph(cg->irg);
295 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
297 /* do code placement, to optimize the position of constants */
301 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
305 * Called immediately before emit phase.
307 static void arm_finish_irg(void *self)
310 /* TODO: - fix offsets for nodes accessing stack
317 * These are some hooks which must be filled but are probably not needed.
319 static void arm_before_sched(void *self)
322 /* Some stuff you need to do after scheduling but before register allocation */
325 static void arm_before_ra(void *self)
328 /* Some stuff you need to do immediately after register allocation */
332 * We transform Spill and Reload here. This needs to be done before
333 * stack biasing otherwise we would miss the corrected offset for these nodes.
335 static void arm_after_ra(void *self)
337 arm_code_gen_t *cg = self;
338 be_coalesce_spillslots(cg->birg);
342 * Emits the code, closes the output file and frees
343 * the code generator interface.
345 static void arm_emit_and_done(void *self) {
346 arm_code_gen_t *cg = self;
347 ir_graph *irg = cg->irg;
349 arm_gen_routine(cg, irg);
353 /* de-allocate code generator */
354 del_set(cg->reg_set);
359 * Move a double floating point value into an integer register.
360 * Place the move operation into block bl.
362 * Handle some special cases here:
363 * 1.) A constant: simply split into two
364 * 2.) A load: simply split into two
366 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
367 ir_node **resH, ir_node **resL) {
369 tarval *tv = get_Const_tarval(arg);
372 /* get the upper 32 bits */
373 v = get_tarval_sub_bits(tv, 7);
374 v = (v << 8) | get_tarval_sub_bits(tv, 6);
375 v = (v << 8) | get_tarval_sub_bits(tv, 5);
376 v = (v << 8) | get_tarval_sub_bits(tv, 4);
377 *resH = new_Const_long(mode_Is, v);
379 /* get the lower 32 bits */
380 v = get_tarval_sub_bits(tv, 3);
381 v = (v << 8) | get_tarval_sub_bits(tv, 2);
382 v = (v << 8) | get_tarval_sub_bits(tv, 1);
383 v = (v << 8) | get_tarval_sub_bits(tv, 0);
384 *resL = new_Const_long(mode_Is, v);
386 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
387 /* FIXME: handling of low/high depends on LE/BE here */
391 ir_graph *irg = current_ir_graph;
394 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
396 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
397 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
398 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
404 * Move a single floating point value into an integer register.
405 * Place the move operation into block bl.
407 * Handle some special cases here:
408 * 1.) A constant: simply move
409 * 2.) A load: simply load
411 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg)
416 tarval *tv = get_Const_tarval(arg);
419 /* get the lower 32 bits */
420 v = get_tarval_sub_bits(tv, 3);
421 v = (v << 8) | get_tarval_sub_bits(tv, 2);
422 v = (v << 8) | get_tarval_sub_bits(tv, 1);
423 v = (v << 8) | get_tarval_sub_bits(tv, 0);
424 return new_Const_long(mode_Is, v);
426 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
429 load = skip_Proj(arg);
436 * Convert the arguments of a call to support the
437 * ARM calling convention of general purpose AND floating
440 static void handle_calls(ir_node *call, void *env)
442 arm_code_gen_t *cg = env;
443 int i, j, n, size, idx, flag, n_param, n_res, first_variadic;
444 ir_type *mtp, *new_mtd, *new_tp[5];
445 ir_node *new_in[5], **in;
451 /* check, if we need conversions */
452 n = get_Call_n_params(call);
453 mtp = get_Call_type(call);
454 assert(get_method_n_params(mtp) == n);
456 /* it's always enough to handle the first 4 parameters */
459 flag = size = idx = 0;
460 bl = get_nodes_block(call);
461 for (i = 0; i < n; ++i) {
462 ir_type *param_tp = get_method_param_type(mtp, i);
464 if (is_compound_type(param_tp)) {
465 /* an aggregate parameter: bad case */
469 /* a primitive parameter */
470 ir_mode *mode = get_type_mode(param_tp);
472 if (mode_is_float(mode)) {
473 if (get_mode_size_bits(mode) > 32) {
474 ir_node *mem = get_Call_mem(call);
476 /* Beware: ARM wants the high part first */
478 new_tp[idx] = cg->int_tp;
479 new_tp[idx+1] = cg->int_tp;
480 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
482 set_Call_mem(call, mem);
486 new_tp[idx] = cg->int_tp;
487 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
494 new_tp[idx] = param_tp;
495 new_in[idx] = get_Call_param(call, i);
504 /* if flag is NOT set, no need to translate the method type */
508 /* construct a new method type */
510 n_param = get_method_n_params(mtp) - n + idx;
511 n_res = get_method_n_ress(mtp);
512 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
514 for (i = 0; i < idx; ++i)
515 set_method_param_type(new_mtd, i, new_tp[i]);
516 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
517 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
518 for (i = 0; i < n_res; ++i)
519 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
521 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
522 first_variadic = get_method_first_variadic_param_index(mtp);
523 if (first_variadic >= 0)
524 set_method_first_variadic_param_index(new_mtd, first_variadic);
526 if (is_lowered_type(mtp)) {
527 mtp = get_associated_type(mtp);
529 set_lowered_type(mtp, new_mtd);
531 set_Call_type(call, new_mtd);
533 /* calculate new in array of the Call */
534 NEW_ARR_A(ir_node *, in, n_param + 2);
535 for (i = 0; i < idx; ++i)
536 in[2 + i] = new_in[i];
537 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
538 in[2 + j++] = get_Call_param(call, i);
540 in[0] = get_Call_mem(call);
541 in[1] = get_Call_ptr(call);
543 /* finally, change the call inputs */
544 set_irn_in(call, n_param + 2, in);
548 * Handle graph transformations before the abi converter does its work.
550 static void arm_before_abi(void *self) {
551 arm_code_gen_t *cg = self;
553 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
557 static void *arm_cg_init(be_irg_t *birg);
559 static const arch_code_generator_if_t arm_code_gen_if = {
561 NULL, /* get_pic_base */
562 arm_before_abi, /* before abi introduce */
565 arm_before_sched, /* before scheduling hook */
566 arm_before_ra, /* before register allocation hook */
573 * Initializes the code generator.
575 static void *arm_cg_init(be_irg_t *birg) {
576 static ir_type *int_tp = NULL;
577 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env.isa;
581 /* create an integer type with machine size */
582 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
585 cg = xmalloc(sizeof(*cg));
586 cg->impl = &arm_code_gen_if;
588 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
589 cg->arch_env = &birg->main_env->arch_env;
593 cg->have_fp_insn = 0;
594 cg->unknown_gp = NULL;
595 cg->unknown_fpa = NULL;
596 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
598 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
600 cur_reg_set = cg->reg_set;
602 /* enter the current code generator */
605 return (arch_code_generator_t *)cg;
610 * Maps all intrinsic calls that the backend support
611 * and map all instructions the backend did not support
614 static void arm_handle_intrinsics(void) {
615 ir_type *tp, *int_tp, *uint_tp;
619 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
621 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
623 int_tp = new_type_primitive(ID("int"), mode_Is);
624 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
626 /* ARM has neither a signed div instruction ... */
628 i_instr_record *map_Div = &records[n_records++].i_instr;
630 tp = new_type_method(ID("rt_iDiv"), 2, 1);
631 set_method_param_type(tp, 0, int_tp);
632 set_method_param_type(tp, 1, int_tp);
633 set_method_res_type(tp, 0, int_tp);
635 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
636 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
637 rt_iDiv.mode = mode_T;
638 rt_iDiv.res_mode = mode_Is;
639 rt_iDiv.mem_proj_nr = pn_Div_M;
640 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
641 rt_iDiv.exc_proj_nr = pn_Div_X_except;
642 rt_iDiv.exc_mem_proj_nr = pn_Div_M;
643 rt_iDiv.res_proj_nr = pn_Div_res;
645 set_entity_visibility(rt_iDiv.ent, visibility_external_allocated);
647 map_Div->kind = INTRINSIC_INSTR;
648 map_Div->op = op_Div;
649 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
650 map_Div->ctx = &rt_iDiv;
652 /* ... nor an unsigned div instruction ... */
654 i_instr_record *map_Div = &records[n_records++].i_instr;
656 tp = new_type_method(ID("rt_uDiv"), 2, 1);
657 set_method_param_type(tp, 0, uint_tp);
658 set_method_param_type(tp, 1, uint_tp);
659 set_method_res_type(tp, 0, uint_tp);
661 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
662 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
663 rt_uDiv.mode = mode_T;
664 rt_uDiv.res_mode = mode_Iu;
665 rt_uDiv.mem_proj_nr = pn_Div_M;
666 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
667 rt_uDiv.exc_proj_nr = pn_Div_X_except;
668 rt_uDiv.exc_mem_proj_nr = pn_Div_M;
669 rt_uDiv.res_proj_nr = pn_Div_res;
671 set_entity_visibility(rt_uDiv.ent, visibility_external_allocated);
673 map_Div->kind = INTRINSIC_INSTR;
674 map_Div->op = op_Div;
675 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
676 map_Div->ctx = &rt_uDiv;
678 /* ... nor a signed mod instruction ... */
680 i_instr_record *map_Mod = &records[n_records++].i_instr;
682 tp = new_type_method(ID("rt_iMod"), 2, 1);
683 set_method_param_type(tp, 0, int_tp);
684 set_method_param_type(tp, 1, int_tp);
685 set_method_res_type(tp, 0, int_tp);
687 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
688 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
689 rt_iMod.mode = mode_T;
690 rt_iMod.res_mode = mode_Is;
691 rt_iMod.mem_proj_nr = pn_Mod_M;
692 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
693 rt_iMod.exc_proj_nr = pn_Mod_X_except;
694 rt_iMod.exc_mem_proj_nr = pn_Mod_M;
695 rt_iMod.res_proj_nr = pn_Mod_res;
697 set_entity_visibility(rt_iMod.ent, visibility_external_allocated);
699 map_Mod->kind = INTRINSIC_INSTR;
700 map_Mod->op = op_Mod;
701 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
702 map_Mod->ctx = &rt_iMod;
704 /* ... nor an unsigned mod. */
706 i_instr_record *map_Mod = &records[n_records++].i_instr;
708 tp = new_type_method(ID("rt_uMod"), 2, 1);
709 set_method_param_type(tp, 0, uint_tp);
710 set_method_param_type(tp, 1, uint_tp);
711 set_method_res_type(tp, 0, uint_tp);
713 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
714 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
715 rt_uMod.mode = mode_T;
716 rt_uMod.res_mode = mode_Iu;
717 rt_uMod.mem_proj_nr = pn_Mod_M;
718 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
719 rt_uMod.exc_proj_nr = pn_Mod_X_except;
720 rt_uMod.exc_mem_proj_nr = pn_Mod_M;
721 rt_uMod.res_proj_nr = pn_Mod_res;
723 set_entity_visibility(rt_uMod.ent, visibility_external_allocated);
725 map_Mod->kind = INTRINSIC_INSTR;
726 map_Mod->op = op_Mod;
727 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
728 map_Mod->ctx = &rt_uMod;
732 lower_intrinsics(records, n_records, /*part_block_used=*/0);
735 /*****************************************************************
736 * ____ _ _ _____ _____
737 * | _ \ | | | | |_ _|/ ____| /\
738 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
739 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
740 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
741 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
743 *****************************************************************/
745 static arm_isa_t arm_isa_template = {
747 &arm_isa_if, /* isa interface */
748 &arm_gp_regs[REG_SP], /* stack pointer */
749 &arm_gp_regs[REG_R11], /* base pointer */
750 -1, /* stack direction */
751 1, /* stack alignment for calls */
752 NULL, /* main environment */
754 5, /* reload costs */
756 0, /* use generic register names instead of SP, LR, PC */
757 ARM_FPU_ARCH_FPE, /* FPU architecture */
758 NULL, /* current code generator */
762 * Initializes the backend ISA and opens the output file.
764 static void *arm_init(FILE *file_handle) {
765 static int inited = 0;
771 isa = xmalloc(sizeof(*isa));
772 memcpy(isa, &arm_isa_template, sizeof(*isa));
777 be_emit_init(file_handle);
779 arm_create_opcodes(&arm_irn_ops);
780 arm_handle_intrinsics();
782 /* we mark referenced global entities, so we can only emit those which
783 * are actually referenced. (Note: you mustn't use the type visited flag
784 * elsewhere in the backend)
786 inc_master_type_visited();
795 * Closes the output file and frees the ISA structure.
797 static void arm_done(void *self) {
798 arm_isa_t *isa = self;
800 be_gas_emit_decls(isa->arch_isa.main_env, 1);
808 * Report the number of register classes.
809 * If we don't have fp instructions, report only GP
810 * here to speed up register allocation (and makes dumps
811 * smaller and more readable).
813 static unsigned arm_get_n_reg_class(const void *self) {
819 * Return the register class with requested index.
821 static const arch_register_class_t *arm_get_reg_class(const void *self,
824 assert(i < N_CLASSES);
825 return &arm_reg_classes[i];
829 * Get the register class which shall be used to store a value of a given mode.
830 * @param self The this pointer.
831 * @param mode The mode in question.
832 * @return A register class which can hold values of the given mode.
834 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
836 if (mode_is_float(mode))
837 return &arm_reg_classes[CLASS_arm_fpa];
839 return &arm_reg_classes[CLASS_arm_gp];
843 * Produces the type which sits between the stack args and the locals on the stack.
844 * it will contain the return address and space to store the old base pointer.
845 * @return The Firm type modeling the ABI between type.
847 static ir_type *arm_get_between_type(void *self) {
848 static ir_type *between_type = NULL;
849 static ir_entity *old_bp_ent = NULL;
852 if (between_type == NULL) {
853 ir_entity *ret_addr_ent;
854 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
855 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
857 between_type = new_type_class(new_id_from_str("arm_between_type"));
858 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
859 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
861 set_entity_offset(old_bp_ent, 0);
862 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
863 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
871 be_abi_call_flags_bits_t flags;
872 const arch_env_t *arch_env;
873 const arch_isa_t *isa;
877 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
879 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
880 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
881 env->flags = fl.bits;
883 env->arch_env = arch_env;
884 env->isa = arch_env->isa;
888 static void arm_abi_dont_save_regs(void *self, pset *s)
890 arm_abi_env_t *env = self;
891 if (env->flags.try_omit_fp)
892 pset_insert_ptr(s, env->isa->bp);
898 * Build the ARM prolog
900 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
901 ir_node *keep, *store;
902 arm_abi_env_t *env = self;
903 ir_graph *irg = env->irg;
904 ir_node *block = get_irg_start_block(irg);
905 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
907 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
908 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
909 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
910 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
911 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
913 if (env->flags.try_omit_fp)
916 ip = be_new_Copy(gp, irg, block, sp);
917 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
918 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
920 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
922 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
923 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
924 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
926 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
927 be_node_set_reg_class(keep, 1, gp);
928 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
929 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
931 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp), 4);
932 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
934 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
935 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
936 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
937 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
938 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
944 * Builds the ARM epilogue
946 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
947 arm_abi_env_t *env = self;
948 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
949 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
950 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
951 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
953 // TODO: Activate Omit fp in epilogue
954 if (env->flags.try_omit_fp) {
955 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
956 add_irn_dep(curr_sp, *mem);
958 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
959 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
960 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
961 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
963 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
964 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
965 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
966 be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
970 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, 12);
972 //set_arm_req_out_all(sub12_node, sub12_req);
973 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
974 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
976 //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
977 //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
978 //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
979 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
980 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
981 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
982 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
983 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
984 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
985 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
987 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
988 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
989 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
990 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
993 static const be_abi_callbacks_t arm_abi_callbacks = {
996 arm_get_between_type,
997 arm_abi_dont_save_regs,
1004 * Get the ABI restrictions for procedure calls.
1005 * @param self The this pointer.
1006 * @param method_type The type of the method (procedure) in question.
1007 * @param abi The abi object to be modified
1009 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1013 int n = get_method_n_params(method_type);
1014 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1017 /* set abi flags for calls */
1018 call_flags.bits.left_to_right = 0;
1019 call_flags.bits.store_args_sequential = 0;
1020 /* call_flags.bits.try_omit_fp don't change this we can handle both */
1021 call_flags.bits.fp_free = 0;
1022 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1024 /* set stack parameter passing style */
1025 be_abi_call_set_flags(abi, call_flags, &arm_abi_callbacks);
1027 for (i = 0; i < n; i++) {
1028 /* reg = get reg for param i; */
1029 /* be_abi_call_param_reg(abi, i, reg); */
1031 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1033 tp = get_method_param_type(method_type, i);
1034 mode = get_type_mode(tp);
1035 be_abi_call_param_stack(abi, i, mode, 4, 0, 0);
1039 /* set return registers */
1040 n = get_method_n_ress(method_type);
1042 assert(n <= 2 && "more than two results not supported");
1044 /* In case of 64bit returns, we will have two 32bit values */
1046 tp = get_method_res_type(method_type, 0);
1047 mode = get_type_mode(tp);
1049 assert(!mode_is_float(mode) && "two FP results not supported");
1051 tp = get_method_res_type(method_type, 1);
1052 mode = get_type_mode(tp);
1054 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1056 be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0]);
1057 be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1]);
1058 } else if (n == 1) {
1059 const arch_register_t *reg;
1061 tp = get_method_res_type(method_type, 0);
1062 assert(is_atomic_type(tp));
1063 mode = get_type_mode(tp);
1065 reg = mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0];
1066 be_abi_call_res_reg(abi, 0, reg);
1070 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1072 if(!is_arm_irn(irn))
1079 * Initializes the code generator interface.
1081 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1083 return &arm_code_gen_if;
1086 list_sched_selector_t arm_sched_selector;
1089 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1091 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1093 memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
1094 /* arm_sched_selector.exectime = arm_sched_exectime; */
1095 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1096 return &arm_sched_selector;
1100 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
1106 * Returns the necessary byte alignment for storing a register of given class.
1108 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1111 /* ARM is a 32 bit CPU, no need for other alignment */
1115 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1123 static const be_machine_t *arm_get_machine(const void *self) {
1131 * Return irp irgs in the desired order.
1133 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
1140 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1141 * @return 1 if allowed, 0 otherwise
1143 static int arm_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) {
1144 ir_node *cmp, *cmp_a, *phi;
1148 /* currently Psi support is not implemented */
1151 /* we don't want long long Psi */
1152 #define IS_BAD_PSI_MODE(mode) (!mode_is_float(mode) && get_mode_size_bits(mode) > 32)
1154 if (get_irn_mode(sel) != mode_b)
1157 cmp = get_Proj_pred(sel);
1158 cmp_a = get_Cmp_left(cmp);
1159 mode = get_irn_mode(cmp_a);
1161 if (IS_BAD_PSI_MODE(mode))
1164 /* check the Phi nodes */
1165 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1166 ir_node *pred_i = get_irn_n(phi, i);
1167 ir_node *pred_j = get_irn_n(phi, j);
1168 ir_mode *mode_i = get_irn_mode(pred_i);
1169 ir_mode *mode_j = get_irn_mode(pred_j);
1171 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1175 #undef IS_BAD_PSI_MODE
1181 * Returns the libFirm configuration parameter for this backend.
1183 static const backend_params *arm_get_libfirm_params(void) {
1184 static const ir_settings_if_conv_t ifconv = {
1185 4, /* maxdepth, doesn't matter for Psi-conversion */
1186 arm_is_psi_allowed /* allows or disallows Psi creation for given selector */
1188 static ir_settings_arch_dep_t ad = {
1190 1, /* Muls are fast enough on ARM but ... */
1191 31, /* ... one shift would be possible better */
1192 NULL, /* no evaluator function */
1193 0, /* SMUL is needed, only in Arch M */
1194 0, /* UMUL is needed, only in Arch M */
1195 32, /* SMUL & UMUL available for 32 bit */
1197 static backend_params p = {
1198 1, /* need dword lowering */
1199 0, /* don't support inline assembler yet */
1200 NULL, /* no additional opcodes */
1201 NULL, /* will be set later */
1202 NULL, /* but yet no creator function */
1203 NULL, /* context for create_intrinsic_fkt */
1204 NULL, /* will be set below */
1208 p.if_conv_info = &ifconv;
1212 /* fpu set architectures. */
1213 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1214 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1215 { "fpe", ARM_FPU_ARCH_FPE },
1216 { "fpa", ARM_FPU_ARCH_FPA },
1217 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1218 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1219 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1223 static lc_opt_enum_int_var_t arch_fpu_var = {
1224 &arm_isa_template.fpu_arch, arm_fpu_items
1227 static const lc_opt_table_entry_t arm_options[] = {
1228 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1229 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1233 const arch_isa_if_t arm_isa_if = {
1236 arm_get_n_reg_class,
1238 arm_get_reg_class_for_mode,
1240 arm_get_code_generator_if,
1241 arm_get_list_sched_selector,
1242 arm_get_ilp_sched_selector,
1243 arm_get_reg_class_alignment,
1244 arm_get_libfirm_params,
1245 arm_get_allowed_execution_units,
1250 void be_init_arch_arm(void)
1252 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1253 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1255 lc_opt_add_table(arm_grp, arm_options);
1257 be_register_isa_if("arm", &arm_isa_if);
1259 arm_init_transform();
1263 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);