2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Oliver Richter, Tobias Gneist
30 #include <libcore/lc_opts.h>
31 #include <libcore/lc_opts_enum.h>
33 #include "pseudo_irg.h"
44 #include "../bearch_t.h" /* the general register allocator interface */
45 #include "../benode_t.h"
46 #include "../belower.h"
47 #include "../besched_t.h"
50 #include "../bemachine.h"
51 #include "../beilpsched.h"
52 #include "../bemodule.h"
53 #include "../beirg_t.h"
54 #include "../bespillslots.h"
55 #include "../begnuas.h"
57 #include "bearch_arm_t.h"
59 #include "arm_new_nodes.h" /* arm nodes interface */
60 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
61 #include "arm_transform.h"
62 #include "arm_emitter.h"
63 #include "arm_map_regs.h"
65 #define DEBUG_MODULE "firm.be.arm.isa"
67 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
68 static set *cur_reg_set = NULL;
70 /**************************************************
73 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
74 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
75 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
76 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
79 **************************************************/
82 * Return register requirements for a arm node.
83 * If the node returns a tuple (mode_T) then the proj's
84 * will be asked for this information.
87 arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node,
89 long node_pos = pos == -1 ? 0 : pos;
90 ir_mode *mode = get_irn_mode(node);
91 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
93 if (is_Block(node) || mode == mode_X || mode == mode_M) {
94 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", node));
95 return arch_no_register_req;
98 if (mode == mode_T && pos < 0) {
99 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", node));
100 return arch_no_register_req;
103 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, node));
106 /* in case of a proj, we need to get the correct OUT slot */
107 /* of the node corresponding to the proj number */
109 node_pos = arm_translate_proj_pos(node);
115 node = skip_Proj_const(node);
117 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", node, node_pos));
120 /* get requirements for our own nodes */
121 if (is_arm_irn(node)) {
122 const arch_register_req_t *req;
124 req = get_arm_in_req(node, pos);
126 req = get_arm_out_req(node, node_pos);
129 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", node, pos));
133 /* unknown should be tranformed by now */
134 assert(!is_Unknown(node));
135 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", node));
137 return arch_no_register_req;
140 static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
145 if (get_irn_mode(irn) == mode_X) {
149 pos = arm_translate_proj_pos(irn);
150 irn = skip_Proj(irn);
153 if (is_arm_irn(irn)) {
154 const arch_register_t **slots;
156 slots = get_arm_slots(irn);
160 /* here we set the registers for the Phi nodes */
161 arm_set_firm_reg(irn, reg, cur_reg_set);
165 static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) {
167 const arch_register_t *reg = NULL;
171 if (get_irn_mode(irn) == mode_X) {
175 pos = arm_translate_proj_pos(irn);
176 irn = skip_Proj_const(irn);
179 if (is_arm_irn(irn)) {
180 const arch_register_t **slots;
181 slots = get_arm_slots(irn);
185 reg = arm_get_firm_reg(irn, cur_reg_set);
191 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
192 irn = skip_Proj_const(irn);
195 return arch_irn_class_branch;
197 else if (is_arm_irn(irn)) {
198 return arch_irn_class_normal;
204 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
205 irn = skip_Proj_const(irn);
207 if (is_arm_irn(irn)) {
208 return get_arm_flags(irn);
210 else if (is_Unknown(irn)) {
211 return arch_irn_flags_ignore;
217 static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
218 /* TODO: return the entity assigned to the frame */
222 static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
223 /* TODO: set the entity assigned to the frame */
227 * This function is called by the generic backend to correct offsets for
228 * nodes accessing the stack.
230 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
231 /* TODO: correct offset if irn accesses the stack */
234 static int arm_get_sp_bias(const void *self, const ir_node *irn) {
238 /* fill register allocator interface */
240 static const arch_irn_ops_if_t arm_irn_ops_if = {
246 arm_get_frame_entity,
247 arm_set_frame_entity,
250 NULL, /* get_inverse */
251 NULL, /* get_op_estimated_cost */
252 NULL, /* possible_memory_operand */
253 NULL, /* perform_memory_operand */
256 arm_irn_ops_t arm_irn_ops = {
263 /**************************************************
266 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
267 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
268 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
269 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
272 **************************************************/
275 * Transforms the standard Firm graph into
278 static void arm_prepare_graph(void *self) {
279 arm_code_gen_t *cg = self;
281 arm_register_transformers();
282 irg_walk_blkwise_graph(cg->irg, arm_move_consts, arm_transform_node, cg);
288 * Called immediately before emit phase.
290 static void arm_finish_irg(void *self) {
291 /* TODO: - fix offsets for nodes accessing stack
298 * These are some hooks which must be filled but are probably not needed.
300 static void arm_before_sched(void *self) {
301 /* Some stuff you need to do after scheduling but before register allocation */
304 static void arm_before_ra(void *self) {
305 /* Some stuff you need to do immediately after register allocation */
309 * We transform Spill and Reload here. This needs to be done before
310 * stack biasing otherwise we would miss the corrected offset for these nodes.
312 static void arm_after_ra(void *self) {
313 arm_code_gen_t *cg = self;
314 be_coalesce_spillslots(cg->birg);
318 * Emits the code, closes the output file and frees
319 * the code generator interface.
321 static void arm_emit_and_done(void *self) {
322 arm_code_gen_t *cg = self;
323 ir_graph *irg = cg->irg;
325 dump_ir_block_graph_sched(irg, "-arm-finished");
326 arm_gen_routine(cg, irg);
330 /* de-allocate code generator */
331 del_set(cg->reg_set);
336 * Move a double floating point value into an integer register.
337 * Place the move operation into block bl.
339 * Handle some special cases here:
340 * 1.) A constant: simply split into two
341 * 2.) A load: simply split into two
343 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
344 ir_node **resH, ir_node **resL) {
346 tarval *tv = get_Const_tarval(arg);
349 /* get the upper 32 bits */
350 v = get_tarval_sub_bits(tv, 7);
351 v = (v << 8) | get_tarval_sub_bits(tv, 6);
352 v = (v << 8) | get_tarval_sub_bits(tv, 5);
353 v = (v << 8) | get_tarval_sub_bits(tv, 4);
354 *resH = new_Const_long(mode_Is, v);
356 /* get the lower 32 bits */
357 v = get_tarval_sub_bits(tv, 3);
358 v = (v << 8) | get_tarval_sub_bits(tv, 2);
359 v = (v << 8) | get_tarval_sub_bits(tv, 1);
360 v = (v << 8) | get_tarval_sub_bits(tv, 0);
361 *resL = new_Const_long(mode_Is, v);
363 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
364 /* FIXME: handling of low/high depends on LE/BE here */
368 ir_graph *irg = current_ir_graph;
371 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
373 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
374 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
375 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
381 * Move a single floating point value into an integer register.
382 * Place the move operation into block bl.
384 * Handle some special cases here:
385 * 1.) A constant: simply move
386 * 2.) A load: simply load
388 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) {
390 tarval *tv = get_Const_tarval(arg);
393 /* get the lower 32 bits */
394 v = get_tarval_sub_bits(tv, 3);
395 v = (v << 8) | get_tarval_sub_bits(tv, 2);
396 v = (v << 8) | get_tarval_sub_bits(tv, 1);
397 v = (v << 8) | get_tarval_sub_bits(tv, 0);
398 return new_Const_long(mode_Is, v);
400 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
403 load = skip_Proj(arg);
410 * Convert the arguments of a call to support the
411 * ARM calling convention of general purpose AND floating
414 static void handle_calls(ir_node *call, void *env)
416 arm_code_gen_t *cg = env;
417 int i, j, n, size, idx, flag, n_param, n_res;
418 ir_type *mtp, *new_mtd, *new_tp[5];
419 ir_node *new_in[5], **in;
425 /* check, if we need conversions */
426 n = get_Call_n_params(call);
427 mtp = get_Call_type(call);
428 assert(get_method_n_params(mtp) == n);
430 /* it's always enough to handle the first 4 parameters */
433 flag = size = idx = 0;
434 bl = get_nodes_block(call);
435 for (i = 0; i < n; ++i) {
436 ir_type *param_tp = get_method_param_type(mtp, i);
438 if (is_compound_type(param_tp)) {
439 /* an aggregate parameter: bad case */
443 /* a primitive parameter */
444 ir_mode *mode = get_type_mode(param_tp);
446 if (mode_is_float(mode)) {
447 if (get_mode_size_bits(mode) > 32) {
448 ir_node *mem = get_Call_mem(call);
450 /* Beware: ARM wants the high part first */
452 new_tp[idx] = cg->int_tp;
453 new_tp[idx+1] = cg->int_tp;
454 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
456 set_Call_mem(call, mem);
460 new_tp[idx] = cg->int_tp;
461 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
468 new_tp[idx] = param_tp;
469 new_in[idx] = get_Call_param(call, i);
478 /* if flag is NOT set, no need to translate the method type */
482 /* construct a new method type */
484 n_param = get_method_n_params(mtp) - n + idx;
485 n_res = get_method_n_ress(mtp);
486 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
488 for (i = 0; i < idx; ++i)
489 set_method_param_type(new_mtd, i, new_tp[i]);
490 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
491 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
492 for (i = 0; i < n_res; ++i)
493 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
495 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
496 set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp));
498 if (is_lowered_type(mtp)) {
499 mtp = get_associated_type(mtp);
501 set_lowered_type(mtp, new_mtd);
503 set_Call_type(call, new_mtd);
505 /* calculate new in array of the Call */
506 NEW_ARR_A(ir_node *, in, n_param + 2);
507 for (i = 0; i < idx; ++i)
508 in[2 + i] = new_in[i];
509 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
510 in[2 + j++] = get_Call_param(call, i);
512 in[0] = get_Call_mem(call);
513 in[1] = get_Call_ptr(call);
515 /* finally, change the call inputs */
516 set_irn_in(call, n_param + 2, in);
520 * Handle graph transformations before the abi converter does its work.
522 static void arm_before_abi(void *self) {
523 arm_code_gen_t *cg = self;
525 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
528 static void *arm_cg_init(be_irg_t *birg);
530 static const arch_code_generator_if_t arm_code_gen_if = {
532 arm_before_abi, /* before abi introduce */
535 arm_before_sched, /* before scheduling hook */
536 arm_before_ra, /* before register allocation hook */
543 * Initializes the code generator.
545 static void *arm_cg_init(be_irg_t *birg) {
546 static ir_type *int_tp = NULL;
547 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
551 /* create an integer type with machine size */
552 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
555 cg = xmalloc(sizeof(*cg));
556 cg->impl = &arm_code_gen_if;
558 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
559 cg->arch_env = birg->main_env->arch_env;
565 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
567 cur_reg_set = cg->reg_set;
571 /* enter the current code generator */
574 return (arch_code_generator_t *)cg;
579 * Maps all intrinsic calls that the backend support
580 * and map all instructions the backend did not support
583 static void arm_handle_intrinsics(void) {
584 ir_type *tp, *int_tp, *uint_tp;
588 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
590 int_tp = new_type_primitive(ID("int"), mode_Is);
591 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
593 /* ARM has neither a signed div instruction ... */
596 i_instr_record *map_Div = &records[n_records++].i_instr;
598 tp = new_type_method(ID("rt_iDiv"), 2, 1);
599 set_method_param_type(tp, 0, int_tp);
600 set_method_param_type(tp, 1, int_tp);
601 set_method_res_type(tp, 0, int_tp);
603 rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
604 rt_Div.mode = mode_T;
605 rt_Div.res_mode = mode_Is;
606 rt_Div.mem_proj_nr = pn_Div_M;
607 rt_Div.regular_proj_nr = pn_Div_X_regular;
608 rt_Div.exc_proj_nr = pn_Div_X_except;
609 rt_Div.exc_mem_proj_nr = pn_Div_M;
610 rt_Div.res_proj_nr = pn_Div_res;
612 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
614 map_Div->kind = INTRINSIC_INSTR;
615 map_Div->op = op_Div;
616 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
617 map_Div->ctx = &rt_Div;
619 /* ... nor an unsigned div instruction ... */
622 i_instr_record *map_Div = &records[n_records++].i_instr;
624 tp = new_type_method(ID("rt_uDiv"), 2, 1);
625 set_method_param_type(tp, 0, uint_tp);
626 set_method_param_type(tp, 1, uint_tp);
627 set_method_res_type(tp, 0, uint_tp);
629 rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
630 rt_Div.mode = mode_T;
631 rt_Div.res_mode = mode_Iu;
632 rt_Div.mem_proj_nr = pn_Div_M;
633 rt_Div.regular_proj_nr = pn_Div_X_regular;
634 rt_Div.exc_proj_nr = pn_Div_X_except;
635 rt_Div.exc_mem_proj_nr = pn_Div_M;
636 rt_Div.res_proj_nr = pn_Div_res;
638 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
640 map_Div->kind = INTRINSIC_INSTR;
641 map_Div->op = op_Div;
642 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
643 map_Div->ctx = &rt_Div;
645 /* ... nor a signed mod instruction ... */
648 i_instr_record *map_Mod = &records[n_records++].i_instr;
650 tp = new_type_method(ID("rt_iMod"), 2, 1);
651 set_method_param_type(tp, 0, int_tp);
652 set_method_param_type(tp, 1, int_tp);
653 set_method_res_type(tp, 0, int_tp);
655 rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
656 rt_Mod.mode = mode_T;
657 rt_Mod.res_mode = mode_Is;
658 rt_Mod.mem_proj_nr = pn_Mod_M;
659 rt_Mod.regular_proj_nr = pn_Mod_X_regular;
660 rt_Mod.exc_proj_nr = pn_Mod_X_except;
661 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
662 rt_Mod.res_proj_nr = pn_Mod_res;
664 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
666 map_Mod->kind = INTRINSIC_INSTR;
667 map_Mod->op = op_Mod;
668 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
669 map_Mod->ctx = &rt_Mod;
671 /* ... nor an unsigned mod. */
674 i_instr_record *map_Mod = &records[n_records++].i_instr;
676 tp = new_type_method(ID("rt_uMod"), 2, 1);
677 set_method_param_type(tp, 0, uint_tp);
678 set_method_param_type(tp, 1, uint_tp);
679 set_method_res_type(tp, 0, uint_tp);
681 rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
682 rt_Mod.mode = mode_T;
683 rt_Mod.res_mode = mode_Iu;
684 rt_Mod.mem_proj_nr = pn_Mod_M;
685 rt_Mod.regular_proj_nr = pn_Mod_X_regular;
686 rt_Mod.exc_proj_nr = pn_Mod_X_except;
687 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
688 rt_Mod.res_proj_nr = pn_Mod_res;
690 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
692 map_Mod->kind = INTRINSIC_INSTR;
693 map_Mod->op = op_Mod;
694 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
695 map_Mod->ctx = &rt_Mod;
699 lower_intrinsics(records, n_records);
702 /*****************************************************************
703 * ____ _ _ _____ _____
704 * | _ \ | | | | |_ _|/ ____| /\
705 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
706 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
707 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
708 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
710 *****************************************************************/
712 static arm_isa_t arm_isa_template = {
714 &arm_isa_if, /* isa interface */
715 &arm_gp_regs[REG_SP], /* stack pointer */
716 &arm_gp_regs[REG_R11], /* base pointer */
717 -1, /* stack direction */
718 NULL, /* main environment */
720 5, /* reload costs */
722 0, /* use generic register names instead of SP, LR, PC */
723 ARM_FPU_ARCH_FPE, /* FPU architecture */
724 NULL, /* current code generator */
725 { NULL, }, /* emitter environment */
729 * Initializes the backend ISA and opens the output file.
731 static void *arm_init(FILE *file_handle) {
732 static int inited = 0;
738 isa = xmalloc(sizeof(*isa));
739 memcpy(isa, &arm_isa_template, sizeof(*isa));
741 arm_register_init(isa);
744 be_emit_init_env(&isa->emit, file_handle);
746 arm_create_opcodes();
747 arm_handle_intrinsics();
749 /* we mark referenced global entities, so we can only emit those which
750 * are actually referenced. (Note: you mustn't use the type visited flag
751 * elsewhere in the backend)
753 inc_master_type_visited();
762 * Closes the output file and frees the ISA structure.
764 static void arm_done(void *self) {
765 arm_isa_t *isa = self;
767 be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
769 be_emit_destroy_env(&isa->emit);
775 * Report the number of register classes.
776 * If we don't have fp instructions, report only GP
777 * here to speed up register allocation (and makes dumps
778 * smaller and more readable).
780 static int arm_get_n_reg_class(const void *self) {
781 const arm_isa_t *isa = self;
783 return isa->cg->have_fp ? 2 : 1;
787 * Return the register class with requested index.
789 static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
790 return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa];
794 * Get the register class which shall be used to store a value of a given mode.
795 * @param self The this pointer.
796 * @param mode The mode in question.
797 * @return A register class which can hold values of the given mode.
799 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
800 if (mode_is_float(mode))
801 return &arm_reg_classes[CLASS_arm_fpa];
803 return &arm_reg_classes[CLASS_arm_gp];
807 * Produces the type which sits between the stack args and the locals on the stack.
808 * it will contain the return address and space to store the old base pointer.
809 * @return The Firm type modelling the ABI between type.
811 static ir_type *arm_get_between_type(void *self) {
812 static ir_type *between_type = NULL;
813 static ir_entity *old_bp_ent = NULL;
816 ir_entity *ret_addr_ent;
817 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
818 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
820 between_type = new_type_class(new_id_from_str("arm_between_type"));
821 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
822 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
824 set_entity_offset(old_bp_ent, 0);
825 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
826 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
834 be_abi_call_flags_bits_t flags;
835 const arch_env_t *arch_env;
836 const arch_isa_t *isa;
840 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
842 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
843 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
844 env->flags = fl.bits;
846 env->arch_env = arch_env;
847 env->isa = arch_env->isa;
851 static void arm_abi_dont_save_regs(void *self, pset *s)
853 arm_abi_env_t *env = self;
854 if (env->flags.try_omit_fp)
855 pset_insert_ptr(s, env->isa->bp);
861 * Build the ARM prolog
863 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
864 ir_node *keep, *store;
865 arm_abi_env_t *env = self;
866 ir_graph *irg = env->irg;
867 ir_node *block = get_irg_start_block(irg);
868 // ir_node *regs[16];
870 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
872 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
873 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
874 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
875 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
876 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
877 // ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]);
878 // ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]);
879 // ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]);
880 // ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]);
882 if(env->flags.try_omit_fp)
885 ip = be_new_Copy(gp, irg, block, sp );
886 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
887 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
889 // if (r0) regs[n_regs++] = r0;
890 // if (r1) regs[n_regs++] = r1;
891 // if (r2) regs[n_regs++] = r2;
892 // if (r3) regs[n_regs++] = r3;
893 // sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
894 // set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
895 // arch_set_irn_register(env->arch_env, sp, env->isa->sp);
896 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
898 // set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
899 // arch_set_irn_register(env->arch_env, store, env->isa->sp);
901 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
902 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
903 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
905 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
906 be_node_set_reg_class(keep, 1, gp);
907 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
908 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
910 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
911 new_tarval_from_long(4, get_irn_mode(fp)));
913 //set_arm_req_out_all(fp, fp_req);
914 //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
915 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
917 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
918 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
919 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2);
920 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3);
921 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
922 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
923 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
924 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
925 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
930 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
931 arm_abi_env_t *env = self;
932 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
933 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
934 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
935 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
937 // TODO: Activate Omit fp in epilogue
938 if(env->flags.try_omit_fp) {
939 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
940 add_irn_dep(curr_sp, *mem);
942 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
943 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
944 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
945 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
947 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
948 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
949 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
950 be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
954 tarval *tv = new_tarval_from_long(12,mode_Iu);
955 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
957 //set_arm_req_out_all(sub12_node, sub12_req);
958 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
959 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
961 //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
962 //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
963 //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
964 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
965 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
966 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
967 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
968 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
969 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
970 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
972 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
973 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
974 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
975 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
978 static const be_abi_callbacks_t arm_abi_callbacks = {
981 arm_get_between_type,
982 arm_abi_dont_save_regs,
989 * Get the ABI restrictions for procedure calls.
990 * @param self The this pointer.
991 * @param method_type The type of the method (procedure) in question.
992 * @param abi The abi object to be modified
994 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
998 int n = get_method_n_params(method_type);
999 be_abi_call_flags_t flags = {
1001 0, /* store from left to right */
1002 0, /* store arguments sequential */
1003 1, /* try to omit the frame pointer */
1004 1, /* the function can use any register as frame pointer */
1005 1 /* a call can take the callee's address as an immediate */
1009 /* set stack parameter passing style */
1010 be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
1012 for (i = 0; i < n; i++) {
1013 /* reg = get reg for param i; */
1014 /* be_abi_call_param_reg(abi, i, reg); */
1017 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1019 be_abi_call_param_stack(abi, i, 4, 0, 0);
1022 /* default: return value is in R0 resp. F0 */
1023 assert(get_method_n_ress(method_type) < 2);
1024 if (get_method_n_ress(method_type) > 0) {
1025 tp = get_method_res_type(method_type, 0);
1026 mode = get_type_mode(tp);
1028 be_abi_call_res_reg(abi, 0,
1029 mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]);
1033 static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1034 return &arm_irn_ops;
1037 const arch_irn_handler_t arm_irn_handler = {
1041 const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
1042 return &arm_irn_handler;
1045 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1046 if(!is_arm_irn(irn))
1053 * Initializes the code generator interface.
1055 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1056 return &arm_code_gen_if;
1059 list_sched_selector_t arm_sched_selector;
1062 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1064 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1065 memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1066 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1067 return &arm_sched_selector;
1070 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
1075 * Returns the necessary byte alignment for storing a register of given class.
1077 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1078 ir_mode *mode = arch_register_class_mode(cls);
1079 return get_mode_size_bytes(mode);
1082 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1088 static const be_machine_t *arm_get_machine(const void *self) {
1095 * Return irp irgs in the desired order.
1097 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
1102 * Returns the libFirm configuration parameter for this backend.
1104 static const backend_params *arm_get_libfirm_params(void) {
1105 static arch_dep_params_t ad = {
1107 1, /* Muls are fast enough on ARM but ... */
1108 1, /* ... one shift would be possible better */
1109 0, /* SMUL is needed, only in Arch M*/
1110 0, /* UMUL is needed, only in Arch M */
1111 32, /* SMUL & UMUL available for 32 bit */
1113 static backend_params p = {
1114 1, /* need dword lowering */
1115 0, /* don't support inline assembler yet */
1116 0, /* no different calling conventions */
1117 NULL, /* no additional opcodes */
1118 NULL, /* will be set later */
1119 NULL, /* but yet no creator function */
1120 NULL, /* context for create_intrinsic_fkt */
1121 NULL, /* no if conversion settings */
1128 /* fpu set architectures. */
1129 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1130 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1131 { "fpe", ARM_FPU_ARCH_FPE },
1132 { "fpa", ARM_FPU_ARCH_FPA },
1133 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1134 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1135 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1139 static lc_opt_enum_int_var_t arch_fpu_var = {
1140 &arm_isa_template.fpu_arch, arm_fpu_items
1143 static const lc_opt_table_entry_t arm_options[] = {
1144 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1145 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1149 const arch_isa_if_t arm_isa_if = {
1152 arm_get_n_reg_class,
1154 arm_get_reg_class_for_mode,
1156 arm_get_irn_handler,
1157 arm_get_code_generator_if,
1158 arm_get_list_sched_selector,
1159 arm_get_ilp_sched_selector,
1160 arm_get_reg_class_alignment,
1161 arm_get_libfirm_params,
1162 arm_get_allowed_execution_units,
1167 void be_init_arch_arm(void)
1169 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1170 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1172 lc_opt_add_table(arm_grp, arm_options);
1174 be_register_isa_if("arm", &arm_isa_if);
1177 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);