2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist
29 #include "lc_opts_enum.h"
31 #include "pseudo_irg.h"
38 #include "iroptimize.h"
48 #include "../bearch.h"
49 #include "../benode.h"
50 #include "../belower.h"
51 #include "../besched.h"
53 #include "../bemachine.h"
54 #include "../beilpsched.h"
55 #include "../bemodule.h"
57 #include "../bespillslots.h"
58 #include "../begnuas.h"
59 #include "../belistsched.h"
60 #include "../beflags.h"
62 #include "bearch_arm_t.h"
64 #include "arm_new_nodes.h"
65 #include "gen_arm_regalloc_if.h"
66 #include "arm_transform.h"
67 #include "arm_optimize.h"
68 #include "arm_emitter.h"
69 #include "arm_map_regs.h"
71 static arch_irn_class_t arm_classify(const ir_node *irn)
74 /* TODO: we should mark reload/spill instructions and classify them here */
78 static ir_entity *arm_get_frame_entity(const ir_node *irn)
80 const arm_attr_t *attr = get_arm_attr_const(irn);
82 if (is_arm_FrameAddr(irn)) {
83 const arm_SymConst_attr_t *attr = get_irn_generic_attr_const(irn);
86 if (attr->is_load_store) {
87 const arm_load_store_attr_t *load_store_attr
88 = get_arm_load_store_attr_const(irn);
89 if (load_store_attr->is_frame_entity) {
90 return load_store_attr->entity;
97 * This function is called by the generic backend to correct offsets for
98 * nodes accessing the stack.
100 static void arm_set_stack_bias(ir_node *irn, int bias)
102 if (is_arm_FrameAddr(irn)) {
103 arm_SymConst_attr_t *attr = get_irn_generic_attr(irn);
104 attr->fp_offset += bias;
106 arm_load_store_attr_t *attr = get_arm_load_store_attr(irn);
107 assert(attr->base.is_load_store);
108 attr->offset += bias;
112 static int arm_get_sp_bias(const ir_node *irn)
114 /* We don't have any nodes changing the stack pointer.
115 We probably want to support post-/pre increment/decrement later */
120 /* fill register allocator interface */
122 static const arch_irn_ops_t arm_irn_ops = {
125 arm_get_frame_entity,
128 NULL, /* get_inverse */
129 NULL, /* get_op_estimated_cost */
130 NULL, /* possible_memory_operand */
131 NULL, /* perform_memory_operand */
135 * Transforms the standard Firm graph into
138 static void arm_prepare_graph(void *self)
140 arm_code_gen_t *cg = self;
142 /* transform nodes into assembler instructions */
143 arm_transform_graph(cg);
145 /* do local optimizations (mainly CSE) */
146 local_optimize_graph(cg->irg);
149 dump_ir_graph(cg->irg, "transformed");
151 /* do code placement, to optimize the position of constants */
155 dump_ir_graph(cg->irg, "place");
159 * Called immediately before emit phase.
161 static void arm_finish_irg(void *self)
163 arm_code_gen_t *cg = self;
165 /* do peephole optimizations and fix stack offsets */
166 arm_peephole_optimization(cg);
169 static ir_node *arm_flags_remat(ir_node *node, ir_node *after)
174 if (is_Block(after)) {
177 block = get_nodes_block(after);
179 copy = exact_copy(node);
180 set_nodes_block(copy, block);
181 sched_add_after(after, copy);
185 static void arm_before_ra(void *self)
187 arm_code_gen_t *cg = self;
189 be_sched_fix_flags(cg->irg, &arm_reg_classes[CLASS_arm_flags],
193 static void transform_Reload(ir_node *node)
195 ir_node *block = get_nodes_block(node);
196 dbg_info *dbgi = get_irn_dbg_info(node);
197 ir_node *ptr = get_irn_n(node, be_pos_Reload_frame);
198 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
199 ir_mode *mode = get_irn_mode(node);
200 ir_entity *entity = be_get_frame_entity(node);
201 const arch_register_t *reg;
205 ir_node *sched_point = sched_prev(node);
207 load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true);
208 sched_add_after(sched_point, load);
211 proj = new_rd_Proj(dbgi, load, mode, pn_arm_Ldr_res);
213 reg = arch_get_irn_register(node);
214 arch_set_irn_register(proj, reg);
216 exchange(node, proj);
219 static void transform_Spill(ir_node *node)
221 ir_node *block = get_nodes_block(node);
222 dbg_info *dbgi = get_irn_dbg_info(node);
223 ir_node *ptr = get_irn_n(node, be_pos_Spill_frame);
224 ir_node *mem = new_NoMem();
225 ir_node *val = get_irn_n(node, be_pos_Spill_val);
226 ir_mode *mode = get_irn_mode(val);
227 ir_entity *entity = be_get_frame_entity(node);
228 ir_node *sched_point;
231 sched_point = sched_prev(node);
232 store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0,
236 sched_add_after(sched_point, store);
238 exchange(node, store);
241 static void arm_after_ra_walker(ir_node *block, void *data)
243 ir_node *node, *prev;
246 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
247 prev = sched_prev(node);
249 if (be_is_Reload(node)) {
250 transform_Reload(node);
251 } else if (be_is_Spill(node)) {
252 transform_Spill(node);
257 static void arm_after_ra(void *self)
259 arm_code_gen_t *cg = self;
260 be_coalesce_spillslots(cg->irg);
262 irg_block_walk_graph(cg->irg, NULL, arm_after_ra_walker, NULL);
266 * Emits the code, closes the output file and frees
267 * the code generator interface.
269 static void arm_emit_and_done(void *self)
271 arm_code_gen_t *cg = self;
272 ir_graph *irg = cg->irg;
274 arm_gen_routine(cg, irg);
276 /* de-allocate code generator */
277 del_set(cg->reg_set);
282 static void *arm_cg_init(ir_graph *irg);
284 static const arch_code_generator_if_t arm_code_gen_if = {
286 NULL, /* get_pic_base */
287 NULL, /* before abi introduce */
290 arm_before_ra, /* before register allocation hook */
297 * Initializes the code generator.
299 static void *arm_cg_init(ir_graph *irg)
301 static ir_type *int_tp = NULL;
302 arm_isa_t *isa = (arm_isa_t *) be_get_irg_arch_env(irg);
306 /* create an integer type with machine size */
307 int_tp = new_type_primitive(mode_Is);
310 cg = XMALLOC(arm_code_gen_t);
311 cg->impl = &arm_code_gen_if;
313 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
316 cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
318 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
320 /* enter the current code generator */
323 return (arch_code_generator_t *)cg;
328 * Maps all intrinsic calls that the backend support
329 * and map all instructions the backend did not support
332 static void arm_handle_intrinsics(void)
334 ir_type *tp, *int_tp, *uint_tp;
338 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
340 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
342 int_tp = new_type_primitive(mode_Is);
343 uint_tp = new_type_primitive(mode_Iu);
345 /* ARM has neither a signed div instruction ... */
347 i_instr_record *map_Div = &records[n_records++].i_instr;
349 tp = new_type_method(2, 1);
350 set_method_param_type(tp, 0, int_tp);
351 set_method_param_type(tp, 1, int_tp);
352 set_method_res_type(tp, 0, int_tp);
354 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
355 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
356 rt_iDiv.mode = mode_T;
357 rt_iDiv.res_mode = mode_Is;
358 rt_iDiv.mem_proj_nr = pn_Div_M;
359 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
360 rt_iDiv.exc_proj_nr = pn_Div_X_except;
361 rt_iDiv.exc_mem_proj_nr = pn_Div_M;
362 rt_iDiv.res_proj_nr = pn_Div_res;
364 add_entity_linkage(rt_iDiv.ent, IR_LINKAGE_CONSTANT);
365 set_entity_visibility(rt_iDiv.ent, ir_visibility_external);
367 map_Div->kind = INTRINSIC_INSTR;
368 map_Div->op = op_Div;
369 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
370 map_Div->ctx = &rt_iDiv;
372 /* ... nor an unsigned div instruction ... */
374 i_instr_record *map_Div = &records[n_records++].i_instr;
376 tp = new_type_method(2, 1);
377 set_method_param_type(tp, 0, uint_tp);
378 set_method_param_type(tp, 1, uint_tp);
379 set_method_res_type(tp, 0, uint_tp);
381 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
382 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
383 rt_uDiv.mode = mode_T;
384 rt_uDiv.res_mode = mode_Iu;
385 rt_uDiv.mem_proj_nr = pn_Div_M;
386 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
387 rt_uDiv.exc_proj_nr = pn_Div_X_except;
388 rt_uDiv.exc_mem_proj_nr = pn_Div_M;
389 rt_uDiv.res_proj_nr = pn_Div_res;
391 set_entity_visibility(rt_uDiv.ent, ir_visibility_external);
393 map_Div->kind = INTRINSIC_INSTR;
394 map_Div->op = op_Div;
395 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
396 map_Div->ctx = &rt_uDiv;
398 /* ... nor a signed mod instruction ... */
400 i_instr_record *map_Mod = &records[n_records++].i_instr;
402 tp = new_type_method(2, 1);
403 set_method_param_type(tp, 0, int_tp);
404 set_method_param_type(tp, 1, int_tp);
405 set_method_res_type(tp, 0, int_tp);
407 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
408 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
409 rt_iMod.mode = mode_T;
410 rt_iMod.res_mode = mode_Is;
411 rt_iMod.mem_proj_nr = pn_Mod_M;
412 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
413 rt_iMod.exc_proj_nr = pn_Mod_X_except;
414 rt_iMod.exc_mem_proj_nr = pn_Mod_M;
415 rt_iMod.res_proj_nr = pn_Mod_res;
417 set_entity_visibility(rt_iMod.ent, ir_visibility_external);
419 map_Mod->kind = INTRINSIC_INSTR;
420 map_Mod->op = op_Mod;
421 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
422 map_Mod->ctx = &rt_iMod;
424 /* ... nor an unsigned mod. */
426 i_instr_record *map_Mod = &records[n_records++].i_instr;
428 tp = new_type_method(2, 1);
429 set_method_param_type(tp, 0, uint_tp);
430 set_method_param_type(tp, 1, uint_tp);
431 set_method_res_type(tp, 0, uint_tp);
433 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
434 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
435 rt_uMod.mode = mode_T;
436 rt_uMod.res_mode = mode_Iu;
437 rt_uMod.mem_proj_nr = pn_Mod_M;
438 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
439 rt_uMod.exc_proj_nr = pn_Mod_X_except;
440 rt_uMod.exc_mem_proj_nr = pn_Mod_M;
441 rt_uMod.res_proj_nr = pn_Mod_res;
443 set_entity_visibility(rt_uMod.ent, ir_visibility_external);
445 map_Mod->kind = INTRINSIC_INSTR;
446 map_Mod->op = op_Mod;
447 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
448 map_Mod->ctx = &rt_uMod;
452 lower_intrinsics(records, n_records, /*part_block_used=*/0);
456 static arm_isa_t arm_isa_template = {
458 &arm_isa_if, /* isa interface */
459 &arm_gp_regs[REG_SP], /* stack pointer */
460 &arm_gp_regs[REG_R11], /* base pointer */
461 &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */
462 -1, /* stack direction */
463 2, /* power of two stack alignment for calls, 2^2 == 4 */
464 NULL, /* main environment */
466 5, /* reload costs */
467 true, /* we do have custom abi handling */
469 0, /* use generic register names instead of SP, LR, PC */
470 ARM_FPU_ARCH_FPE, /* FPU architecture */
471 NULL, /* current code generator */
475 * Initializes the backend ISA and opens the output file.
477 static arch_env_t *arm_init(FILE *file_handle)
479 static int inited = 0;
485 isa = XMALLOC(arm_isa_t);
486 memcpy(isa, &arm_isa_template, sizeof(*isa));
491 be_emit_init(file_handle);
493 arm_create_opcodes(&arm_irn_ops);
494 arm_handle_intrinsics();
496 be_gas_emit_types = false;
498 /* needed for the debug support */
499 be_gas_emit_switch_section(GAS_SECTION_TEXT);
500 be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
501 be_emit_write_line();
504 return &isa->arch_env;
510 * Closes the output file and frees the ISA structure.
512 static void arm_done(void *self)
514 arm_isa_t *isa = self;
516 be_gas_emit_decls(isa->arch_env.main_env);
524 * Report the number of register classes.
525 * If we don't have fp instructions, report only GP
526 * here to speed up register allocation (and makes dumps
527 * smaller and more readable).
529 static unsigned arm_get_n_reg_class(void)
535 * Return the register class with requested index.
537 static const arch_register_class_t *arm_get_reg_class(unsigned i)
539 assert(i < N_CLASSES);
540 return &arm_reg_classes[i];
544 * Get the register class which shall be used to store a value of a given mode.
545 * @param self The this pointer.
546 * @param mode The mode in question.
547 * @return A register class which can hold values of the given mode.
549 static const arch_register_class_t *arm_get_reg_class_for_mode(const ir_mode *mode)
551 if (mode_is_float(mode))
552 return &arm_reg_classes[CLASS_arm_fpa];
554 return &arm_reg_classes[CLASS_arm_gp];
557 static int arm_to_appear_in_schedule(void *block_env, const ir_node *irn)
560 if (!is_arm_irn(irn))
567 * Initializes the code generator interface.
569 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self)
572 return &arm_code_gen_if;
575 list_sched_selector_t arm_sched_selector;
578 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
580 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector)
583 memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
584 /* arm_sched_selector.exectime = arm_sched_exectime; */
585 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
586 return &arm_sched_selector;
590 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self)
597 * Returns the necessary byte alignment for storing a register of given class.
599 static int arm_get_reg_class_alignment(const arch_register_class_t *cls)
602 /* ARM is a 32 bit CPU, no need for other alignment */
606 static const be_execution_unit_t ***arm_get_allowed_execution_units(const ir_node *irn)
610 panic("Unimplemented arm_get_allowed_execution_units()");
613 static const be_machine_t *arm_get_machine(const void *self)
617 panic("Unimplemented arm_get_machine()");
621 * Return irp irgs in the desired order.
623 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list)
631 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
632 * @return 1 if allowed, 0 otherwise
634 static int arm_is_mux_allowed(ir_node *sel, ir_node *mux_false,
644 static asm_constraint_flags_t arm_parse_asm_constraint(const char **c)
646 /* asm not supported */
648 return ASM_CONSTRAINT_FLAG_INVALID;
651 static int arm_is_valid_clobber(const char *clobber)
658 * Returns the libFirm configuration parameter for this backend.
660 static const backend_params *arm_get_libfirm_params(void)
662 static const ir_settings_if_conv_t ifconv = {
663 4, /* maxdepth, doesn't matter for Psi-conversion */
664 arm_is_mux_allowed /* allows or disallows Mux creation for given selector */
666 static ir_settings_arch_dep_t ad = {
668 1, /* Muls are fast enough on ARM but ... */
669 31, /* ... one shift would be possible better */
670 NULL, /* no evaluator function */
671 0, /* SMUL is needed, only in Arch M */
672 0, /* UMUL is needed, only in Arch M */
673 32, /* SMUL & UMUL available for 32 bit */
675 static backend_params p = {
676 1, /* need dword lowering */
677 0, /* don't support inline assembler yet */
678 NULL, /* will be set later */
679 NULL, /* but yet no creator function */
680 NULL, /* context for create_intrinsic_fkt */
681 NULL, /* ifconv_info will be set below */
682 NULL, /* float arithmetic mode (TODO) */
683 0, /* no trampoline support: size 0 */
684 0, /* no trampoline support: align 0 */
685 NULL, /* no trampoline support: no trampoline builder */
686 4 /* alignment of stack parameter */
690 p.if_conv_info = &ifconv;
694 /* fpu set architectures. */
695 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
696 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
697 { "fpe", ARM_FPU_ARCH_FPE },
698 { "fpa", ARM_FPU_ARCH_FPA },
699 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
700 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
701 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
705 static lc_opt_enum_int_var_t arch_fpu_var = {
706 &arm_isa_template.fpu_arch, arm_fpu_items
709 static const lc_opt_table_entry_t arm_options[] = {
710 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
711 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
715 const arch_isa_if_t arm_isa_if = {
718 NULL, /* handle_intrinsics */
721 arm_get_reg_class_for_mode,
723 arm_get_code_generator_if,
724 arm_get_list_sched_selector,
725 arm_get_ilp_sched_selector,
726 arm_get_reg_class_alignment,
727 arm_get_libfirm_params,
728 arm_get_allowed_execution_units,
731 NULL, /* mark remat */
732 arm_parse_asm_constraint,
736 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);
737 void be_init_arch_arm(void)
739 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
740 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
742 lc_opt_add_table(arm_grp, arm_options);
744 be_register_isa_if("arm", &arm_isa_if);
746 arm_init_transform();