2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Oliver Richter, Tobias Gneist
30 #include <libcore/lc_opts.h>
31 #include <libcore/lc_opts_enum.h>
33 #include "pseudo_irg.h"
45 #include "../bearch_t.h" /* the general register allocator interface */
46 #include "../benode_t.h"
47 #include "../belower.h"
48 #include "../besched_t.h"
51 #include "../bemachine.h"
52 #include "../beilpsched.h"
53 #include "../bemodule.h"
54 #include "../beirg_t.h"
55 #include "../bespillslots.h"
56 #include "../begnuas.h"
58 #include "bearch_arm_t.h"
60 #include "arm_new_nodes.h" /* arm nodes interface */
61 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
62 #include "arm_transform.h"
63 #include "arm_emitter.h"
64 #include "arm_map_regs.h"
66 #define DEBUG_MODULE "firm.be.arm.isa"
68 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
69 static set *cur_reg_set = NULL;
71 /**************************************************
74 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
75 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
76 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
77 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
80 **************************************************/
83 * Return register requirements for a arm node.
84 * If the node returns a tuple (mode_T) then the proj's
85 * will be asked for this information.
88 arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node,
91 long node_pos = pos == -1 ? 0 : pos;
92 ir_mode *mode = get_irn_mode(node);
95 if (is_Block(node) || mode == mode_X || mode == mode_M) {
96 return arch_no_register_req;
99 if (mode == mode_T && pos < 0) {
100 return arch_no_register_req;
104 /* in case of a proj, we need to get the correct OUT slot */
105 /* of the node corresponding to the proj number */
107 return arch_no_register_req;
110 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
111 node = skip_Proj_const(node);
114 /* get requirements for our own nodes */
115 if (is_arm_irn(node)) {
116 const arch_register_req_t *req;
118 req = get_arm_in_req(node, pos);
120 req = get_arm_out_req(node, node_pos);
126 /* unknown should be transformed by now */
127 assert(!is_Unknown(node));
128 return arch_no_register_req;
131 static void arm_set_irn_reg(const void *self, ir_node *irn,
132 const arch_register_t *reg)
137 if (get_irn_mode(irn) == mode_X) {
142 pos = get_Proj_proj(irn);
143 irn = skip_Proj(irn);
146 if (is_arm_irn(irn)) {
147 const arch_register_t **slots;
149 slots = get_arm_slots(irn);
153 /* here we set the registers for the Phi nodes */
154 arm_set_firm_reg(irn, reg, cur_reg_set);
158 static const arch_register_t *arm_get_irn_reg(const void *self,
162 const arch_register_t *reg = NULL;
167 if (get_irn_mode(irn) == mode_X) {
171 pos = get_Proj_proj(irn);
172 irn = skip_Proj_const(irn);
175 if (is_arm_irn(irn)) {
176 const arch_register_t **slots;
177 slots = get_arm_slots(irn);
181 reg = arm_get_firm_reg(irn, cur_reg_set);
187 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn)
190 irn = skip_Proj_const(irn);
193 return arch_irn_class_branch;
195 else if (is_arm_irn(irn)) {
196 return arch_irn_class_normal;
202 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn)
205 irn = skip_Proj_const(irn);
207 if (is_arm_irn(irn)) {
208 return get_arm_flags(irn);
210 else if (is_Unknown(irn)) {
211 return arch_irn_flags_ignore;
217 static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn)
221 /* TODO: return the entity assigned to the frame */
225 static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent)
230 /* TODO: set the entity assigned to the frame */
234 * This function is called by the generic backend to correct offsets for
235 * nodes accessing the stack.
237 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias)
242 /* TODO: correct offset if irn accesses the stack */
245 static int arm_get_sp_bias(const void *self, const ir_node *irn)
252 /* fill register allocator interface */
254 static const arch_irn_ops_if_t arm_irn_ops_if = {
260 arm_get_frame_entity,
261 arm_set_frame_entity,
264 NULL, /* get_inverse */
265 NULL, /* get_op_estimated_cost */
266 NULL, /* possible_memory_operand */
267 NULL, /* perform_memory_operand */
270 arm_irn_ops_t arm_irn_ops = {
277 /**************************************************
280 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
281 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
282 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
283 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
286 **************************************************/
289 * Transforms the standard Firm graph into
292 static void arm_prepare_graph(void *self) {
293 arm_code_gen_t *cg = self;
295 /* transform nodes into assembler instructions */
296 arm_transform_graph(cg);
298 /* do local optimizations (mainly CSE) */
299 local_optimize_graph(cg->irg);
302 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
304 /* do code placement, to optimize the position of constants */
308 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
312 * Called immediately before emit phase.
314 static void arm_finish_irg(void *self)
317 /* TODO: - fix offsets for nodes accessing stack
324 * These are some hooks which must be filled but are probably not needed.
326 static void arm_before_sched(void *self)
329 /* Some stuff you need to do after scheduling but before register allocation */
332 static void arm_before_ra(void *self)
335 /* Some stuff you need to do immediately after register allocation */
339 * We transform Spill and Reload here. This needs to be done before
340 * stack biasing otherwise we would miss the corrected offset for these nodes.
342 static void arm_after_ra(void *self)
344 arm_code_gen_t *cg = self;
345 be_coalesce_spillslots(cg->birg);
349 * Emits the code, closes the output file and frees
350 * the code generator interface.
352 static void arm_emit_and_done(void *self) {
353 arm_code_gen_t *cg = self;
354 ir_graph *irg = cg->irg;
356 arm_gen_routine(cg, irg);
360 /* de-allocate code generator */
361 del_set(cg->reg_set);
366 * Move a double floating point value into an integer register.
367 * Place the move operation into block bl.
369 * Handle some special cases here:
370 * 1.) A constant: simply split into two
371 * 2.) A load: simply split into two
373 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
374 ir_node **resH, ir_node **resL) {
376 tarval *tv = get_Const_tarval(arg);
379 /* get the upper 32 bits */
380 v = get_tarval_sub_bits(tv, 7);
381 v = (v << 8) | get_tarval_sub_bits(tv, 6);
382 v = (v << 8) | get_tarval_sub_bits(tv, 5);
383 v = (v << 8) | get_tarval_sub_bits(tv, 4);
384 *resH = new_Const_long(mode_Is, v);
386 /* get the lower 32 bits */
387 v = get_tarval_sub_bits(tv, 3);
388 v = (v << 8) | get_tarval_sub_bits(tv, 2);
389 v = (v << 8) | get_tarval_sub_bits(tv, 1);
390 v = (v << 8) | get_tarval_sub_bits(tv, 0);
391 *resL = new_Const_long(mode_Is, v);
393 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
394 /* FIXME: handling of low/high depends on LE/BE here */
398 ir_graph *irg = current_ir_graph;
401 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
403 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
404 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
405 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
411 * Move a single floating point value into an integer register.
412 * Place the move operation into block bl.
414 * Handle some special cases here:
415 * 1.) A constant: simply move
416 * 2.) A load: simply load
418 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg)
423 tarval *tv = get_Const_tarval(arg);
426 /* get the lower 32 bits */
427 v = get_tarval_sub_bits(tv, 3);
428 v = (v << 8) | get_tarval_sub_bits(tv, 2);
429 v = (v << 8) | get_tarval_sub_bits(tv, 1);
430 v = (v << 8) | get_tarval_sub_bits(tv, 0);
431 return new_Const_long(mode_Is, v);
433 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
436 load = skip_Proj(arg);
443 * Convert the arguments of a call to support the
444 * ARM calling convention of general purpose AND floating
447 static void handle_calls(ir_node *call, void *env)
449 arm_code_gen_t *cg = env;
450 int i, j, n, size, idx, flag, n_param, n_res, first_variadic;
451 ir_type *mtp, *new_mtd, *new_tp[5];
452 ir_node *new_in[5], **in;
458 /* check, if we need conversions */
459 n = get_Call_n_params(call);
460 mtp = get_Call_type(call);
461 assert(get_method_n_params(mtp) == n);
463 /* it's always enough to handle the first 4 parameters */
466 flag = size = idx = 0;
467 bl = get_nodes_block(call);
468 for (i = 0; i < n; ++i) {
469 ir_type *param_tp = get_method_param_type(mtp, i);
471 if (is_compound_type(param_tp)) {
472 /* an aggregate parameter: bad case */
476 /* a primitive parameter */
477 ir_mode *mode = get_type_mode(param_tp);
479 if (mode_is_float(mode)) {
480 if (get_mode_size_bits(mode) > 32) {
481 ir_node *mem = get_Call_mem(call);
483 /* Beware: ARM wants the high part first */
485 new_tp[idx] = cg->int_tp;
486 new_tp[idx+1] = cg->int_tp;
487 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
489 set_Call_mem(call, mem);
493 new_tp[idx] = cg->int_tp;
494 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
501 new_tp[idx] = param_tp;
502 new_in[idx] = get_Call_param(call, i);
511 /* if flag is NOT set, no need to translate the method type */
515 /* construct a new method type */
517 n_param = get_method_n_params(mtp) - n + idx;
518 n_res = get_method_n_ress(mtp);
519 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
521 for (i = 0; i < idx; ++i)
522 set_method_param_type(new_mtd, i, new_tp[i]);
523 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
524 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
525 for (i = 0; i < n_res; ++i)
526 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
528 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
529 first_variadic = get_method_first_variadic_param_index(mtp);
530 if (first_variadic >= 0)
531 set_method_first_variadic_param_index(new_mtd, first_variadic);
533 if (is_lowered_type(mtp)) {
534 mtp = get_associated_type(mtp);
536 set_lowered_type(mtp, new_mtd);
538 set_Call_type(call, new_mtd);
540 /* calculate new in array of the Call */
541 NEW_ARR_A(ir_node *, in, n_param + 2);
542 for (i = 0; i < idx; ++i)
543 in[2 + i] = new_in[i];
544 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
545 in[2 + j++] = get_Call_param(call, i);
547 in[0] = get_Call_mem(call);
548 in[1] = get_Call_ptr(call);
550 /* finally, change the call inputs */
551 set_irn_in(call, n_param + 2, in);
555 * Handle graph transformations before the abi converter does its work.
557 static void arm_before_abi(void *self) {
558 arm_code_gen_t *cg = self;
560 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
564 static void *arm_cg_init(be_irg_t *birg);
566 static const arch_code_generator_if_t arm_code_gen_if = {
568 arm_before_abi, /* before abi introduce */
571 arm_before_sched, /* before scheduling hook */
572 arm_before_ra, /* before register allocation hook */
579 * Initializes the code generator.
581 static void *arm_cg_init(be_irg_t *birg) {
582 static ir_type *int_tp = NULL;
583 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
587 /* create an integer type with machine size */
588 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
591 cg = xmalloc(sizeof(*cg));
592 cg->impl = &arm_code_gen_if;
594 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
595 cg->arch_env = birg->main_env->arch_env;
599 cg->have_fp_insn = 0;
600 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
602 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
604 cur_reg_set = cg->reg_set;
608 /* enter the current code generator */
611 return (arch_code_generator_t *)cg;
616 * Maps all intrinsic calls that the backend support
617 * and map all instructions the backend did not support
620 static void arm_handle_intrinsics(void) {
621 ir_type *tp, *int_tp, *uint_tp;
625 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
627 int_tp = new_type_primitive(ID("int"), mode_Is);
628 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
630 /* ARM has neither a signed div instruction ... */
633 i_instr_record *map_Div = &records[n_records++].i_instr;
635 tp = new_type_method(ID("rt_iDiv"), 2, 1);
636 set_method_param_type(tp, 0, int_tp);
637 set_method_param_type(tp, 1, int_tp);
638 set_method_res_type(tp, 0, int_tp);
640 rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
641 rt_Div.mode = mode_T;
642 rt_Div.res_mode = mode_Is;
643 rt_Div.mem_proj_nr = pn_Div_M;
644 rt_Div.regular_proj_nr = pn_Div_X_regular;
645 rt_Div.exc_proj_nr = pn_Div_X_except;
646 rt_Div.exc_mem_proj_nr = pn_Div_M;
647 rt_Div.res_proj_nr = pn_Div_res;
649 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
651 map_Div->kind = INTRINSIC_INSTR;
652 map_Div->op = op_Div;
653 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
654 map_Div->ctx = &rt_Div;
656 /* ... nor an unsigned div instruction ... */
659 i_instr_record *map_Div = &records[n_records++].i_instr;
661 tp = new_type_method(ID("rt_uDiv"), 2, 1);
662 set_method_param_type(tp, 0, uint_tp);
663 set_method_param_type(tp, 1, uint_tp);
664 set_method_res_type(tp, 0, uint_tp);
666 rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
667 rt_Div.mode = mode_T;
668 rt_Div.res_mode = mode_Iu;
669 rt_Div.mem_proj_nr = pn_Div_M;
670 rt_Div.regular_proj_nr = pn_Div_X_regular;
671 rt_Div.exc_proj_nr = pn_Div_X_except;
672 rt_Div.exc_mem_proj_nr = pn_Div_M;
673 rt_Div.res_proj_nr = pn_Div_res;
675 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
677 map_Div->kind = INTRINSIC_INSTR;
678 map_Div->op = op_Div;
679 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
680 map_Div->ctx = &rt_Div;
682 /* ... nor a signed mod instruction ... */
685 i_instr_record *map_Mod = &records[n_records++].i_instr;
687 tp = new_type_method(ID("rt_iMod"), 2, 1);
688 set_method_param_type(tp, 0, int_tp);
689 set_method_param_type(tp, 1, int_tp);
690 set_method_res_type(tp, 0, int_tp);
692 rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
693 rt_Mod.mode = mode_T;
694 rt_Mod.res_mode = mode_Is;
695 rt_Mod.mem_proj_nr = pn_Mod_M;
696 rt_Mod.regular_proj_nr = pn_Mod_X_regular;
697 rt_Mod.exc_proj_nr = pn_Mod_X_except;
698 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
699 rt_Mod.res_proj_nr = pn_Mod_res;
701 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
703 map_Mod->kind = INTRINSIC_INSTR;
704 map_Mod->op = op_Mod;
705 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
706 map_Mod->ctx = &rt_Mod;
708 /* ... nor an unsigned mod. */
711 i_instr_record *map_Mod = &records[n_records++].i_instr;
713 tp = new_type_method(ID("rt_uMod"), 2, 1);
714 set_method_param_type(tp, 0, uint_tp);
715 set_method_param_type(tp, 1, uint_tp);
716 set_method_res_type(tp, 0, uint_tp);
718 rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
719 rt_Mod.mode = mode_T;
720 rt_Mod.res_mode = mode_Iu;
721 rt_Mod.mem_proj_nr = pn_Mod_M;
722 rt_Mod.regular_proj_nr = pn_Mod_X_regular;
723 rt_Mod.exc_proj_nr = pn_Mod_X_except;
724 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
725 rt_Mod.res_proj_nr = pn_Mod_res;
727 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
729 map_Mod->kind = INTRINSIC_INSTR;
730 map_Mod->op = op_Mod;
731 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
732 map_Mod->ctx = &rt_Mod;
736 lower_intrinsics(records, n_records);
739 /*****************************************************************
740 * ____ _ _ _____ _____
741 * | _ \ | | | | |_ _|/ ____| /\
742 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
743 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
744 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
745 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
747 *****************************************************************/
749 static arm_isa_t arm_isa_template = {
751 &arm_isa_if, /* isa interface */
752 &arm_gp_regs[REG_SP], /* stack pointer */
753 &arm_gp_regs[REG_R11], /* base pointer */
754 -1, /* stack direction */
755 NULL, /* main environment */
757 5, /* reload costs */
759 0, /* use generic register names instead of SP, LR, PC */
760 ARM_FPU_ARCH_FPE, /* FPU architecture */
761 NULL, /* current code generator */
762 NULL_EMITTER, /* emitter environment */
766 * Initializes the backend ISA and opens the output file.
768 static void *arm_init(FILE *file_handle) {
769 static int inited = 0;
775 isa = xmalloc(sizeof(*isa));
776 memcpy(isa, &arm_isa_template, sizeof(*isa));
781 be_emit_init_env(&isa->emit, file_handle);
783 arm_create_opcodes();
784 arm_register_copy_attr_func();
785 arm_handle_intrinsics();
787 /* we mark referenced global entities, so we can only emit those which
788 * are actually referenced. (Note: you mustn't use the type visited flag
789 * elsewhere in the backend)
791 inc_master_type_visited();
800 * Closes the output file and frees the ISA structure.
802 static void arm_done(void *self) {
803 arm_isa_t *isa = self;
805 be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
807 be_emit_destroy_env(&isa->emit);
813 * Report the number of register classes.
814 * If we don't have fp instructions, report only GP
815 * here to speed up register allocation (and makes dumps
816 * smaller and more readable).
818 static int arm_get_n_reg_class(const void *self) {
819 const arm_isa_t *isa = self;
821 /* ARGH! is called BEFORE transform */
823 return isa->cg->have_fp_insn ? 2 : 1;
827 * Return the register class with requested index.
829 static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
831 return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa];
835 * Get the register class which shall be used to store a value of a given mode.
836 * @param self The this pointer.
837 * @param mode The mode in question.
838 * @return A register class which can hold values of the given mode.
840 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
841 if (mode_is_float(mode))
842 return &arm_reg_classes[CLASS_arm_fpa];
844 return &arm_reg_classes[CLASS_arm_gp];
848 * Produces the type which sits between the stack args and the locals on the stack.
849 * it will contain the return address and space to store the old base pointer.
850 * @return The Firm type modelling the ABI between type.
852 static ir_type *arm_get_between_type(void *self) {
853 static ir_type *between_type = NULL;
854 static ir_entity *old_bp_ent = NULL;
857 ir_entity *ret_addr_ent;
858 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
859 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
861 between_type = new_type_class(new_id_from_str("arm_between_type"));
862 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
863 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
865 set_entity_offset(old_bp_ent, 0);
866 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
867 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
875 be_abi_call_flags_bits_t flags;
876 const arch_env_t *arch_env;
877 const arch_isa_t *isa;
881 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
883 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
884 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
885 env->flags = fl.bits;
887 env->arch_env = arch_env;
888 env->isa = arch_env->isa;
892 static void arm_abi_dont_save_regs(void *self, pset *s)
894 arm_abi_env_t *env = self;
895 if (env->flags.try_omit_fp)
896 pset_insert_ptr(s, env->isa->bp);
902 * Build the ARM prolog
904 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
905 ir_node *keep, *store;
906 arm_abi_env_t *env = self;
907 ir_graph *irg = env->irg;
908 ir_node *block = get_irg_start_block(irg);
909 // ir_node *regs[16];
911 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
913 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
914 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
915 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
916 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
917 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
918 // ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]);
919 // ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]);
920 // ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]);
921 // ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]);
923 if(env->flags.try_omit_fp)
926 ip = be_new_Copy(gp, irg, block, sp );
927 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
928 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
930 // if (r0) regs[n_regs++] = r0;
931 // if (r1) regs[n_regs++] = r1;
932 // if (r2) regs[n_regs++] = r2;
933 // if (r3) regs[n_regs++] = r3;
934 // sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
935 // set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
936 // arch_set_irn_register(env->arch_env, sp, env->isa->sp);
937 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
939 // set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
940 // arch_set_irn_register(env->arch_env, store, env->isa->sp);
942 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
943 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
944 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
946 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
947 be_node_set_reg_class(keep, 1, gp);
948 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
949 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
951 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
952 new_tarval_from_long(4, get_irn_mode(fp)));
954 //set_arm_req_out_all(fp, fp_req);
955 //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
956 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
958 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
959 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
960 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2);
961 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3);
962 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
963 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
964 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
965 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
966 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
971 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
972 arm_abi_env_t *env = self;
973 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
974 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
975 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
976 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
978 // TODO: Activate Omit fp in epilogue
979 if(env->flags.try_omit_fp) {
980 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
981 add_irn_dep(curr_sp, *mem);
983 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
984 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
985 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
986 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
988 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
989 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
990 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
991 be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
995 tarval *tv = new_tarval_from_long(12,mode_Iu);
996 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
998 //set_arm_req_out_all(sub12_node, sub12_req);
999 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
1000 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
1002 //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
1003 //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
1004 //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
1005 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
1006 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
1007 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
1008 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
1009 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
1010 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
1011 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
1013 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
1014 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
1015 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
1016 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
1019 static const be_abi_callbacks_t arm_abi_callbacks = {
1022 arm_get_between_type,
1023 arm_abi_dont_save_regs,
1030 * Get the ABI restrictions for procedure calls.
1031 * @param self The this pointer.
1032 * @param method_type The type of the method (procedure) in question.
1033 * @param abi The abi object to be modified
1035 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1039 int n = get_method_n_params(method_type);
1040 be_abi_call_flags_t flags = {
1042 0, /* store from left to right */
1043 0, /* store arguments sequential */
1044 1, /* try to omit the frame pointer */
1045 1, /* the function can use any register as frame pointer */
1046 1 /* a call can take the callee's address as an immediate */
1050 /* set stack parameter passing style */
1051 be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
1053 for (i = 0; i < n; i++) {
1054 /* reg = get reg for param i; */
1055 /* be_abi_call_param_reg(abi, i, reg); */
1058 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1060 be_abi_call_param_stack(abi, i, 4, 0, 0);
1063 /* default: return value is in R0 resp. F0 */
1064 assert(get_method_n_ress(method_type) < 2);
1065 if (get_method_n_ress(method_type) > 0) {
1066 tp = get_method_res_type(method_type, 0);
1067 mode = get_type_mode(tp);
1069 be_abi_call_res_reg(abi, 0,
1070 mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]);
1074 static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1075 return &arm_irn_ops;
1078 const arch_irn_handler_t arm_irn_handler = {
1082 const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
1083 return &arm_irn_handler;
1086 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1087 if(!is_arm_irn(irn))
1094 * Initializes the code generator interface.
1096 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1097 return &arm_code_gen_if;
1100 list_sched_selector_t arm_sched_selector;
1103 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1105 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1106 memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1107 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1108 return &arm_sched_selector;
1111 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
1116 * Returns the necessary byte alignment for storing a register of given class.
1118 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1119 /* ARM is a 32 bit CPU, no need for other alignment */
1123 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1129 static const be_machine_t *arm_get_machine(const void *self) {
1136 * Return irp irgs in the desired order.
1138 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
1143 * Returns the libFirm configuration parameter for this backend.
1145 static const backend_params *arm_get_libfirm_params(void) {
1146 static arch_dep_params_t ad = {
1148 1, /* Muls are fast enough on ARM but ... */
1149 1, /* ... one shift would be possible better */
1150 0, /* SMUL is needed, only in Arch M*/
1151 0, /* UMUL is needed, only in Arch M */
1152 32, /* SMUL & UMUL available for 32 bit */
1154 static backend_params p = {
1155 1, /* need dword lowering */
1156 0, /* don't support inline assembler yet */
1157 NULL, /* no additional opcodes */
1158 NULL, /* will be set later */
1159 NULL, /* but yet no creator function */
1160 NULL, /* context for create_intrinsic_fkt */
1161 NULL, /* no if conversion settings */
1168 /* fpu set architectures. */
1169 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1170 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1171 { "fpe", ARM_FPU_ARCH_FPE },
1172 { "fpa", ARM_FPU_ARCH_FPA },
1173 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1174 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1175 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1179 static lc_opt_enum_int_var_t arch_fpu_var = {
1180 &arm_isa_template.fpu_arch, arm_fpu_items
1183 static const lc_opt_table_entry_t arm_options[] = {
1184 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1185 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1189 const arch_isa_if_t arm_isa_if = {
1192 arm_get_n_reg_class,
1194 arm_get_reg_class_for_mode,
1196 arm_get_irn_handler,
1197 arm_get_code_generator_if,
1198 arm_get_list_sched_selector,
1199 arm_get_ilp_sched_selector,
1200 arm_get_reg_class_alignment,
1201 arm_get_libfirm_params,
1202 arm_get_allowed_execution_units,
1207 void be_init_arch_arm(void)
1209 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1210 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1212 lc_opt_add_table(arm_grp, arm_options);
1214 be_register_isa_if("arm", &arm_isa_if);
1216 arm_init_transform();
1219 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);