2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist
29 #include "lc_opts_enum.h"
37 #include "iroptimize.h"
47 #include "../bearch.h"
48 #include "../benode.h"
49 #include "../belower.h"
50 #include "../besched.h"
52 #include "../bemachine.h"
53 #include "../beilpsched.h"
54 #include "../bemodule.h"
56 #include "../bespillslots.h"
57 #include "../begnuas.h"
58 #include "../belistsched.h"
59 #include "../beflags.h"
61 #include "bearch_arm_t.h"
63 #include "arm_new_nodes.h"
64 #include "gen_arm_regalloc_if.h"
65 #include "arm_transform.h"
66 #include "arm_optimize.h"
67 #include "arm_emitter.h"
68 #include "arm_map_regs.h"
70 static arch_irn_class_t arm_classify(const ir_node *irn)
73 /* TODO: we should mark reload/spill instructions and classify them here */
77 static ir_entity *arm_get_frame_entity(const ir_node *irn)
79 const arm_attr_t *attr = get_arm_attr_const(irn);
81 if (is_arm_FrameAddr(irn)) {
82 const arm_SymConst_attr_t *attr = get_irn_generic_attr_const(irn);
85 if (attr->is_load_store) {
86 const arm_load_store_attr_t *load_store_attr
87 = get_arm_load_store_attr_const(irn);
88 if (load_store_attr->is_frame_entity) {
89 return load_store_attr->entity;
96 * This function is called by the generic backend to correct offsets for
97 * nodes accessing the stack.
99 static void arm_set_stack_bias(ir_node *irn, int bias)
101 if (is_arm_FrameAddr(irn)) {
102 arm_SymConst_attr_t *attr = get_irn_generic_attr(irn);
103 attr->fp_offset += bias;
105 arm_load_store_attr_t *attr = get_arm_load_store_attr(irn);
106 assert(attr->base.is_load_store);
107 attr->offset += bias;
111 static int arm_get_sp_bias(const ir_node *irn)
113 /* We don't have any nodes changing the stack pointer.
114 We probably want to support post-/pre increment/decrement later */
119 /* fill register allocator interface */
121 static const arch_irn_ops_t arm_irn_ops = {
123 arm_get_frame_entity,
126 NULL, /* get_inverse */
127 NULL, /* get_op_estimated_cost */
128 NULL, /* possible_memory_operand */
129 NULL, /* perform_memory_operand */
133 * Transforms the standard Firm graph into
136 static void arm_prepare_graph(void *self)
138 arm_code_gen_t *cg = self;
140 /* transform nodes into assembler instructions */
141 arm_transform_graph(cg);
143 /* do local optimizations (mainly CSE) */
144 local_optimize_graph(cg->irg);
147 dump_ir_graph(cg->irg, "transformed");
149 /* do code placement, to optimize the position of constants */
153 dump_ir_graph(cg->irg, "place");
157 * Called immediately before emit phase.
159 static void arm_finish_irg(void *self)
161 arm_code_gen_t *cg = self;
163 /* do peephole optimizations and fix stack offsets */
164 arm_peephole_optimization(cg);
167 static void arm_before_ra(void *self)
169 arm_code_gen_t *cg = self;
171 be_sched_fix_flags(cg->irg, &arm_reg_classes[CLASS_arm_flags],
175 static void transform_Reload(ir_node *node)
177 ir_node *block = get_nodes_block(node);
178 dbg_info *dbgi = get_irn_dbg_info(node);
179 ir_node *ptr = get_irn_n(node, be_pos_Reload_frame);
180 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
181 ir_mode *mode = get_irn_mode(node);
182 ir_entity *entity = be_get_frame_entity(node);
183 const arch_register_t *reg;
187 ir_node *sched_point = sched_prev(node);
189 load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true);
190 sched_add_after(sched_point, load);
193 proj = new_rd_Proj(dbgi, load, mode, pn_arm_Ldr_res);
195 reg = arch_get_irn_register(node);
196 arch_set_irn_register(proj, reg);
198 exchange(node, proj);
201 static void transform_Spill(ir_node *node)
203 ir_node *block = get_nodes_block(node);
204 dbg_info *dbgi = get_irn_dbg_info(node);
205 ir_node *ptr = get_irn_n(node, be_pos_Spill_frame);
206 ir_node *mem = new_NoMem();
207 ir_node *val = get_irn_n(node, be_pos_Spill_val);
208 ir_mode *mode = get_irn_mode(val);
209 ir_entity *entity = be_get_frame_entity(node);
210 ir_node *sched_point;
213 sched_point = sched_prev(node);
214 store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0,
218 sched_add_after(sched_point, store);
220 exchange(node, store);
223 static void arm_after_ra_walker(ir_node *block, void *data)
225 ir_node *node, *prev;
228 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
229 prev = sched_prev(node);
231 if (be_is_Reload(node)) {
232 transform_Reload(node);
233 } else if (be_is_Spill(node)) {
234 transform_Spill(node);
239 static void arm_collect_frame_entity_nodes(ir_node *node, void *data)
241 be_fec_env_t *env = data;
245 const arm_load_store_attr_t *attr;
247 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
248 mode = get_irn_mode(node);
249 align = get_mode_size_bytes(mode);
250 be_node_needs_frame_entity(env, node, mode, align);
254 switch (get_arm_irn_opcode(node)) {
262 attr = get_arm_load_store_attr_const(node);
263 entity = attr->entity;
264 mode = attr->load_store_mode;
265 align = get_mode_size_bytes(mode);
268 if (!attr->is_frame_entity)
270 be_node_needs_frame_entity(env, node, mode, align);
273 static void arm_set_frame_entity(ir_node *node, ir_entity *entity)
275 if (is_be_node(node)) {
276 be_node_set_frame_entity(node, entity);
278 arm_load_store_attr_t *attr = get_arm_load_store_attr(node);
279 attr->entity = entity;
283 static void arm_after_ra(void *self)
285 arm_code_gen_t *cg = self;
286 ir_graph *irg = cg->irg;
288 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
290 irg_walk_graph(irg, NULL, arm_collect_frame_entity_nodes, fec_env);
291 be_assign_entities(fec_env, arm_set_frame_entity);
292 be_free_frame_entity_coalescer(fec_env);
294 irg_block_walk_graph(cg->irg, NULL, arm_after_ra_walker, NULL);
298 * Emits the code, closes the output file and frees
299 * the code generator interface.
301 static void arm_emit_and_done(void *self)
303 arm_code_gen_t *cg = self;
304 ir_graph *irg = cg->irg;
306 arm_gen_routine(cg, irg);
308 /* de-allocate code generator */
313 static void *arm_cg_init(ir_graph *irg);
315 static const arch_code_generator_if_t arm_code_gen_if = {
317 NULL, /* get_pic_base */
318 NULL, /* before abi introduce */
321 arm_before_ra, /* before register allocation hook */
328 * Initializes the code generator.
330 static void *arm_cg_init(ir_graph *irg)
332 arm_isa_t *isa = (arm_isa_t*) be_get_irg_arch_env(irg);
335 cg = XMALLOCZ(arm_code_gen_t);
336 cg->impl = &arm_code_gen_if;
339 cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
341 /* enter the current code generator */
344 return (arch_code_generator_t *)cg;
349 * Maps all intrinsic calls that the backend support
350 * and map all instructions the backend did not support
353 static void arm_handle_intrinsics(void)
355 ir_type *tp, *int_tp, *uint_tp;
359 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
361 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
363 int_tp = get_type_for_mode(mode_Is);
364 uint_tp = get_type_for_mode(mode_Iu);
366 /* ARM has neither a signed div instruction ... */
368 i_instr_record *map_Div = &records[n_records++].i_instr;
370 tp = new_type_method(2, 1);
371 set_method_param_type(tp, 0, int_tp);
372 set_method_param_type(tp, 1, int_tp);
373 set_method_res_type(tp, 0, int_tp);
375 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
376 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
377 rt_iDiv.mode = mode_T;
378 rt_iDiv.res_mode = mode_Is;
379 rt_iDiv.mem_proj_nr = pn_Div_M;
380 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
381 rt_iDiv.exc_proj_nr = pn_Div_X_except;
382 rt_iDiv.exc_mem_proj_nr = pn_Div_M;
383 rt_iDiv.res_proj_nr = pn_Div_res;
385 add_entity_linkage(rt_iDiv.ent, IR_LINKAGE_CONSTANT);
386 set_entity_visibility(rt_iDiv.ent, ir_visibility_external);
388 map_Div->kind = INTRINSIC_INSTR;
389 map_Div->op = op_Div;
390 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
391 map_Div->ctx = &rt_iDiv;
393 /* ... nor an unsigned div instruction ... */
395 i_instr_record *map_Div = &records[n_records++].i_instr;
397 tp = new_type_method(2, 1);
398 set_method_param_type(tp, 0, uint_tp);
399 set_method_param_type(tp, 1, uint_tp);
400 set_method_res_type(tp, 0, uint_tp);
402 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
403 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
404 rt_uDiv.mode = mode_T;
405 rt_uDiv.res_mode = mode_Iu;
406 rt_uDiv.mem_proj_nr = pn_Div_M;
407 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
408 rt_uDiv.exc_proj_nr = pn_Div_X_except;
409 rt_uDiv.exc_mem_proj_nr = pn_Div_M;
410 rt_uDiv.res_proj_nr = pn_Div_res;
412 set_entity_visibility(rt_uDiv.ent, ir_visibility_external);
414 map_Div->kind = INTRINSIC_INSTR;
415 map_Div->op = op_Div;
416 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
417 map_Div->ctx = &rt_uDiv;
419 /* ... nor a signed mod instruction ... */
421 i_instr_record *map_Mod = &records[n_records++].i_instr;
423 tp = new_type_method(2, 1);
424 set_method_param_type(tp, 0, int_tp);
425 set_method_param_type(tp, 1, int_tp);
426 set_method_res_type(tp, 0, int_tp);
428 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
429 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
430 rt_iMod.mode = mode_T;
431 rt_iMod.res_mode = mode_Is;
432 rt_iMod.mem_proj_nr = pn_Mod_M;
433 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
434 rt_iMod.exc_proj_nr = pn_Mod_X_except;
435 rt_iMod.exc_mem_proj_nr = pn_Mod_M;
436 rt_iMod.res_proj_nr = pn_Mod_res;
438 set_entity_visibility(rt_iMod.ent, ir_visibility_external);
440 map_Mod->kind = INTRINSIC_INSTR;
441 map_Mod->op = op_Mod;
442 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
443 map_Mod->ctx = &rt_iMod;
445 /* ... nor an unsigned mod. */
447 i_instr_record *map_Mod = &records[n_records++].i_instr;
449 tp = new_type_method(2, 1);
450 set_method_param_type(tp, 0, uint_tp);
451 set_method_param_type(tp, 1, uint_tp);
452 set_method_res_type(tp, 0, uint_tp);
454 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
455 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
456 rt_uMod.mode = mode_T;
457 rt_uMod.res_mode = mode_Iu;
458 rt_uMod.mem_proj_nr = pn_Mod_M;
459 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
460 rt_uMod.exc_proj_nr = pn_Mod_X_except;
461 rt_uMod.exc_mem_proj_nr = pn_Mod_M;
462 rt_uMod.res_proj_nr = pn_Mod_res;
464 set_entity_visibility(rt_uMod.ent, ir_visibility_external);
466 map_Mod->kind = INTRINSIC_INSTR;
467 map_Mod->op = op_Mod;
468 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
469 map_Mod->ctx = &rt_uMod;
473 lower_intrinsics(records, n_records, /*part_block_used=*/0);
476 const arch_isa_if_t arm_isa_if;
477 static arm_isa_t arm_isa_template = {
479 &arm_isa_if, /* isa interface */
480 &arm_gp_regs[REG_SP], /* stack pointer */
481 &arm_gp_regs[REG_R11], /* base pointer */
482 &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */
483 -1, /* stack direction */
484 2, /* power of two stack alignment for calls, 2^2 == 4 */
485 NULL, /* main environment */
487 5, /* reload costs */
488 true, /* we do have custom abi handling */
490 ARM_FPU_ARCH_FPE, /* FPU architecture */
491 NULL, /* current code generator */
495 * Initializes the backend ISA and opens the output file.
497 static arch_env_t *arm_init(FILE *file_handle)
499 static int inited = 0;
505 isa = XMALLOC(arm_isa_t);
506 memcpy(isa, &arm_isa_template, sizeof(*isa));
511 be_emit_init(file_handle);
513 arm_create_opcodes(&arm_irn_ops);
514 arm_handle_intrinsics();
516 be_gas_emit_types = false;
518 /* needed for the debug support */
519 be_gas_emit_switch_section(GAS_SECTION_TEXT);
520 be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
521 be_emit_write_line();
530 * Closes the output file and frees the ISA structure.
532 static void arm_done(void *self)
534 arm_isa_t *isa = self;
536 be_gas_emit_decls(isa->base.main_env);
544 * Report the number of register classes.
545 * If we don't have fp instructions, report only GP
546 * here to speed up register allocation (and makes dumps
547 * smaller and more readable).
549 static unsigned arm_get_n_reg_class(void)
555 * Return the register class with requested index.
557 static const arch_register_class_t *arm_get_reg_class(unsigned i)
559 assert(i < N_CLASSES);
560 return &arm_reg_classes[i];
564 * Get the register class which shall be used to store a value of a given mode.
565 * @param self The this pointer.
566 * @param mode The mode in question.
567 * @return A register class which can hold values of the given mode.
569 static const arch_register_class_t *arm_get_reg_class_for_mode(const ir_mode *mode)
571 if (mode_is_float(mode))
572 return &arm_reg_classes[CLASS_arm_fpa];
574 return &arm_reg_classes[CLASS_arm_gp];
577 static int arm_to_appear_in_schedule(void *block_env, const ir_node *irn)
580 if (!is_arm_irn(irn))
587 * Initializes the code generator interface.
589 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self)
592 return &arm_code_gen_if;
595 list_sched_selector_t arm_sched_selector;
598 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
600 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector)
603 memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
604 /* arm_sched_selector.exectime = arm_sched_exectime; */
605 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
606 return &arm_sched_selector;
610 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self)
617 * Returns the necessary byte alignment for storing a register of given class.
619 static int arm_get_reg_class_alignment(const arch_register_class_t *cls)
622 /* ARM is a 32 bit CPU, no need for other alignment */
626 static const be_execution_unit_t ***arm_get_allowed_execution_units(const ir_node *irn)
630 panic("Unimplemented arm_get_allowed_execution_units()");
633 static const be_machine_t *arm_get_machine(const void *self)
637 panic("Unimplemented arm_get_machine()");
641 * Return irp irgs in the desired order.
643 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list)
651 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
652 * @return 1 if allowed, 0 otherwise
654 static int arm_is_mux_allowed(ir_node *sel, ir_node *mux_false,
664 static asm_constraint_flags_t arm_parse_asm_constraint(const char **c)
666 /* asm not supported */
668 return ASM_CONSTRAINT_FLAG_INVALID;
671 static int arm_is_valid_clobber(const char *clobber)
677 static void arm_lower_for_target(void)
680 int n_irgs = get_irp_n_irgs();
682 for (i = 0; i < n_irgs; ++i) {
683 ir_graph *irg = get_irp_irg(i);
684 lower_switch(irg, 256, true);
689 * Returns the libFirm configuration parameter for this backend.
691 static const backend_params *arm_get_libfirm_params(void)
693 static ir_settings_arch_dep_t ad = {
695 1, /* Muls are fast enough on ARM but ... */
696 31, /* ... one shift would be possible better */
697 NULL, /* no evaluator function */
698 0, /* SMUL is needed, only in Arch M */
699 0, /* UMUL is needed, only in Arch M */
700 32, /* SMUL & UMUL available for 32 bit */
702 static backend_params p = {
703 0, /* don't support inline assembler yet */
704 1, /* support Rotl nodes */
706 arm_lower_for_target, /* lowering function */
707 &ad, /* will be set later */
708 arm_is_mux_allowed, /* allow_ifconv function */
709 NULL, /* float arithmetic mode (TODO) */
710 0, /* no trampoline support: size 0 */
711 0, /* no trampoline support: align 0 */
712 NULL, /* no trampoline support: no trampoline builder */
713 4 /* alignment of stack parameter */
719 /* fpu set architectures. */
720 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
721 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
722 { "fpe", ARM_FPU_ARCH_FPE },
723 { "fpa", ARM_FPU_ARCH_FPA },
724 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
725 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
726 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
730 static lc_opt_enum_int_var_t arch_fpu_var = {
731 &arm_isa_template.fpu_arch, arm_fpu_items
734 static const lc_opt_table_entry_t arm_options[] = {
735 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
739 const arch_isa_if_t arm_isa_if = {
742 NULL, /* handle_intrinsics */
745 arm_get_reg_class_for_mode,
747 arm_get_code_generator_if,
748 arm_get_list_sched_selector,
749 arm_get_ilp_sched_selector,
750 arm_get_reg_class_alignment,
751 arm_get_libfirm_params,
752 arm_get_allowed_execution_units,
755 NULL, /* mark remat */
756 arm_parse_asm_constraint,
760 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);
761 void be_init_arch_arm(void)
763 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
764 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
766 lc_opt_add_table(arm_grp, arm_options);
768 be_register_isa_if("arm", &arm_isa_if);
770 arm_init_transform();