2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Oliver Richter, Tobias Gneist
30 #include <libcore/lc_opts.h>
31 #include <libcore/lc_opts_enum.h>
33 #include "pseudo_irg.h"
45 #include "../bearch_t.h" /* the general register allocator interface */
46 #include "../benode_t.h"
47 #include "../belower.h"
48 #include "../besched_t.h"
51 #include "../bemachine.h"
52 #include "../beilpsched.h"
53 #include "../bemodule.h"
54 #include "../beirg_t.h"
55 #include "../bespillslots.h"
56 #include "../begnuas.h"
58 #include "bearch_arm_t.h"
60 #include "arm_new_nodes.h" /* arm nodes interface */
61 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
62 #include "arm_transform.h"
63 #include "arm_emitter.h"
64 #include "arm_map_regs.h"
66 #define DEBUG_MODULE "firm.be.arm.isa"
68 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
69 static set *cur_reg_set = NULL;
71 /**************************************************
74 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
75 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
76 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
77 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
80 **************************************************/
83 * Return register requirements for a arm node.
84 * If the node returns a tuple (mode_T) then the proj's
85 * will be asked for this information.
88 arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node,
91 long node_pos = pos == -1 ? 0 : pos;
92 ir_mode *mode = get_irn_mode(node);
95 if (is_Block(node) || mode == mode_X) {
96 return arch_no_register_req;
99 if (mode == mode_T && pos < 0) {
100 return arch_no_register_req;
105 return arch_no_register_req;
108 return arch_no_register_req;
111 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
112 node = skip_Proj_const(node);
115 /* get requirements for our own nodes */
116 if (is_arm_irn(node)) {
117 const arch_register_req_t *req;
119 req = get_arm_in_req(node, pos);
121 req = get_arm_out_req(node, node_pos);
127 /* unknown should be transformed by now */
128 assert(!is_Unknown(node));
129 return arch_no_register_req;
132 static void arm_set_irn_reg(const void *self, ir_node *irn,
133 const arch_register_t *reg)
138 if (get_irn_mode(irn) == mode_X) {
143 pos = get_Proj_proj(irn);
144 irn = skip_Proj(irn);
147 if (is_arm_irn(irn)) {
148 const arch_register_t **slots;
150 slots = get_arm_slots(irn);
154 /* here we set the registers for the Phi nodes */
155 arm_set_firm_reg(irn, reg, cur_reg_set);
159 static const arch_register_t *arm_get_irn_reg(const void *self,
163 const arch_register_t *reg = NULL;
168 if (get_irn_mode(irn) == mode_X) {
172 pos = get_Proj_proj(irn);
173 irn = skip_Proj_const(irn);
176 if (is_arm_irn(irn)) {
177 const arch_register_t **slots;
178 slots = get_arm_slots(irn);
182 reg = arm_get_firm_reg(irn, cur_reg_set);
188 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn)
191 irn = skip_Proj_const(irn);
194 return arch_irn_class_branch;
196 else if (is_arm_irn(irn)) {
197 return arch_irn_class_normal;
203 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn)
206 irn = skip_Proj_const(irn);
208 if (is_arm_irn(irn)) {
209 return get_arm_flags(irn);
211 else if (is_Unknown(irn)) {
212 return arch_irn_flags_ignore;
218 static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn)
222 /* TODO: return the entity assigned to the frame */
226 static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent)
231 /* TODO: set the entity assigned to the frame */
235 * This function is called by the generic backend to correct offsets for
236 * nodes accessing the stack.
238 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias)
243 /* TODO: correct offset if irn accesses the stack */
246 static int arm_get_sp_bias(const void *self, const ir_node *irn)
253 /* fill register allocator interface */
255 static const arch_irn_ops_if_t arm_irn_ops_if = {
261 arm_get_frame_entity,
262 arm_set_frame_entity,
265 NULL, /* get_inverse */
266 NULL, /* get_op_estimated_cost */
267 NULL, /* possible_memory_operand */
268 NULL, /* perform_memory_operand */
271 arm_irn_ops_t arm_irn_ops = {
278 /**************************************************
281 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
282 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
283 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
284 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
287 **************************************************/
290 * Transforms the standard Firm graph into
293 static void arm_prepare_graph(void *self) {
294 arm_code_gen_t *cg = self;
296 /* transform nodes into assembler instructions */
297 arm_transform_graph(cg);
299 /* do local optimizations (mainly CSE) */
300 local_optimize_graph(cg->irg);
303 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
305 /* do code placement, to optimize the position of constants */
309 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
313 * Called immediately before emit phase.
315 static void arm_finish_irg(void *self)
318 /* TODO: - fix offsets for nodes accessing stack
325 * These are some hooks which must be filled but are probably not needed.
327 static void arm_before_sched(void *self)
330 /* Some stuff you need to do after scheduling but before register allocation */
333 static void arm_before_ra(void *self)
336 /* Some stuff you need to do immediately after register allocation */
340 * We transform Spill and Reload here. This needs to be done before
341 * stack biasing otherwise we would miss the corrected offset for these nodes.
343 static void arm_after_ra(void *self)
345 arm_code_gen_t *cg = self;
346 be_coalesce_spillslots(cg->birg);
350 * Emits the code, closes the output file and frees
351 * the code generator interface.
353 static void arm_emit_and_done(void *self) {
354 arm_code_gen_t *cg = self;
355 ir_graph *irg = cg->irg;
357 arm_gen_routine(cg, irg);
361 /* de-allocate code generator */
362 del_set(cg->reg_set);
367 * Move a double floating point value into an integer register.
368 * Place the move operation into block bl.
370 * Handle some special cases here:
371 * 1.) A constant: simply split into two
372 * 2.) A load: simply split into two
374 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
375 ir_node **resH, ir_node **resL) {
377 tarval *tv = get_Const_tarval(arg);
380 /* get the upper 32 bits */
381 v = get_tarval_sub_bits(tv, 7);
382 v = (v << 8) | get_tarval_sub_bits(tv, 6);
383 v = (v << 8) | get_tarval_sub_bits(tv, 5);
384 v = (v << 8) | get_tarval_sub_bits(tv, 4);
385 *resH = new_Const_long(mode_Is, v);
387 /* get the lower 32 bits */
388 v = get_tarval_sub_bits(tv, 3);
389 v = (v << 8) | get_tarval_sub_bits(tv, 2);
390 v = (v << 8) | get_tarval_sub_bits(tv, 1);
391 v = (v << 8) | get_tarval_sub_bits(tv, 0);
392 *resL = new_Const_long(mode_Is, v);
394 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
395 /* FIXME: handling of low/high depends on LE/BE here */
399 ir_graph *irg = current_ir_graph;
402 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
404 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
405 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
406 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
412 * Move a single floating point value into an integer register.
413 * Place the move operation into block bl.
415 * Handle some special cases here:
416 * 1.) A constant: simply move
417 * 2.) A load: simply load
419 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg)
424 tarval *tv = get_Const_tarval(arg);
427 /* get the lower 32 bits */
428 v = get_tarval_sub_bits(tv, 3);
429 v = (v << 8) | get_tarval_sub_bits(tv, 2);
430 v = (v << 8) | get_tarval_sub_bits(tv, 1);
431 v = (v << 8) | get_tarval_sub_bits(tv, 0);
432 return new_Const_long(mode_Is, v);
434 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
437 load = skip_Proj(arg);
444 * Convert the arguments of a call to support the
445 * ARM calling convention of general purpose AND floating
448 static void handle_calls(ir_node *call, void *env)
450 arm_code_gen_t *cg = env;
451 int i, j, n, size, idx, flag, n_param, n_res, first_variadic;
452 ir_type *mtp, *new_mtd, *new_tp[5];
453 ir_node *new_in[5], **in;
459 /* check, if we need conversions */
460 n = get_Call_n_params(call);
461 mtp = get_Call_type(call);
462 assert(get_method_n_params(mtp) == n);
464 /* it's always enough to handle the first 4 parameters */
467 flag = size = idx = 0;
468 bl = get_nodes_block(call);
469 for (i = 0; i < n; ++i) {
470 ir_type *param_tp = get_method_param_type(mtp, i);
472 if (is_compound_type(param_tp)) {
473 /* an aggregate parameter: bad case */
477 /* a primitive parameter */
478 ir_mode *mode = get_type_mode(param_tp);
480 if (mode_is_float(mode)) {
481 if (get_mode_size_bits(mode) > 32) {
482 ir_node *mem = get_Call_mem(call);
484 /* Beware: ARM wants the high part first */
486 new_tp[idx] = cg->int_tp;
487 new_tp[idx+1] = cg->int_tp;
488 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
490 set_Call_mem(call, mem);
494 new_tp[idx] = cg->int_tp;
495 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
502 new_tp[idx] = param_tp;
503 new_in[idx] = get_Call_param(call, i);
512 /* if flag is NOT set, no need to translate the method type */
516 /* construct a new method type */
518 n_param = get_method_n_params(mtp) - n + idx;
519 n_res = get_method_n_ress(mtp);
520 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
522 for (i = 0; i < idx; ++i)
523 set_method_param_type(new_mtd, i, new_tp[i]);
524 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
525 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
526 for (i = 0; i < n_res; ++i)
527 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
529 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
530 first_variadic = get_method_first_variadic_param_index(mtp);
531 if (first_variadic >= 0)
532 set_method_first_variadic_param_index(new_mtd, first_variadic);
534 if (is_lowered_type(mtp)) {
535 mtp = get_associated_type(mtp);
537 set_lowered_type(mtp, new_mtd);
539 set_Call_type(call, new_mtd);
541 /* calculate new in array of the Call */
542 NEW_ARR_A(ir_node *, in, n_param + 2);
543 for (i = 0; i < idx; ++i)
544 in[2 + i] = new_in[i];
545 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
546 in[2 + j++] = get_Call_param(call, i);
548 in[0] = get_Call_mem(call);
549 in[1] = get_Call_ptr(call);
551 /* finally, change the call inputs */
552 set_irn_in(call, n_param + 2, in);
556 * Handle graph transformations before the abi converter does its work.
558 static void arm_before_abi(void *self) {
559 arm_code_gen_t *cg = self;
561 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
565 static void *arm_cg_init(be_irg_t *birg);
567 static const arch_code_generator_if_t arm_code_gen_if = {
569 arm_before_abi, /* before abi introduce */
572 arm_before_sched, /* before scheduling hook */
573 arm_before_ra, /* before register allocation hook */
580 * Initializes the code generator.
582 static void *arm_cg_init(be_irg_t *birg) {
583 static ir_type *int_tp = NULL;
584 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
588 /* create an integer type with machine size */
589 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
592 cg = xmalloc(sizeof(*cg));
593 cg->impl = &arm_code_gen_if;
595 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
596 cg->arch_env = birg->main_env->arch_env;
600 cg->have_fp_insn = 0;
601 cg->unknown_gp = NULL;
602 cg->unknown_fpa = NULL;
603 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
605 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
607 cur_reg_set = cg->reg_set;
611 /* enter the current code generator */
614 return (arch_code_generator_t *)cg;
619 * Maps all intrinsic calls that the backend support
620 * and map all instructions the backend did not support
623 static void arm_handle_intrinsics(void) {
624 ir_type *tp, *int_tp, *uint_tp;
628 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
630 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
632 int_tp = new_type_primitive(ID("int"), mode_Is);
633 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
635 /* ARM has neither a signed div instruction ... */
637 i_instr_record *map_Div = &records[n_records++].i_instr;
639 tp = new_type_method(ID("rt_iDiv"), 2, 1);
640 set_method_param_type(tp, 0, int_tp);
641 set_method_param_type(tp, 1, int_tp);
642 set_method_res_type(tp, 0, int_tp);
644 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
645 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
646 rt_iDiv.mode = mode_T;
647 rt_iDiv.res_mode = mode_Is;
648 rt_iDiv.mem_proj_nr = pn_Div_M;
649 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
650 rt_iDiv.exc_proj_nr = pn_Div_X_except;
651 rt_iDiv.exc_mem_proj_nr = pn_Div_M;
652 rt_iDiv.res_proj_nr = pn_Div_res;
654 set_entity_visibility(rt_iDiv.ent, visibility_external_allocated);
656 map_Div->kind = INTRINSIC_INSTR;
657 map_Div->op = op_Div;
658 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
659 map_Div->ctx = &rt_iDiv;
661 /* ... nor an unsigned div instruction ... */
663 i_instr_record *map_Div = &records[n_records++].i_instr;
665 tp = new_type_method(ID("rt_uDiv"), 2, 1);
666 set_method_param_type(tp, 0, uint_tp);
667 set_method_param_type(tp, 1, uint_tp);
668 set_method_res_type(tp, 0, uint_tp);
670 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
671 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
672 rt_uDiv.mode = mode_T;
673 rt_uDiv.res_mode = mode_Iu;
674 rt_uDiv.mem_proj_nr = pn_Div_M;
675 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
676 rt_uDiv.exc_proj_nr = pn_Div_X_except;
677 rt_uDiv.exc_mem_proj_nr = pn_Div_M;
678 rt_uDiv.res_proj_nr = pn_Div_res;
680 set_entity_visibility(rt_uDiv.ent, visibility_external_allocated);
682 map_Div->kind = INTRINSIC_INSTR;
683 map_Div->op = op_Div;
684 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
685 map_Div->ctx = &rt_uDiv;
687 /* ... nor a signed mod instruction ... */
689 i_instr_record *map_Mod = &records[n_records++].i_instr;
691 tp = new_type_method(ID("rt_iMod"), 2, 1);
692 set_method_param_type(tp, 0, int_tp);
693 set_method_param_type(tp, 1, int_tp);
694 set_method_res_type(tp, 0, int_tp);
696 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
697 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
698 rt_iMod.mode = mode_T;
699 rt_iMod.res_mode = mode_Is;
700 rt_iMod.mem_proj_nr = pn_Mod_M;
701 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
702 rt_iMod.exc_proj_nr = pn_Mod_X_except;
703 rt_iMod.exc_mem_proj_nr = pn_Mod_M;
704 rt_iMod.res_proj_nr = pn_Mod_res;
706 set_entity_visibility(rt_iMod.ent, visibility_external_allocated);
708 map_Mod->kind = INTRINSIC_INSTR;
709 map_Mod->op = op_Mod;
710 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
711 map_Mod->ctx = &rt_iMod;
713 /* ... nor an unsigned mod. */
715 i_instr_record *map_Mod = &records[n_records++].i_instr;
717 tp = new_type_method(ID("rt_uMod"), 2, 1);
718 set_method_param_type(tp, 0, uint_tp);
719 set_method_param_type(tp, 1, uint_tp);
720 set_method_res_type(tp, 0, uint_tp);
722 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
723 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
724 rt_uMod.mode = mode_T;
725 rt_uMod.res_mode = mode_Iu;
726 rt_uMod.mem_proj_nr = pn_Mod_M;
727 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
728 rt_uMod.exc_proj_nr = pn_Mod_X_except;
729 rt_uMod.exc_mem_proj_nr = pn_Mod_M;
730 rt_uMod.res_proj_nr = pn_Mod_res;
732 set_entity_visibility(rt_uMod.ent, visibility_external_allocated);
734 map_Mod->kind = INTRINSIC_INSTR;
735 map_Mod->op = op_Mod;
736 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
737 map_Mod->ctx = &rt_uMod;
741 lower_intrinsics(records, n_records);
744 /*****************************************************************
745 * ____ _ _ _____ _____
746 * | _ \ | | | | |_ _|/ ____| /\
747 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
748 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
749 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
750 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
752 *****************************************************************/
754 static arm_isa_t arm_isa_template = {
756 &arm_isa_if, /* isa interface */
757 &arm_gp_regs[REG_SP], /* stack pointer */
758 &arm_gp_regs[REG_R11], /* base pointer */
759 -1, /* stack direction */
760 NULL, /* main environment */
762 5, /* reload costs */
764 0, /* use generic register names instead of SP, LR, PC */
765 ARM_FPU_ARCH_FPE, /* FPU architecture */
766 NULL, /* current code generator */
767 NULL_EMITTER, /* emitter environment */
771 * Initializes the backend ISA and opens the output file.
773 static void *arm_init(FILE *file_handle) {
774 static int inited = 0;
780 isa = xmalloc(sizeof(*isa));
781 memcpy(isa, &arm_isa_template, sizeof(*isa));
786 be_emit_init_env(&isa->emit, file_handle);
788 arm_create_opcodes();
789 arm_handle_intrinsics();
791 /* we mark referenced global entities, so we can only emit those which
792 * are actually referenced. (Note: you mustn't use the type visited flag
793 * elsewhere in the backend)
795 inc_master_type_visited();
804 * Closes the output file and frees the ISA structure.
806 static void arm_done(void *self) {
807 arm_isa_t *isa = self;
809 be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
811 be_emit_destroy_env(&isa->emit);
817 * Report the number of register classes.
818 * If we don't have fp instructions, report only GP
819 * here to speed up register allocation (and makes dumps
820 * smaller and more readable).
822 static int arm_get_n_reg_class(const void *self) {
823 const arm_isa_t *isa = self;
825 /* ARGH! is called BEFORE transform */
827 return isa->cg->have_fp_insn ? 2 : 1;
831 * Return the register class with requested index.
833 static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
835 return &arm_reg_classes[i];
839 * Get the register class which shall be used to store a value of a given mode.
840 * @param self The this pointer.
841 * @param mode The mode in question.
842 * @return A register class which can hold values of the given mode.
844 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
846 if (mode_is_float(mode))
847 return &arm_reg_classes[CLASS_arm_fpa];
849 return &arm_reg_classes[CLASS_arm_gp];
853 * Produces the type which sits between the stack args and the locals on the stack.
854 * it will contain the return address and space to store the old base pointer.
855 * @return The Firm type modeling the ABI between type.
857 static ir_type *arm_get_between_type(void *self) {
858 static ir_type *between_type = NULL;
859 static ir_entity *old_bp_ent = NULL;
862 if (between_type == NULL) {
863 ir_entity *ret_addr_ent;
864 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
865 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
867 between_type = new_type_class(new_id_from_str("arm_between_type"));
868 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
869 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
871 set_entity_offset(old_bp_ent, 0);
872 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
873 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
881 be_abi_call_flags_bits_t flags;
882 const arch_env_t *arch_env;
883 const arch_isa_t *isa;
887 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
889 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
890 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
891 env->flags = fl.bits;
893 env->arch_env = arch_env;
894 env->isa = arch_env->isa;
898 static void arm_abi_dont_save_regs(void *self, pset *s)
900 arm_abi_env_t *env = self;
901 if (env->flags.try_omit_fp)
902 pset_insert_ptr(s, env->isa->bp);
908 * Build the ARM prolog
910 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
911 ir_node *keep, *store;
912 arm_abi_env_t *env = self;
913 ir_graph *irg = env->irg;
914 ir_node *block = get_irg_start_block(irg);
915 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
917 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
918 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
919 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
920 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
921 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
923 if (env->flags.try_omit_fp)
926 ip = be_new_Copy(gp, irg, block, sp);
927 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
928 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
930 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
932 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
933 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
934 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
936 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
937 be_node_set_reg_class(keep, 1, gp);
938 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
939 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
941 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
942 new_tarval_from_long(4, get_irn_mode(fp)));
943 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
945 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
946 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
947 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
948 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
949 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
955 * Builds the ARM epilogue
957 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
958 arm_abi_env_t *env = self;
959 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
960 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
961 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
962 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
964 // TODO: Activate Omit fp in epilogue
965 if (env->flags.try_omit_fp) {
966 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
967 add_irn_dep(curr_sp, *mem);
969 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
970 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
971 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
972 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
974 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
975 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
976 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
977 be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
981 tarval *tv = new_tarval_from_long(12,mode_Iu);
982 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
984 //set_arm_req_out_all(sub12_node, sub12_req);
985 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
986 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
988 //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
989 //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
990 //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
991 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
992 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
993 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
994 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
995 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
996 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
997 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
999 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
1000 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
1001 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
1002 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
1005 static const be_abi_callbacks_t arm_abi_callbacks = {
1008 arm_get_between_type,
1009 arm_abi_dont_save_regs,
1016 * Get the ABI restrictions for procedure calls.
1017 * @param self The this pointer.
1018 * @param method_type The type of the method (procedure) in question.
1019 * @param abi The abi object to be modified
1021 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1025 int n = get_method_n_params(method_type);
1026 be_abi_call_flags_t flags = {
1028 0, /* store from left to right */
1029 0, /* store arguments sequential */
1030 1, /* try to omit the frame pointer */
1031 1, /* the function can use any register as frame pointer */
1032 1, /* a call can take the callee's address as an immediate */
1033 0, /* IRG is a leaf function */
1034 0 /* Set to one, if there is already enough room on the stack for call args. */
1039 /* set stack parameter passing style */
1040 be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
1042 for (i = 0; i < n; i++) {
1043 /* reg = get reg for param i; */
1044 /* be_abi_call_param_reg(abi, i, reg); */
1047 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1049 be_abi_call_param_stack(abi, i, 4, 0, 0);
1052 /* set return registers */
1053 n = get_method_n_ress(method_type);
1055 assert(n <= 2 && "more than two results not supported");
1057 /* In case of 64bit returns, we will have two 32bit values */
1059 tp = get_method_res_type(method_type, 0);
1060 mode = get_type_mode(tp);
1062 assert(!mode_is_float(mode) && "two FP results not supported");
1064 tp = get_method_res_type(method_type, 1);
1065 mode = get_type_mode(tp);
1067 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1069 be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0]);
1070 be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1]);
1071 } else if (n == 1) {
1072 const arch_register_t *reg;
1074 tp = get_method_res_type(method_type, 0);
1075 assert(is_atomic_type(tp));
1076 mode = get_type_mode(tp);
1078 reg = mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0];
1079 be_abi_call_res_reg(abi, 0, reg);
1083 static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1086 return &arm_irn_ops;
1089 const arch_irn_handler_t arm_irn_handler = {
1093 const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
1095 return &arm_irn_handler;
1098 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1100 if(!is_arm_irn(irn))
1107 * Initializes the code generator interface.
1109 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1111 return &arm_code_gen_if;
1114 list_sched_selector_t arm_sched_selector;
1117 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1119 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1122 memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1123 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1124 return &arm_sched_selector;
1127 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
1133 * Returns the necessary byte alignment for storing a register of given class.
1135 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1138 /* ARM is a 32 bit CPU, no need for other alignment */
1142 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1150 static const be_machine_t *arm_get_machine(const void *self) {
1158 * Return irp irgs in the desired order.
1160 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
1167 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1168 * @return 1 if allowed, 0 otherwise
1170 static int arm_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) {
1171 ir_node *cmp, *cmp_a, *phi;
1175 /* currently Psi support is not implemented */
1178 /* we don't want long long Psi */
1179 #define IS_BAD_PSI_MODE(mode) (!mode_is_float(mode) && get_mode_size_bits(mode) > 32)
1181 if (get_irn_mode(sel) != mode_b)
1184 cmp = get_Proj_pred(sel);
1185 cmp_a = get_Cmp_left(cmp);
1186 mode = get_irn_mode(cmp_a);
1188 if (IS_BAD_PSI_MODE(mode))
1191 /* check the Phi nodes */
1192 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1193 ir_node *pred_i = get_irn_n(phi, i);
1194 ir_node *pred_j = get_irn_n(phi, j);
1195 ir_mode *mode_i = get_irn_mode(pred_i);
1196 ir_mode *mode_j = get_irn_mode(pred_j);
1198 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1202 #undef IS_BAD_PSI_MODE
1208 * Returns the libFirm configuration parameter for this backend.
1210 static const backend_params *arm_get_libfirm_params(void) {
1211 static const opt_if_conv_info_t ifconv = {
1212 4, /* maxdepth, doesn't matter for Psi-conversion */
1213 arm_is_psi_allowed /* allows or disallows Psi creation for given selector */
1215 static arch_dep_params_t ad = {
1217 1, /* Muls are fast enough on ARM but ... */
1218 31, /* ... one shift would be possible better */
1219 0, /* SMUL is needed, only in Arch M */
1220 0, /* UMUL is needed, only in Arch M */
1221 32, /* SMUL & UMUL available for 32 bit */
1223 static backend_params p = {
1224 1, /* need dword lowering */
1225 0, /* don't support inline assembler yet */
1226 NULL, /* no additional opcodes */
1227 NULL, /* will be set later */
1228 NULL, /* but yet no creator function */
1229 NULL, /* context for create_intrinsic_fkt */
1230 NULL, /* will be set below */
1234 p.if_conv_info = &ifconv;
1238 /* fpu set architectures. */
1239 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1240 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1241 { "fpe", ARM_FPU_ARCH_FPE },
1242 { "fpa", ARM_FPU_ARCH_FPA },
1243 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1244 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1245 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1249 static lc_opt_enum_int_var_t arch_fpu_var = {
1250 &arm_isa_template.fpu_arch, arm_fpu_items
1253 static const lc_opt_table_entry_t arm_options[] = {
1254 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1255 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1259 const arch_isa_if_t arm_isa_if = {
1262 arm_get_n_reg_class,
1264 arm_get_reg_class_for_mode,
1266 arm_get_irn_handler,
1267 arm_get_code_generator_if,
1268 arm_get_list_sched_selector,
1269 arm_get_ilp_sched_selector,
1270 arm_get_reg_class_alignment,
1271 arm_get_libfirm_params,
1272 arm_get_allowed_execution_units,
1277 void be_init_arch_arm(void)
1279 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1280 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1282 lc_opt_add_table(arm_grp, arm_options);
1284 be_register_isa_if("arm", &arm_isa_if);
1286 arm_init_transform();
1289 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);