2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Oliver Richter, Tobias Gneist
29 #include "lc_opts_enum.h"
31 #include "pseudo_irg.h"
38 #include "iroptimize.h"
47 #include "../bearch_t.h" /* the general register allocator interface */
48 #include "../benode_t.h"
49 #include "../belower.h"
50 #include "../besched_t.h"
53 #include "../bemachine.h"
54 #include "../beilpsched.h"
55 #include "../bemodule.h"
56 #include "../beirg_t.h"
57 #include "../bespillslots.h"
58 #include "../begnuas.h"
60 #include "bearch_arm_t.h"
62 #include "arm_new_nodes.h" /* arm nodes interface */
63 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
64 #include "arm_transform.h"
65 #include "arm_optimize.h"
66 #include "arm_emitter.h"
67 #include "arm_map_regs.h"
69 #define DEBUG_MODULE "firm.be.arm.isa"
71 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
72 static set *cur_reg_set = NULL;
74 /**************************************************
77 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
78 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
79 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
80 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
83 **************************************************/
86 * Return register requirements for a arm node.
87 * If the node returns a tuple (mode_T) then the proj's
88 * will be asked for this information.
90 static const arch_register_req_t *arm_get_irn_reg_req(const ir_node *node,
93 long node_pos = pos == -1 ? 0 : pos;
94 ir_mode *mode = get_irn_mode(node);
96 if (is_Block(node) || mode == mode_X) {
97 return arch_no_register_req;
100 if (mode == mode_T && pos < 0) {
101 return arch_no_register_req;
106 return arch_no_register_req;
109 return arch_no_register_req;
112 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
113 node = skip_Proj_const(node);
116 /* get requirements for our own nodes */
117 if (is_arm_irn(node)) {
118 const arch_register_req_t *req;
120 req = get_arm_in_req(node, pos);
122 req = get_arm_out_req(node, node_pos);
128 /* unknown should be transformed by now */
129 assert(!is_Unknown(node));
130 return arch_no_register_req;
133 static void arm_set_irn_reg(ir_node *irn, const arch_register_t *reg)
137 if (get_irn_mode(irn) == mode_X) {
142 pos = get_Proj_proj(irn);
143 irn = skip_Proj(irn);
146 if (is_arm_irn(irn)) {
147 const arch_register_t **slots;
149 slots = get_arm_slots(irn);
153 /* here we set the registers for the Phi nodes */
154 arm_set_firm_reg(irn, reg, cur_reg_set);
158 static const arch_register_t *arm_get_irn_reg(const ir_node *irn)
161 const arch_register_t *reg = NULL;
165 if (get_irn_mode(irn) == mode_X) {
169 pos = get_Proj_proj(irn);
170 irn = skip_Proj_const(irn);
173 if (is_arm_irn(irn)) {
174 const arch_register_t **slots;
175 slots = get_arm_slots(irn);
179 reg = arm_get_firm_reg(irn, cur_reg_set);
185 static arch_irn_class_t arm_classify(const ir_node *irn)
187 irn = skip_Proj_const(irn);
190 return arch_irn_class_branch;
196 static arch_irn_flags_t arm_get_flags(const ir_node *irn)
198 arch_irn_flags_t flags = arch_irn_flags_none;
200 if(is_Unknown(irn)) {
201 return arch_irn_flags_ignore;
204 if (is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
205 ir_node *pred = get_Proj_pred(irn);
206 if (is_arm_irn(pred)) {
207 flags = get_arm_out_flags(pred, get_Proj_proj(irn));
212 if (is_arm_irn(irn)) {
213 flags |= get_arm_flags(irn);
219 static ir_entity *arm_get_frame_entity(const ir_node *irn) {
220 /* we do NOT transform be_Spill or be_Reload nodes, so we never
221 have frame access using ARM nodes. */
226 static void arm_set_frame_entity(ir_node *irn, ir_entity *ent) {
229 panic("arm_set_frame_entity() called. This should not happen.");
233 * This function is called by the generic backend to correct offsets for
234 * nodes accessing the stack.
236 static void arm_set_stack_bias(ir_node *irn, int bias)
240 /* TODO: correct offset if irn accesses the stack */
243 static int arm_get_sp_bias(const ir_node *irn)
249 /* fill register allocator interface */
251 static const arch_irn_ops_t arm_irn_ops = {
257 arm_get_frame_entity,
258 arm_set_frame_entity,
261 NULL, /* get_inverse */
262 NULL, /* get_op_estimated_cost */
263 NULL, /* possible_memory_operand */
264 NULL, /* perform_memory_operand */
267 /**************************************************
270 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
271 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
272 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
273 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
276 **************************************************/
279 * Transforms the standard Firm graph into
282 static void arm_prepare_graph(void *self) {
283 arm_code_gen_t *cg = self;
285 /* transform nodes into assembler instructions */
286 arm_transform_graph(cg);
288 /* do local optimizations (mainly CSE) */
289 local_optimize_graph(cg->irg);
292 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
294 /* do code placement, to optimize the position of constants */
298 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
302 * Called immediately before emit phase.
304 static void arm_finish_irg(void *self)
306 arm_code_gen_t *cg = self;
308 /* do peephole optimizations and fix stack offsets */
309 arm_peephole_optimization(cg);
314 * These are some hooks which must be filled but are probably not needed.
316 static void arm_before_sched(void *self)
319 /* Some stuff you need to do after scheduling but before register allocation */
322 static void arm_before_ra(void *self)
325 /* Some stuff you need to do immediately after register allocation */
329 * We transform Spill and Reload here. This needs to be done before
330 * stack biasing otherwise we would miss the corrected offset for these nodes.
332 static void arm_after_ra(void *self)
334 arm_code_gen_t *cg = self;
335 be_coalesce_spillslots(cg->birg);
339 * Emits the code, closes the output file and frees
340 * the code generator interface.
342 static void arm_emit_and_done(void *self) {
343 arm_code_gen_t *cg = self;
344 ir_graph *irg = cg->irg;
346 arm_gen_routine(cg, irg);
350 /* de-allocate code generator */
351 del_set(cg->reg_set);
356 * Move a double floating point value into an integer register.
357 * Place the move operation into block bl.
359 * Handle some special cases here:
360 * 1.) A constant: simply split into two
361 * 2.) A load: simply split into two
363 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
364 ir_node **resH, ir_node **resL) {
366 tarval *tv = get_Const_tarval(arg);
369 /* get the upper 32 bits */
370 v = get_tarval_sub_bits(tv, 7);
371 v = (v << 8) | get_tarval_sub_bits(tv, 6);
372 v = (v << 8) | get_tarval_sub_bits(tv, 5);
373 v = (v << 8) | get_tarval_sub_bits(tv, 4);
374 *resH = new_Const_long(mode_Is, v);
376 /* get the lower 32 bits */
377 v = get_tarval_sub_bits(tv, 3);
378 v = (v << 8) | get_tarval_sub_bits(tv, 2);
379 v = (v << 8) | get_tarval_sub_bits(tv, 1);
380 v = (v << 8) | get_tarval_sub_bits(tv, 0);
381 *resL = new_Const_long(mode_Is, v);
382 } else if (is_Load(skip_Proj(arg))) {
383 /* FIXME: handling of low/high depends on LE/BE here */
384 panic("Unimplemented convert_dbl_to_int() case");
387 ir_graph *irg = current_ir_graph;
390 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
392 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
393 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
394 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
400 * Move a single floating point value into an integer register.
401 * Place the move operation into block bl.
403 * Handle some special cases here:
404 * 1.) A constant: simply move
405 * 2.) A load: simply load
407 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg)
412 tarval *tv = get_Const_tarval(arg);
415 /* get the lower 32 bits */
416 v = get_tarval_sub_bits(tv, 3);
417 v = (v << 8) | get_tarval_sub_bits(tv, 2);
418 v = (v << 8) | get_tarval_sub_bits(tv, 1);
419 v = (v << 8) | get_tarval_sub_bits(tv, 0);
420 return new_Const_long(mode_Is, v);
421 } else if (is_Load(skip_Proj(arg))) {
424 load = skip_Proj(arg);
426 panic("Unimplemented convert_sng_to_int() case");
430 * Convert the arguments of a call to support the
431 * ARM calling convention of general purpose AND floating
434 static void handle_calls(ir_node *call, void *env)
436 arm_code_gen_t *cg = env;
437 int i, j, n, size, idx, flag, n_param, n_res, first_variadic;
438 ir_type *mtp, *new_mtd, *new_tp[5];
439 ir_node *new_in[5], **in;
445 /* check, if we need conversions */
446 n = get_Call_n_params(call);
447 mtp = get_Call_type(call);
448 assert(get_method_n_params(mtp) == n);
450 /* it's always enough to handle the first 4 parameters */
453 flag = size = idx = 0;
454 bl = get_nodes_block(call);
455 for (i = 0; i < n; ++i) {
456 ir_type *param_tp = get_method_param_type(mtp, i);
458 if (is_compound_type(param_tp)) {
459 /* an aggregate parameter: bad case */
463 /* a primitive parameter */
464 ir_mode *mode = get_type_mode(param_tp);
466 if (mode_is_float(mode)) {
467 if (get_mode_size_bits(mode) > 32) {
468 ir_node *mem = get_Call_mem(call);
470 /* Beware: ARM wants the high part first */
472 new_tp[idx] = cg->int_tp;
473 new_tp[idx+1] = cg->int_tp;
474 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
476 set_Call_mem(call, mem);
480 new_tp[idx] = cg->int_tp;
481 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
488 new_tp[idx] = param_tp;
489 new_in[idx] = get_Call_param(call, i);
498 /* if flag is NOT set, no need to translate the method type */
502 /* construct a new method type */
504 n_param = get_method_n_params(mtp) - n + idx;
505 n_res = get_method_n_ress(mtp);
506 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
508 for (i = 0; i < idx; ++i)
509 set_method_param_type(new_mtd, i, new_tp[i]);
510 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
511 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
512 for (i = 0; i < n_res; ++i)
513 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
515 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
516 first_variadic = get_method_first_variadic_param_index(mtp);
517 if (first_variadic >= 0)
518 set_method_first_variadic_param_index(new_mtd, first_variadic);
520 if (is_lowered_type(mtp)) {
521 mtp = get_associated_type(mtp);
523 set_lowered_type(mtp, new_mtd);
525 set_Call_type(call, new_mtd);
527 /* calculate new in array of the Call */
528 NEW_ARR_A(ir_node *, in, n_param + 2);
529 for (i = 0; i < idx; ++i)
530 in[2 + i] = new_in[i];
531 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
532 in[2 + j++] = get_Call_param(call, i);
534 in[0] = get_Call_mem(call);
535 in[1] = get_Call_ptr(call);
537 /* finally, change the call inputs */
538 set_irn_in(call, n_param + 2, in);
542 * Handle graph transformations before the abi converter does its work.
544 static void arm_before_abi(void *self) {
545 arm_code_gen_t *cg = self;
547 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
551 static void *arm_cg_init(be_irg_t *birg);
553 static const arch_code_generator_if_t arm_code_gen_if = {
555 NULL, /* get_pic_base */
556 arm_before_abi, /* before abi introduce */
559 arm_before_sched, /* before scheduling hook */
560 arm_before_ra, /* before register allocation hook */
567 * Initializes the code generator.
569 static void *arm_cg_init(be_irg_t *birg) {
570 static ir_type *int_tp = NULL;
571 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env;
575 /* create an integer type with machine size */
576 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
579 cg = XMALLOC(arm_code_gen_t);
580 cg->impl = &arm_code_gen_if;
582 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
586 cg->have_fp_insn = 0;
587 cg->unknown_gp = NULL;
588 cg->unknown_fpa = NULL;
589 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
591 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
593 cur_reg_set = cg->reg_set;
595 /* enter the current code generator */
598 return (arch_code_generator_t *)cg;
603 * Maps all intrinsic calls that the backend support
604 * and map all instructions the backend did not support
607 static void arm_handle_intrinsics(void) {
608 ir_type *tp, *int_tp, *uint_tp;
612 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
614 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
616 int_tp = new_type_primitive(ID("int"), mode_Is);
617 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
619 /* ARM has neither a signed div instruction ... */
621 i_instr_record *map_Div = &records[n_records++].i_instr;
623 tp = new_type_method(ID("rt_iDiv"), 2, 1);
624 set_method_param_type(tp, 0, int_tp);
625 set_method_param_type(tp, 1, int_tp);
626 set_method_res_type(tp, 0, int_tp);
628 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
629 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
630 rt_iDiv.mode = mode_T;
631 rt_iDiv.res_mode = mode_Is;
632 rt_iDiv.mem_proj_nr = pn_Div_M;
633 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
634 rt_iDiv.exc_proj_nr = pn_Div_X_except;
635 rt_iDiv.exc_mem_proj_nr = pn_Div_M;
636 rt_iDiv.res_proj_nr = pn_Div_res;
638 set_entity_visibility(rt_iDiv.ent, visibility_external_allocated);
640 map_Div->kind = INTRINSIC_INSTR;
641 map_Div->op = op_Div;
642 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
643 map_Div->ctx = &rt_iDiv;
645 /* ... nor an unsigned div instruction ... */
647 i_instr_record *map_Div = &records[n_records++].i_instr;
649 tp = new_type_method(ID("rt_uDiv"), 2, 1);
650 set_method_param_type(tp, 0, uint_tp);
651 set_method_param_type(tp, 1, uint_tp);
652 set_method_res_type(tp, 0, uint_tp);
654 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
655 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
656 rt_uDiv.mode = mode_T;
657 rt_uDiv.res_mode = mode_Iu;
658 rt_uDiv.mem_proj_nr = pn_Div_M;
659 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
660 rt_uDiv.exc_proj_nr = pn_Div_X_except;
661 rt_uDiv.exc_mem_proj_nr = pn_Div_M;
662 rt_uDiv.res_proj_nr = pn_Div_res;
664 set_entity_visibility(rt_uDiv.ent, visibility_external_allocated);
666 map_Div->kind = INTRINSIC_INSTR;
667 map_Div->op = op_Div;
668 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
669 map_Div->ctx = &rt_uDiv;
671 /* ... nor a signed mod instruction ... */
673 i_instr_record *map_Mod = &records[n_records++].i_instr;
675 tp = new_type_method(ID("rt_iMod"), 2, 1);
676 set_method_param_type(tp, 0, int_tp);
677 set_method_param_type(tp, 1, int_tp);
678 set_method_res_type(tp, 0, int_tp);
680 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
681 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
682 rt_iMod.mode = mode_T;
683 rt_iMod.res_mode = mode_Is;
684 rt_iMod.mem_proj_nr = pn_Mod_M;
685 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
686 rt_iMod.exc_proj_nr = pn_Mod_X_except;
687 rt_iMod.exc_mem_proj_nr = pn_Mod_M;
688 rt_iMod.res_proj_nr = pn_Mod_res;
690 set_entity_visibility(rt_iMod.ent, visibility_external_allocated);
692 map_Mod->kind = INTRINSIC_INSTR;
693 map_Mod->op = op_Mod;
694 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
695 map_Mod->ctx = &rt_iMod;
697 /* ... nor an unsigned mod. */
699 i_instr_record *map_Mod = &records[n_records++].i_instr;
701 tp = new_type_method(ID("rt_uMod"), 2, 1);
702 set_method_param_type(tp, 0, uint_tp);
703 set_method_param_type(tp, 1, uint_tp);
704 set_method_res_type(tp, 0, uint_tp);
706 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
707 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
708 rt_uMod.mode = mode_T;
709 rt_uMod.res_mode = mode_Iu;
710 rt_uMod.mem_proj_nr = pn_Mod_M;
711 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
712 rt_uMod.exc_proj_nr = pn_Mod_X_except;
713 rt_uMod.exc_mem_proj_nr = pn_Mod_M;
714 rt_uMod.res_proj_nr = pn_Mod_res;
716 set_entity_visibility(rt_uMod.ent, visibility_external_allocated);
718 map_Mod->kind = INTRINSIC_INSTR;
719 map_Mod->op = op_Mod;
720 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
721 map_Mod->ctx = &rt_uMod;
725 lower_intrinsics(records, n_records, /*part_block_used=*/0);
728 /*****************************************************************
729 * ____ _ _ _____ _____
730 * | _ \ | | | | |_ _|/ ____| /\
731 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
732 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
733 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
734 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
736 *****************************************************************/
738 static arm_isa_t arm_isa_template = {
740 &arm_isa_if, /* isa interface */
741 &arm_gp_regs[REG_SP], /* stack pointer */
742 &arm_gp_regs[REG_R11], /* base pointer */
743 -1, /* stack direction */
744 2, /* power of two stack alignment for calls, 2^2 == 4 */
745 NULL, /* main environment */
747 5, /* reload costs */
749 0, /* use generic register names instead of SP, LR, PC */
750 ARM_FPU_ARCH_FPE, /* FPU architecture */
751 NULL, /* current code generator */
755 * Initializes the backend ISA and opens the output file.
757 static arch_env_t *arm_init(FILE *file_handle) {
758 static int inited = 0;
764 isa = XMALLOC(arm_isa_t);
765 memcpy(isa, &arm_isa_template, sizeof(*isa));
770 be_emit_init(file_handle);
772 arm_create_opcodes(&arm_irn_ops);
773 arm_handle_intrinsics();
775 /* needed for the debug support */
776 be_gas_emit_switch_section(GAS_SECTION_TEXT);
777 be_emit_cstring(".Ltext0:\n");
778 be_emit_write_line();
780 /* we mark referenced global entities, so we can only emit those which
781 * are actually referenced. (Note: you mustn't use the type visited flag
782 * elsewhere in the backend)
784 inc_master_type_visited();
787 return &isa->arch_env;
793 * Closes the output file and frees the ISA structure.
795 static void arm_done(void *self) {
796 arm_isa_t *isa = self;
798 be_gas_emit_decls(isa->arch_env.main_env, 1);
806 * Report the number of register classes.
807 * If we don't have fp instructions, report only GP
808 * here to speed up register allocation (and makes dumps
809 * smaller and more readable).
811 static unsigned arm_get_n_reg_class(const void *self) {
817 * Return the register class with requested index.
819 static const arch_register_class_t *arm_get_reg_class(const void *self,
822 assert(i < N_CLASSES);
823 return &arm_reg_classes[i];
827 * Get the register class which shall be used to store a value of a given mode.
828 * @param self The this pointer.
829 * @param mode The mode in question.
830 * @return A register class which can hold values of the given mode.
832 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
834 if (mode_is_float(mode))
835 return &arm_reg_classes[CLASS_arm_fpa];
837 return &arm_reg_classes[CLASS_arm_gp];
841 * Produces the type which sits between the stack args and the locals on the stack.
842 * it will contain the return address and space to store the old base pointer.
843 * @return The Firm type modeling the ABI between type.
845 static ir_type *arm_get_between_type(void *self) {
846 static ir_type *between_type = NULL;
847 static ir_entity *old_bp_ent = NULL;
850 if (between_type == NULL) {
851 ir_entity *ret_addr_ent;
852 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
853 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
855 between_type = new_type_class(new_id_from_str("arm_between_type"));
856 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
857 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
859 set_entity_offset(old_bp_ent, 0);
860 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
861 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
869 be_abi_call_flags_bits_t flags;
870 const arch_env_t *arch_env;
874 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
876 arm_abi_env_t *env = XMALLOC(arm_abi_env_t);
877 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
878 env->flags = fl.bits;
880 env->arch_env = arch_env;
885 * Put all registers which are saved by the prologue/epilogue in a set.
887 * @param self The callback object.
888 * @param s The result set.
890 static void arm_abi_dont_save_regs(void *self, pset *s)
892 arm_abi_env_t *env = self;
893 if (env->flags.try_omit_fp)
894 pset_insert_ptr(s, env->arch_env->bp);
898 * Generate the routine prologue.
900 * @param self The callback object.
901 * @param mem A pointer to the mem node. Update this if you define new memory.
902 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
903 * @param stack_bias Points to the current stack bias, can be modified if needed.
905 * @return The register which shall be used as a stack frame base.
907 * All nodes which define registers in @p reg_map must keep @p reg_map current.
909 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias) {
910 arm_abi_env_t *env = self;
911 ir_node *keep, *store;
914 arch_register_class_t *gp;
916 ir_node *fp, *ip, *lr, *pc;
917 ir_node *sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
921 if (env->flags.try_omit_fp)
922 return env->arch_env->sp;
924 fp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
925 ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
926 lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
927 pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
929 gp = &arm_reg_classes[CLASS_arm_gp];
931 block = get_irg_start_block(irg);
933 ip = be_new_Copy(gp, irg, block, sp);
934 arch_set_irn_register(ip, &arm_gp_regs[REG_R12]);
935 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
937 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
939 sp = new_r_Proj(irg, block, store, env->arch_env->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
940 arch_set_irn_register(sp, env->arch_env->sp);
941 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
943 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
944 be_node_set_reg_class(keep, 1, gp);
945 arch_set_irn_register(keep, &arm_gp_regs[REG_R12]);
946 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
948 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp), 4);
949 arch_set_irn_register(fp, env->arch_env->bp);
950 fp = be_new_Copy(gp, irg, block, fp); // XXX Gammelfix: only be_ nodes can have the ignore flag set
951 arch_set_irn_register(fp, env->arch_env->bp);
952 be_node_set_flags(fp, BE_OUT_POS(0), arch_irn_flags_ignore);
954 be_abi_reg_map_set(reg_map, env->arch_env->bp, fp);
955 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
956 be_abi_reg_map_set(reg_map, env->arch_env->sp, sp);
957 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
958 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
960 return env->arch_env->bp;
964 * Builds the ARM epilogue
966 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
967 arm_abi_env_t *env = self;
968 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
969 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
970 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
971 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
973 // TODO: Activate Omit fp in epilogue
974 if (env->flags.try_omit_fp) {
975 curr_sp = be_new_IncSP(env->arch_env->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
977 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
978 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
979 arch_set_irn_register(curr_lr, &arm_gp_regs[REG_LR]);
980 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
982 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
983 arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]);
984 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
985 be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
989 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, 12);
991 //set_arm_req_out_all(sub12_node, sub12_req);
992 arch_set_irn_register(sub12_node, env->arch_env->sp);
993 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
995 //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
996 //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
997 //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
998 curr_bp = new_r_Proj(env->irg, bl, load_node, env->arch_env->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
999 curr_sp = new_r_Proj(env->irg, bl, load_node, env->arch_env->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
1000 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
1001 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
1002 arch_set_irn_register(curr_bp, env->arch_env->bp);
1003 arch_set_irn_register(curr_sp, env->arch_env->sp);
1004 arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]);
1006 be_abi_reg_map_set(reg_map, env->arch_env->sp, curr_sp);
1007 be_abi_reg_map_set(reg_map, env->arch_env->bp, curr_bp);
1008 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
1009 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
1012 static const be_abi_callbacks_t arm_abi_callbacks = {
1015 arm_get_between_type,
1016 arm_abi_dont_save_regs,
1023 * Get the ABI restrictions for procedure calls.
1024 * @param self The this pointer.
1025 * @param method_type The type of the method (procedure) in question.
1026 * @param abi The abi object to be modified
1028 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1032 int n = get_method_n_params(method_type);
1033 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1036 /* set abi flags for calls */
1037 call_flags.bits.left_to_right = 0;
1038 call_flags.bits.store_args_sequential = 0;
1039 /* call_flags.bits.try_omit_fp don't change this we can handle both */
1040 call_flags.bits.fp_free = 0;
1041 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1043 /* set stack parameter passing style */
1044 be_abi_call_set_flags(abi, call_flags, &arm_abi_callbacks);
1046 for (i = 0; i < n; i++) {
1047 /* reg = get reg for param i; */
1048 /* be_abi_call_param_reg(abi, i, reg); */
1050 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1052 tp = get_method_param_type(method_type, i);
1053 mode = get_type_mode(tp);
1054 be_abi_call_param_stack(abi, i, mode, 4, 0, 0);
1058 /* set return registers */
1059 n = get_method_n_ress(method_type);
1061 assert(n <= 2 && "more than two results not supported");
1063 /* In case of 64bit returns, we will have two 32bit values */
1065 tp = get_method_res_type(method_type, 0);
1066 mode = get_type_mode(tp);
1068 assert(!mode_is_float(mode) && "two FP results not supported");
1070 tp = get_method_res_type(method_type, 1);
1071 mode = get_type_mode(tp);
1073 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1075 be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0]);
1076 be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1]);
1077 } else if (n == 1) {
1078 const arch_register_t *reg;
1080 tp = get_method_res_type(method_type, 0);
1081 assert(is_atomic_type(tp));
1082 mode = get_type_mode(tp);
1084 reg = mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0];
1085 be_abi_call_res_reg(abi, 0, reg);
1089 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1091 if(!is_arm_irn(irn))
1098 * Initializes the code generator interface.
1100 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1102 return &arm_code_gen_if;
1105 list_sched_selector_t arm_sched_selector;
1108 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1110 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1112 memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
1113 /* arm_sched_selector.exectime = arm_sched_exectime; */
1114 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1115 return &arm_sched_selector;
1119 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
1125 * Returns the necessary byte alignment for storing a register of given class.
1127 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1130 /* ARM is a 32 bit CPU, no need for other alignment */
1134 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1138 panic("Unimplemented arm_get_allowed_execution_units()");
1141 static const be_machine_t *arm_get_machine(const void *self) {
1144 panic("Unimplemented arm_get_machine()");
1148 * Return irp irgs in the desired order.
1150 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
1157 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1158 * @return 1 if allowed, 0 otherwise
1160 static int arm_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) {
1161 ir_node *cmp, *cmp_a, *phi;
1165 /* currently Psi support is not implemented */
1168 /* we don't want long long Psi */
1169 #define IS_BAD_PSI_MODE(mode) (!mode_is_float(mode) && get_mode_size_bits(mode) > 32)
1171 if (get_irn_mode(sel) != mode_b)
1174 cmp = get_Proj_pred(sel);
1175 cmp_a = get_Cmp_left(cmp);
1176 mode = get_irn_mode(cmp_a);
1178 if (IS_BAD_PSI_MODE(mode))
1181 /* check the Phi nodes */
1182 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1183 ir_node *pred_i = get_irn_n(phi, i);
1184 ir_node *pred_j = get_irn_n(phi, j);
1185 ir_mode *mode_i = get_irn_mode(pred_i);
1186 ir_mode *mode_j = get_irn_mode(pred_j);
1188 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1192 #undef IS_BAD_PSI_MODE
1197 static asm_constraint_flags_t arm_parse_asm_constraint(const void *self, const char **c)
1199 /* asm not supported */
1202 return ASM_CONSTRAINT_FLAG_INVALID;
1205 static int arm_is_valid_clobber(const void *self, const char *clobber)
1213 * Returns the libFirm configuration parameter for this backend.
1215 static const backend_params *arm_get_libfirm_params(void) {
1216 static const ir_settings_if_conv_t ifconv = {
1217 4, /* maxdepth, doesn't matter for Psi-conversion */
1218 arm_is_psi_allowed /* allows or disallows Psi creation for given selector */
1220 static ir_settings_arch_dep_t ad = {
1222 1, /* Muls are fast enough on ARM but ... */
1223 31, /* ... one shift would be possible better */
1224 NULL, /* no evaluator function */
1225 0, /* SMUL is needed, only in Arch M */
1226 0, /* UMUL is needed, only in Arch M */
1227 32, /* SMUL & UMUL available for 32 bit */
1229 static backend_params p = {
1230 1, /* need dword lowering */
1231 0, /* don't support inline assembler yet */
1232 0, /* no immediate floating point mode. */
1233 NULL, /* no additional opcodes */
1234 NULL, /* will be set later */
1235 NULL, /* but yet no creator function */
1236 NULL, /* context for create_intrinsic_fkt */
1237 NULL, /* will be set below */
1238 NULL /* no immediate fp mode */
1242 p.if_conv_info = &ifconv;
1246 /* fpu set architectures. */
1247 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1248 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1249 { "fpe", ARM_FPU_ARCH_FPE },
1250 { "fpa", ARM_FPU_ARCH_FPA },
1251 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1252 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1253 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1257 static lc_opt_enum_int_var_t arch_fpu_var = {
1258 &arm_isa_template.fpu_arch, arm_fpu_items
1261 static const lc_opt_table_entry_t arm_options[] = {
1262 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1263 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1267 const arch_isa_if_t arm_isa_if = {
1270 arm_get_n_reg_class,
1272 arm_get_reg_class_for_mode,
1274 arm_get_code_generator_if,
1275 arm_get_list_sched_selector,
1276 arm_get_ilp_sched_selector,
1277 arm_get_reg_class_alignment,
1278 arm_get_libfirm_params,
1279 arm_get_allowed_execution_units,
1282 NULL, /* mark remat */
1283 arm_parse_asm_constraint,
1284 arm_is_valid_clobber
1287 void be_init_arch_arm(void)
1289 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1290 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1292 lc_opt_add_table(arm_grp, arm_options);
1294 be_register_isa_if("arm", &arm_isa_if);
1296 arm_init_transform();
1300 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);