2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist
29 #include "lc_opts_enum.h"
37 #include "iroptimize.h"
47 #include "../bearch.h"
48 #include "../benode.h"
49 #include "../belower.h"
50 #include "../besched.h"
52 #include "../bemachine.h"
53 #include "../bemodule.h"
55 #include "../bespillslots.h"
56 #include "../begnuas.h"
57 #include "../belistsched.h"
58 #include "../beflags.h"
60 #include "bearch_arm_t.h"
62 #include "arm_new_nodes.h"
63 #include "gen_arm_regalloc_if.h"
64 #include "arm_transform.h"
65 #include "arm_optimize.h"
66 #include "arm_emitter.h"
67 #include "arm_map_regs.h"
69 static arch_irn_class_t arm_classify(const ir_node *irn)
72 /* TODO: we should mark reload/spill instructions and classify them here */
73 return arch_irn_class_none;
76 static ir_entity *arm_get_frame_entity(const ir_node *irn)
78 const arm_attr_t *attr = get_arm_attr_const(irn);
80 if (is_arm_FrameAddr(irn)) {
81 const arm_SymConst_attr_t *attr = get_arm_SymConst_attr_const(irn);
84 if (attr->is_load_store) {
85 const arm_load_store_attr_t *load_store_attr
86 = get_arm_load_store_attr_const(irn);
87 if (load_store_attr->is_frame_entity) {
88 return load_store_attr->entity;
95 * This function is called by the generic backend to correct offsets for
96 * nodes accessing the stack.
98 static void arm_set_stack_bias(ir_node *irn, int bias)
100 if (is_arm_FrameAddr(irn)) {
101 arm_SymConst_attr_t *attr = get_arm_SymConst_attr(irn);
102 attr->fp_offset += bias;
104 arm_load_store_attr_t *attr = get_arm_load_store_attr(irn);
105 assert(attr->base.is_load_store);
106 attr->offset += bias;
110 static int arm_get_sp_bias(const ir_node *irn)
112 /* We don't have any nodes changing the stack pointer.
113 We probably want to support post-/pre increment/decrement later */
118 /* fill register allocator interface */
120 static const arch_irn_ops_t arm_irn_ops = {
122 arm_get_frame_entity,
125 NULL, /* get_inverse */
126 NULL, /* get_op_estimated_cost */
127 NULL, /* possible_memory_operand */
128 NULL, /* perform_memory_operand */
132 * Transforms the standard Firm graph into
135 static void arm_prepare_graph(ir_graph *irg)
137 /* transform nodes into assembler instructions */
138 arm_transform_graph(irg);
140 /* do local optimizations (mainly CSE) */
141 local_optimize_graph(irg);
143 /* do code placement, to optimize the position of constants */
148 * Called immediately before emit phase.
150 static void arm_finish_irg(ir_graph *irg)
152 /* do peephole optimizations and fix stack offsets */
153 arm_peephole_optimization(irg);
156 static void arm_before_ra(ir_graph *irg)
158 be_sched_fix_flags(irg, &arm_reg_classes[CLASS_arm_flags], NULL, NULL);
161 static void transform_Reload(ir_node *node)
163 ir_node *block = get_nodes_block(node);
164 dbg_info *dbgi = get_irn_dbg_info(node);
165 ir_node *ptr = get_irn_n(node, be_pos_Reload_frame);
166 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
167 ir_mode *mode = get_irn_mode(node);
168 ir_entity *entity = be_get_frame_entity(node);
169 const arch_register_t *reg;
173 ir_node *sched_point = sched_prev(node);
175 load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true);
176 sched_add_after(sched_point, load);
179 proj = new_rd_Proj(dbgi, load, mode, pn_arm_Ldr_res);
181 reg = arch_get_irn_register(node);
182 arch_set_irn_register(proj, reg);
184 exchange(node, proj);
187 static void transform_Spill(ir_node *node)
189 ir_node *block = get_nodes_block(node);
190 dbg_info *dbgi = get_irn_dbg_info(node);
191 ir_node *ptr = get_irn_n(node, be_pos_Spill_frame);
192 ir_graph *irg = get_irn_irg(node);
193 ir_node *mem = new_r_NoMem(irg);
194 ir_node *val = get_irn_n(node, be_pos_Spill_val);
195 ir_mode *mode = get_irn_mode(val);
196 ir_entity *entity = be_get_frame_entity(node);
197 ir_node *sched_point;
200 sched_point = sched_prev(node);
201 store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0,
205 sched_add_after(sched_point, store);
207 exchange(node, store);
210 static void arm_after_ra_walker(ir_node *block, void *data)
212 ir_node *node, *prev;
215 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
216 prev = sched_prev(node);
218 if (be_is_Reload(node)) {
219 transform_Reload(node);
220 } else if (be_is_Spill(node)) {
221 transform_Spill(node);
226 static void arm_collect_frame_entity_nodes(ir_node *node, void *data)
228 be_fec_env_t *env = (be_fec_env_t*)data;
232 const arm_load_store_attr_t *attr;
234 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
235 mode = get_irn_mode(node);
236 align = get_mode_size_bytes(mode);
237 be_node_needs_frame_entity(env, node, mode, align);
241 switch (get_arm_irn_opcode(node)) {
249 attr = get_arm_load_store_attr_const(node);
250 entity = attr->entity;
251 mode = attr->load_store_mode;
252 align = get_mode_size_bytes(mode);
255 if (!attr->is_frame_entity)
257 be_node_needs_frame_entity(env, node, mode, align);
260 static void arm_set_frame_entity(ir_node *node, ir_entity *entity)
262 if (is_be_node(node)) {
263 be_node_set_frame_entity(node, entity);
265 arm_load_store_attr_t *attr = get_arm_load_store_attr(node);
266 attr->entity = entity;
270 static void arm_after_ra(ir_graph *irg)
272 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
274 irg_walk_graph(irg, NULL, arm_collect_frame_entity_nodes, fec_env);
275 be_assign_entities(fec_env, arm_set_frame_entity);
276 be_free_frame_entity_coalescer(fec_env);
278 irg_block_walk_graph(irg, NULL, arm_after_ra_walker, NULL);
282 * Initializes the code generator.
284 static void arm_init_graph(ir_graph *irg)
291 * Maps all intrinsic calls that the backend support
292 * and map all instructions the backend did not support
295 static void arm_handle_intrinsics(void)
297 ir_type *tp, *int_tp, *uint_tp;
301 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
303 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
305 int_tp = get_type_for_mode(mode_Is);
306 uint_tp = get_type_for_mode(mode_Iu);
308 /* ARM has neither a signed div instruction ... */
310 i_instr_record *map_Div = &records[n_records++].i_instr;
312 tp = new_type_method(2, 1);
313 set_method_param_type(tp, 0, int_tp);
314 set_method_param_type(tp, 1, int_tp);
315 set_method_res_type(tp, 0, int_tp);
317 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
318 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
319 rt_iDiv.mode = mode_T;
320 rt_iDiv.res_mode = mode_Is;
321 rt_iDiv.mem_proj_nr = pn_Div_M;
322 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
323 rt_iDiv.exc_proj_nr = pn_Div_X_except;
324 rt_iDiv.exc_mem_proj_nr = pn_Div_M;
325 rt_iDiv.res_proj_nr = pn_Div_res;
327 add_entity_linkage(rt_iDiv.ent, IR_LINKAGE_CONSTANT);
328 set_entity_visibility(rt_iDiv.ent, ir_visibility_external);
330 map_Div->kind = INTRINSIC_INSTR;
331 map_Div->op = op_Div;
332 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
333 map_Div->ctx = &rt_iDiv;
335 /* ... nor an unsigned div instruction ... */
337 i_instr_record *map_Div = &records[n_records++].i_instr;
339 tp = new_type_method(2, 1);
340 set_method_param_type(tp, 0, uint_tp);
341 set_method_param_type(tp, 1, uint_tp);
342 set_method_res_type(tp, 0, uint_tp);
344 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
345 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
346 rt_uDiv.mode = mode_T;
347 rt_uDiv.res_mode = mode_Iu;
348 rt_uDiv.mem_proj_nr = pn_Div_M;
349 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
350 rt_uDiv.exc_proj_nr = pn_Div_X_except;
351 rt_uDiv.exc_mem_proj_nr = pn_Div_M;
352 rt_uDiv.res_proj_nr = pn_Div_res;
354 set_entity_visibility(rt_uDiv.ent, ir_visibility_external);
356 map_Div->kind = INTRINSIC_INSTR;
357 map_Div->op = op_Div;
358 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
359 map_Div->ctx = &rt_uDiv;
361 /* ... nor a signed mod instruction ... */
363 i_instr_record *map_Mod = &records[n_records++].i_instr;
365 tp = new_type_method(2, 1);
366 set_method_param_type(tp, 0, int_tp);
367 set_method_param_type(tp, 1, int_tp);
368 set_method_res_type(tp, 0, int_tp);
370 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
371 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
372 rt_iMod.mode = mode_T;
373 rt_iMod.res_mode = mode_Is;
374 rt_iMod.mem_proj_nr = pn_Mod_M;
375 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
376 rt_iMod.exc_proj_nr = pn_Mod_X_except;
377 rt_iMod.exc_mem_proj_nr = pn_Mod_M;
378 rt_iMod.res_proj_nr = pn_Mod_res;
380 set_entity_visibility(rt_iMod.ent, ir_visibility_external);
382 map_Mod->kind = INTRINSIC_INSTR;
383 map_Mod->op = op_Mod;
384 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
385 map_Mod->ctx = &rt_iMod;
387 /* ... nor an unsigned mod. */
389 i_instr_record *map_Mod = &records[n_records++].i_instr;
391 tp = new_type_method(2, 1);
392 set_method_param_type(tp, 0, uint_tp);
393 set_method_param_type(tp, 1, uint_tp);
394 set_method_res_type(tp, 0, uint_tp);
396 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
397 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
398 rt_uMod.mode = mode_T;
399 rt_uMod.res_mode = mode_Iu;
400 rt_uMod.mem_proj_nr = pn_Mod_M;
401 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
402 rt_uMod.exc_proj_nr = pn_Mod_X_except;
403 rt_uMod.exc_mem_proj_nr = pn_Mod_M;
404 rt_uMod.res_proj_nr = pn_Mod_res;
406 set_entity_visibility(rt_uMod.ent, ir_visibility_external);
408 map_Mod->kind = INTRINSIC_INSTR;
409 map_Mod->op = op_Mod;
410 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
411 map_Mod->ctx = &rt_uMod;
415 lower_intrinsics(records, n_records, /*part_block_used=*/0);
418 extern const arch_isa_if_t arm_isa_if;
419 static arm_isa_t arm_isa_template = {
421 &arm_isa_if, /* isa interface */
426 &arm_registers[REG_SP], /* stack pointer */
427 &arm_registers[REG_R11], /* base pointer */
428 &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */
429 -1, /* stack direction */
430 2, /* power of two stack alignment for calls, 2^2 == 4 */
431 NULL, /* main environment */
433 5, /* reload costs */
434 true, /* we do have custom abi handling */
436 ARM_FPU_ARCH_FPE, /* FPU architecture */
440 * Initializes the backend ISA and opens the output file.
442 static arch_env_t *arm_init(FILE *file_handle)
444 arm_isa_t *isa = XMALLOC(arm_isa_t);
445 memcpy(isa, &arm_isa_template, sizeof(*isa));
449 be_emit_init(file_handle);
451 arm_create_opcodes(&arm_irn_ops);
452 arm_handle_intrinsics();
454 be_gas_emit_types = false;
456 /* needed for the debug support */
457 be_gas_emit_switch_section(GAS_SECTION_TEXT);
458 be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
459 be_emit_write_line();
467 * Closes the output file and frees the ISA structure.
469 static void arm_done(void *self)
471 arm_isa_t *isa = (arm_isa_t*)self;
473 be_gas_emit_decls(isa->base.main_env);
480 * Get the register class which shall be used to store a value of a given mode.
481 * @param self The this pointer.
482 * @param mode The mode in question.
483 * @return A register class which can hold values of the given mode.
485 static const arch_register_class_t *arm_get_reg_class_for_mode(const ir_mode *mode)
487 if (mode_is_float(mode))
488 return &arm_reg_classes[CLASS_arm_fpa];
490 return &arm_reg_classes[CLASS_arm_gp];
494 * Returns the necessary byte alignment for storing a register of given class.
496 static int arm_get_reg_class_alignment(const arch_register_class_t *cls)
499 /* ARM is a 32 bit CPU, no need for other alignment */
504 * Return irp irgs in the desired order.
506 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list)
514 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
515 * @return 1 if allowed, 0 otherwise
517 static int arm_is_mux_allowed(ir_node *sel, ir_node *mux_false,
526 static asm_constraint_flags_t arm_parse_asm_constraint(const char **c)
528 /* asm not supported */
530 return ASM_CONSTRAINT_FLAG_INVALID;
533 static int arm_is_valid_clobber(const char *clobber)
539 static void arm_lower_for_target(void)
542 int n_irgs = get_irp_n_irgs();
544 for (i = 0; i < n_irgs; ++i) {
545 ir_graph *irg = get_irp_irg(i);
546 lower_switch(irg, 256, true);
551 * Returns the libFirm configuration parameter for this backend.
553 static const backend_params *arm_get_libfirm_params(void)
555 static ir_settings_arch_dep_t ad = {
557 1, /* Muls are fast enough on ARM but ... */
558 31, /* ... one shift would be possible better */
559 NULL, /* no evaluator function */
560 0, /* SMUL is needed, only in Arch M */
561 0, /* UMUL is needed, only in Arch M */
562 32, /* SMUL & UMUL available for 32 bit */
564 static backend_params p = {
565 0, /* don't support inline assembler yet */
566 1, /* support Rotl nodes */
568 &ad, /* will be set later */
569 arm_is_mux_allowed, /* allow_ifconv function */
570 NULL, /* float arithmetic mode (TODO) */
571 0, /* no trampoline support: size 0 */
572 0, /* no trampoline support: align 0 */
573 NULL, /* no trampoline support: no trampoline builder */
574 4 /* alignment of stack parameter */
580 /* fpu set architectures. */
581 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
582 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
583 { "fpe", ARM_FPU_ARCH_FPE },
584 { "fpa", ARM_FPU_ARCH_FPA },
585 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
586 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
587 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
591 static lc_opt_enum_int_var_t arch_fpu_var = {
592 &arm_isa_template.fpu_arch, arm_fpu_items
595 static const lc_opt_table_entry_t arm_options[] = {
596 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
600 const arch_isa_if_t arm_isa_if = {
602 arm_lower_for_target,
604 NULL, /* handle_intrinsics */
605 arm_get_reg_class_for_mode,
607 arm_get_reg_class_alignment,
608 arm_get_libfirm_params,
610 NULL, /* mark remat */
611 arm_parse_asm_constraint,
612 arm_is_valid_clobber,
615 NULL, /* get_pic_base */
616 NULL, /* before_abi */
624 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);
625 void be_init_arch_arm(void)
627 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
628 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
630 lc_opt_add_table(arm_grp, arm_options);
632 be_register_isa_if("arm", &arm_isa_if);
634 arm_init_transform();