1 /* The main arm backend driver file. */
9 #include <libcore/lc_opts.h>
10 #include <libcore/lc_opts_enum.h>
11 #endif /* WITH_LIBCORE */
13 #include "pseudo_irg.h"
19 #include "lower_intrinsics.h"
24 #include "../bearch.h" /* the general register allocator interface */
25 #include "../benode_t.h"
26 #include "../belower.h"
27 #include "../besched_t.h"
31 #include "bearch_arm_t.h"
33 #include "arm_new_nodes.h" /* arm nodes interface */
34 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
35 #include "arm_gen_decls.h" /* interface declaration emitter */
36 #include "arm_transform.h"
37 #include "arm_emitter.h"
38 #include "arm_map_regs.h"
40 #define DEBUG_MODULE "firm.be.arm.isa"
42 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
43 static set *cur_reg_set = NULL;
45 /**************************************************
48 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
49 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
50 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
51 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
54 **************************************************/
56 static ir_node *my_skip_proj(const ir_node *n) {
63 * Return register requirements for a arm node.
64 * If the node returns a tuple (mode_T) then the proj's
65 * will be asked for this information.
67 static const arch_register_req_t *arm_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
68 const arm_register_req_t *irn_req;
69 long node_pos = pos == -1 ? 0 : pos;
70 ir_mode *mode = get_irn_mode(irn);
71 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
73 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
74 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
78 if (mode == mode_T && pos < 0) {
79 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
83 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
86 /* in case of a proj, we need to get the correct OUT slot */
87 /* of the node corresponding to the proj number */
89 node_pos = arm_translate_proj_pos(irn);
95 irn = my_skip_proj(irn);
97 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
100 /* get requirements for our own nodes */
101 if (is_arm_irn(irn)) {
103 irn_req = get_arm_in_req(irn, pos);
106 irn_req = get_arm_out_req(irn, node_pos);
109 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
111 memcpy(req, &(irn_req->req), sizeof(*req));
113 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
114 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
115 req->other_same = get_irn_n(irn, irn_req->same_pos);
118 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
119 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
120 req->other_different = get_irn_n(irn, irn_req->different_pos);
123 /* get requirements for FIRM nodes */
125 /* treat Phi like Const with default requirements */
127 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
129 if (mode_is_float(mode)) {
130 memcpy(req, &(arm_default_req_arm_fpa.req), sizeof(*req));
132 else if (mode_is_int(mode) || mode_is_reference(mode)) {
133 memcpy(req, &(arm_default_req_arm_gp.req), sizeof(*req));
135 else if (mode == mode_T || mode == mode_M) {
136 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
140 assert(0 && "unsupported Phi-Mode");
144 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
152 static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
157 if (get_irn_mode(irn) == mode_X) {
161 pos = arm_translate_proj_pos(irn);
162 irn = my_skip_proj(irn);
165 if (is_arm_irn(irn)) {
166 const arch_register_t **slots;
168 slots = get_arm_slots(irn);
172 /* here we set the registers for the Phi nodes */
173 arm_set_firm_reg(irn, reg, cur_reg_set);
177 static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) {
179 const arch_register_t *reg = NULL;
183 if (get_irn_mode(irn) == mode_X) {
187 pos = arm_translate_proj_pos(irn);
188 irn = my_skip_proj(irn);
191 if (is_arm_irn(irn)) {
192 const arch_register_t **slots;
193 slots = get_arm_slots(irn);
197 reg = arm_get_firm_reg(irn, cur_reg_set);
203 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
204 irn = my_skip_proj(irn);
207 return arch_irn_class_branch;
209 else if (is_arm_irn(irn)) {
210 return arch_irn_class_normal;
216 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
217 irn = my_skip_proj(irn);
219 if (is_arm_irn(irn)) {
220 return get_arm_flags(irn);
222 else if (is_Unknown(irn)) {
223 return arch_irn_flags_ignore;
229 static entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
230 /* TODO: return the entity assigned to the frame */
234 static void arm_set_frame_entity(const void *self, ir_node *irn, entity *ent) {
235 /* TODO: set the entity assigned to the frame */
239 * This function is called by the generic backend to correct offsets for
240 * nodes accessing the stack.
242 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
243 /* TODO: correct offset if irn accesses the stack */
246 static int arm_get_sp_bias(const void *self, const ir_node *irn) {
250 /* fill register allocator interface */
252 static const arch_irn_ops_if_t arm_irn_ops_if = {
258 arm_get_frame_entity,
259 arm_set_frame_entity,
262 NULL, /* get_inverse */
263 NULL, /* get_op_estimated_cost */
264 NULL, /* possible_memory_operand */
265 NULL, /* perform_memory_operand */
268 arm_irn_ops_t arm_irn_ops = {
275 /**************************************************
278 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
279 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
280 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
281 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
284 **************************************************/
287 * Transforms the standard Firm graph into
290 static void arm_prepare_graph(void *self) {
291 arm_code_gen_t *cg = self;
293 arm_register_transformers();
294 irg_walk_blkwise_graph(cg->irg, arm_move_consts, arm_transform_node, cg);
300 * Called immediately before emit phase.
302 static void arm_finish_irg(void *self) {
303 /* TODO: - fix offsets for nodes accessing stack
310 * These are some hooks which must be filled but are probably not needed.
312 static void arm_before_sched(void *self) {
313 /* Some stuff you need to do after scheduling but before register allocation */
316 static void arm_before_ra(void *self) {
317 /* Some stuff you need to do immediately after register allocation */
322 * Emits the code, closes the output file and frees
323 * the code generator interface.
325 static void arm_emit_and_done(void *self) {
326 arm_code_gen_t *cg = self;
327 ir_graph *irg = cg->irg;
328 FILE *out = cg->isa->out;
330 if (cg->emit_decls) {
335 dump_ir_block_graph_sched(irg, "-arm-finished");
336 arm_gen_routine(out, irg, cg);
340 /* de-allocate code generator */
341 del_set(cg->reg_set);
346 * Move a double floating point value into an integer register.
347 * Place the move operation into block bl.
349 * Handle some special cases here:
350 * 1.) A constant: simply split into two
351 * 2.) A load: siply split into two
353 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
354 ir_node **resH, ir_node **resL) {
356 tarval *tv = get_Const_tarval(arg);
359 /* get the upper 32 bits */
360 v = get_tarval_sub_bits(tv, 7);
361 v = (v << 8) | get_tarval_sub_bits(tv, 6);
362 v = (v << 8) | get_tarval_sub_bits(tv, 5);
363 v = (v << 8) | get_tarval_sub_bits(tv, 4);
364 *resH = new_Const_long(mode_Is, v);
366 /* get the lower 32 bits */
367 v = get_tarval_sub_bits(tv, 3);
368 v = (v << 8) | get_tarval_sub_bits(tv, 2);
369 v = (v << 8) | get_tarval_sub_bits(tv, 1);
370 v = (v << 8) | get_tarval_sub_bits(tv, 0);
371 *resL = new_Const_long(mode_Is, v);
373 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
374 /* FIXME: handling of low/high depends on LE/BE here */
378 ir_graph *irg = current_ir_graph;
381 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
383 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
384 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
385 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
391 * Move a single floating point value into an integer register.
392 * Place the move operation into block bl.
394 * Handle some special cases here:
395 * 1.) A constant: simply move
396 * 2.) A load: siply load
398 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) {
400 tarval *tv = get_Const_tarval(arg);
403 /* get the lower 32 bits */
404 v = get_tarval_sub_bits(tv, 3);
405 v = (v << 8) | get_tarval_sub_bits(tv, 2);
406 v = (v << 8) | get_tarval_sub_bits(tv, 1);
407 v = (v << 8) | get_tarval_sub_bits(tv, 0);
408 return new_Const_long(mode_Is, v);
410 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
413 load = skip_Proj(arg);
420 * Convert the arguments of a call to support the
421 * ARM calling convention of general purpose AND floating
424 static void handle_calls(ir_node *call, void *env)
426 arm_code_gen_t *cg = env;
427 int i, j, n, size, idx, flag, n_param, n_res;
428 ir_type *mtp, *new_mtd, *new_tp[5];
429 ir_node *new_in[5], **in;
435 /* check, if we need conversions */
436 n = get_Call_n_params(call);
437 mtp = get_Call_type(call);
438 assert(get_method_n_params(mtp) == n);
440 /* it's always enough to handle the first 4 parameters */
443 flag = size = idx = 0;
444 bl = get_nodes_block(call);
445 for (i = 0; i < n; ++i) {
446 ir_type *param_tp = get_method_param_type(mtp, i);
448 if (is_compound_type(param_tp)) {
449 /* an aggregate parameter: bad case */
453 /* a primitive parameter */
454 ir_mode *mode = get_type_mode(param_tp);
456 if (mode_is_float(mode)) {
457 if (get_mode_size_bits(mode) > 32) {
458 ir_node *mem = get_Call_mem(call);
460 /* Beware: ARM wants the high part first */
462 new_tp[idx] = cg->int_tp;
463 new_tp[idx+1] = cg->int_tp;
464 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
466 set_Call_mem(call, mem);
470 new_tp[idx] = cg->int_tp;
471 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
478 new_tp[idx] = param_tp;
479 new_in[idx] = get_Call_param(call, i);
488 /* if flag is NOT set, no need to translate the method type */
492 /* construct a new method type */
494 n_param = get_method_n_params(mtp) - n + idx;
495 n_res = get_method_n_ress(mtp);
496 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
498 for (i = 0; i < idx; ++i)
499 set_method_param_type(new_mtd, i, new_tp[i]);
500 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
501 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
502 for (i = 0; i < n_res; ++i)
503 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
505 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
506 set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp));
508 if (is_lowered_type(mtp)) {
509 mtp = get_associated_type(mtp);
511 set_lowered_type(mtp, new_mtd);
513 set_Call_type(call, new_mtd);
515 /* calculate new in array of the Call */
516 NEW_ARR_A(ir_node *, in, n_param + 2);
517 for (i = 0; i < idx; ++i)
518 in[2 + i] = new_in[i];
519 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
520 in[2 + j++] = get_Call_param(call, i);
522 in[0] = get_Call_mem(call);
523 in[1] = get_Call_ptr(call);
525 /* finally, change the call inputs */
526 set_irn_in(call, n_param + 2, in);
530 * Handle graph transformations before the abi converter does its work.
532 static void arm_before_abi(void *self) {
533 arm_code_gen_t *cg = self;
535 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
538 static void *arm_cg_init(const be_irg_t *birg);
540 static const arch_code_generator_if_t arm_code_gen_if = {
542 arm_before_abi, /* before abi introduce */
544 arm_before_sched, /* before scheduling hook */
545 arm_before_ra, /* before register allocation hook */
546 NULL, /* after register allocation */
552 * Initializes the code generator.
554 static void *arm_cg_init(const be_irg_t *birg) {
555 static ir_type *int_tp = NULL;
556 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
560 /* create an integer type with machine size */
561 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
564 cg = xmalloc(sizeof(*cg));
565 cg->impl = &arm_code_gen_if;
567 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
568 cg->arch_env = birg->main_env->arch_env;
574 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
578 if (isa->num_codegens > 1)
583 cur_reg_set = cg->reg_set;
587 /* enter the current code generator */
590 return (arch_code_generator_t *)cg;
595 * Maps all intrinsic calls that the backend support
596 * and map all instructions the backend did not support
599 static void arm_handle_intrinsics(void) {
600 ir_type *tp, *int_tp, *uint_tp;
604 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
606 int_tp = new_type_primitive(ID("int"), mode_Is);
607 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
609 /* ARM has neither a signed div instruction ... */
612 i_instr_record *map_Div = &records[n_records++].i_instr;
614 tp = new_type_method(ID("rt_iDiv"), 2, 1);
615 set_method_param_type(tp, 0, int_tp);
616 set_method_param_type(tp, 1, int_tp);
617 set_method_res_type(tp, 0, int_tp);
619 rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
620 rt_Div.mode = mode_T;
621 rt_Div.mem_proj_nr = pn_Div_M;
622 rt_Div.exc_proj_nr = pn_Div_X_except;
623 rt_Div.exc_mem_proj_nr = pn_Div_M;
624 rt_Div.res_proj_nr = pn_Div_res;
626 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
628 map_Div->kind = INTRINSIC_INSTR;
629 map_Div->op = op_Div;
630 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
631 map_Div->ctx = &rt_Div;
633 /* ... nor a signed div instruction ... */
636 i_instr_record *map_Div = &records[n_records++].i_instr;
638 tp = new_type_method(ID("rt_uDiv"), 2, 1);
639 set_method_param_type(tp, 0, uint_tp);
640 set_method_param_type(tp, 1, uint_tp);
641 set_method_res_type(tp, 0, uint_tp);
643 rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
644 rt_Div.mode = mode_T;
645 rt_Div.mem_proj_nr = pn_Div_M;
646 rt_Div.exc_proj_nr = pn_Div_X_except;
647 rt_Div.exc_mem_proj_nr = pn_Div_M;
648 rt_Div.res_proj_nr = pn_Div_res;
650 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
652 map_Div->kind = INTRINSIC_INSTR;
653 map_Div->op = op_Div;
654 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
655 map_Div->ctx = &rt_Div;
657 /* ... nor a signed mod instruction ... */
660 i_instr_record *map_Mod = &records[n_records++].i_instr;
662 tp = new_type_method(ID("rt_iMod"), 2, 1);
663 set_method_param_type(tp, 0, int_tp);
664 set_method_param_type(tp, 1, int_tp);
665 set_method_res_type(tp, 0, int_tp);
667 rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
668 rt_Mod.mode = mode_T;
669 rt_Mod.mem_proj_nr = pn_Mod_M;
670 rt_Mod.exc_proj_nr = pn_Mod_X_except;
671 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
672 rt_Mod.res_proj_nr = pn_Mod_res;
674 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
676 map_Mod->kind = INTRINSIC_INSTR;
677 map_Mod->op = op_Mod;
678 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
679 map_Mod->ctx = &rt_Mod;
681 /* ... nor a unsigned mod. */
684 i_instr_record *map_Mod = &records[n_records++].i_instr;
686 tp = new_type_method(ID("rt_uMod"), 2, 1);
687 set_method_param_type(tp, 0, uint_tp);
688 set_method_param_type(tp, 1, uint_tp);
689 set_method_res_type(tp, 0, uint_tp);
691 rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
692 rt_Mod.mode = mode_T;
693 rt_Mod.mem_proj_nr = pn_Mod_M;
694 rt_Mod.exc_proj_nr = pn_Mod_X_except;
695 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
696 rt_Mod.res_proj_nr = pn_Mod_res;
698 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
700 map_Mod->kind = INTRINSIC_INSTR;
701 map_Mod->op = op_Mod;
702 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
703 map_Mod->ctx = &rt_Mod;
707 lower_intrinsics(records, n_records);
710 /*****************************************************************
711 * ____ _ _ _____ _____
712 * | _ \ | | | | |_ _|/ ____| /\
713 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
714 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
715 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
716 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
718 *****************************************************************/
720 static arm_isa_t arm_isa_template = {
721 &arm_isa_if, /* isa interface */
722 &arm_gp_regs[REG_SP], /* stack pointer */
723 &arm_gp_regs[REG_R11], /* base pointer */
724 -1, /* stack direction */
725 0, /* number of codegenerator objects */
726 0, /* use generic register names instead of SP, LR, PC */
727 NULL, /* current code generator */
728 NULL, /* output file */
729 ARM_FPU_ARCH_FPE, /* FPU architecture */
733 * Initializes the backend ISA and opens the output file.
735 static void *arm_init(FILE *file_handle) {
736 static int inited = 0;
742 isa = xmalloc(sizeof(*isa));
743 memcpy(isa, &arm_isa_template, sizeof(*isa));
745 arm_register_init(isa);
746 if (isa->gen_reg_names) {
747 /* patch register names */
748 arm_gp_regs[REG_R11].name = "r11";
749 arm_gp_regs[REG_SP].name = "r13";
750 arm_gp_regs[REG_LR].name = "r14";
751 arm_gp_regs[REG_PC].name = "r15";
755 isa->out = file_handle;
757 arm_create_opcodes();
758 arm_handle_intrinsics();
759 arm_switch_section(NULL, NO_SECTION);
768 * frees the ISA structure.
770 static void arm_done(void *self) {
776 * Report the number of register classes.
777 * If we don't have fp instructions, report only GP
778 * here to speed up register allocation (and makes dumps
779 * smaller and more readable).
781 static int arm_get_n_reg_class(const void *self) {
782 const arm_isa_t *isa = self;
784 return isa->cg->have_fp ? 2 : 1;
788 * Return the register class with requested index.
790 static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
791 return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa];
795 * Get the register class which shall be used to store a value of a given mode.
796 * @param self The this pointer.
797 * @param mode The mode in question.
798 * @return A register class which can hold values of the given mode.
800 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
801 if (mode_is_float(mode))
802 return &arm_reg_classes[CLASS_arm_fpa];
804 return &arm_reg_classes[CLASS_arm_gp];
808 * Produces the type which sits between the stack args and the locals on the stack.
809 * it will contain the return address and space to store the old base pointer.
810 * @return The Firm type modelling the ABI between type.
812 static ir_type *arm_get_between_type(void *self) {
813 static ir_type *between_type = NULL;
814 static entity *old_bp_ent = NULL;
817 entity *ret_addr_ent;
818 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
819 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
821 between_type = new_type_class(new_id_from_str("arm_between_type"));
822 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
823 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
825 set_entity_offset_bytes(old_bp_ent, 0);
826 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
827 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
835 be_abi_call_flags_bits_t flags;
836 const arch_env_t *arch_env;
837 const arch_isa_t *isa;
841 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
843 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
844 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
845 env->flags = fl.bits;
847 env->arch_env = arch_env;
848 env->isa = arch_env->isa;
852 static void arm_abi_dont_save_regs(void *self, pset *s)
854 arm_abi_env_t *env = self;
855 if (env->flags.try_omit_fp)
856 pset_insert_ptr(s, env->isa->bp);
862 * Build the ARM prolog
864 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
865 ir_node *keep, *store;
866 arm_abi_env_t *env = self;
867 ir_graph *irg = env->irg;
868 ir_node *block = get_irg_start_block(irg);
869 // ir_node *regs[16];
871 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
872 static const arm_register_req_t *fp_req[] = {
873 &arm_default_req_arm_gp_r11
876 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
877 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
878 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
879 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
880 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
881 // ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]);
882 // ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]);
883 // ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]);
884 // ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]);
886 if(env->flags.try_omit_fp)
889 ip = be_new_Copy(gp, irg, block, sp );
890 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
891 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
893 // if (r0) regs[n_regs++] = r0;
894 // if (r1) regs[n_regs++] = r1;
895 // if (r2) regs[n_regs++] = r2;
896 // if (r3) regs[n_regs++] = r3;
897 // sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
898 // set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
899 // arch_set_irn_register(env->arch_env, sp, env->isa->sp);
900 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
901 set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
902 // arch_set_irn_register(env->arch_env, store, env->isa->sp);
904 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
905 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
906 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
908 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
909 be_node_set_reg_class(keep, 1, gp);
910 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
911 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
913 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
914 new_tarval_from_long(4, get_irn_mode(fp)));
915 set_arm_req_out_all(fp, fp_req);
916 //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
917 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
919 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
920 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
921 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2);
922 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3);
923 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
924 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
925 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
926 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
927 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
932 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
933 arm_abi_env_t *env = self;
934 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
935 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
936 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
937 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
938 static const arm_register_req_t *sub12_req[] = {
939 &arm_default_req_arm_gp_sp
942 // TODO: Activate Omit fp in epilogue
943 if(env->flags.try_omit_fp) {
944 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
945 add_irn_dep(curr_sp, *mem);
947 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
948 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
949 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
950 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
952 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
953 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
954 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
958 tarval *tv = new_tarval_from_long(12,mode_Iu);
959 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
960 set_arm_req_out_all(sub12_node, sub12_req);
961 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
962 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
963 set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
964 set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
965 set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
966 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
967 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
968 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
969 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
970 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
971 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
972 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
974 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
975 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
976 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
977 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
980 static const be_abi_callbacks_t arm_abi_callbacks = {
983 arm_get_between_type,
984 arm_abi_dont_save_regs,
991 * Get the ABI restrictions for procedure calls.
992 * @param self The this pointer.
993 * @param method_type The type of the method (procedure) in question.
994 * @param abi The abi object to be modified
996 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1000 int n = get_method_n_params(method_type);
1001 be_abi_call_flags_t flags = {
1003 0, /* store from left to right */
1004 0, /* store arguments sequential */
1005 1, /* try to omit the frame pointer */
1006 1, /* the function can use any register as frame pointer */
1007 1 /* a call can take the callee's address as an immediate */
1011 /* set stack parameter passing style */
1012 be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
1014 for (i = 0; i < n; i++) {
1015 /* reg = get reg for param i; */
1016 /* be_abi_call_param_reg(abi, i, reg); */
1019 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1021 be_abi_call_param_stack(abi, i, 4, 0, 0);
1024 /* default: return value is in R0 resp. F0 */
1025 assert(get_method_n_ress(method_type) < 2);
1026 if (get_method_n_ress(method_type) > 0) {
1027 tp = get_method_res_type(method_type, 0);
1028 mode = get_type_mode(tp);
1030 be_abi_call_res_reg(abi, 0,
1031 mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]);
1035 static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1036 return &arm_irn_ops;
1039 const arch_irn_handler_t arm_irn_handler = {
1043 const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
1044 return &arm_irn_handler;
1047 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1048 return is_arm_irn(irn);
1052 * Initializes the code generator interface.
1054 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1055 return &arm_code_gen_if;
1058 list_sched_selector_t arm_sched_selector;
1061 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1063 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1064 memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1065 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1066 return &arm_sched_selector;
1070 * Returns the necessary byte alignment for storing a register of given class.
1072 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1073 ir_mode *mode = arch_register_class_mode(cls);
1074 return get_mode_size_bytes(mode);
1078 * Returns the libFirm configuration parameter for this backend.
1080 static const backend_params *arm_get_libfirm_params(void) {
1081 static arch_dep_params_t ad = {
1083 0, /* Muls are fast enough on ARM */
1084 31, /* shift would be ok */
1085 0, /* SMUL is needed, only in Arch M*/
1086 0, /* UMUL is needed, only in Arch M */
1087 32, /* SMUL & UMUL available for 32 bit */
1089 static backend_params p = {
1090 NULL, /* no additional opcodes */
1091 NULL, /* will be set later */
1092 1, /* need dword lowering */
1093 NULL, /* but yet no creator function */
1094 NULL, /* context for create_intrinsic_fkt */
1103 /* fpu set architectures. */
1104 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1105 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1106 { "fpe", ARM_FPU_ARCH_FPE },
1107 { "fpa", ARM_FPU_ARCH_FPA },
1108 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1109 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1110 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1114 static lc_opt_enum_int_var_t arch_fpu_var = {
1115 &arm_isa_template.fpu_arch, arm_fpu_items
1118 static const lc_opt_table_entry_t arm_options[] = {
1119 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1120 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1125 * Register command line options for the ARM backend.
1129 * arm-fpuunit=unit select the floating point unit
1130 * arm-gen_reg_names use generic register names instead of SP, LR, PC
1132 static void arm_register_options(lc_opt_entry_t *ent)
1134 lc_opt_entry_t *be_grp_arm = lc_opt_get_grp(ent, "arm");
1135 lc_opt_add_table(be_grp_arm, arm_options);
1137 #endif /* WITH_LIBCORE */
1139 const arch_isa_if_t arm_isa_if = {
1142 arm_get_n_reg_class,
1144 arm_get_reg_class_for_mode,
1146 arm_get_irn_handler,
1147 arm_get_code_generator_if,
1148 arm_get_list_sched_selector,
1149 arm_get_reg_class_alignment,
1150 arm_get_libfirm_params,
1152 arm_register_options