2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist
29 #include "lc_opts_enum.h"
37 #include "iroptimize.h"
39 #include "lower_calls.h"
52 #include "bemachine.h"
55 #include "bespillslots.h"
56 #include "bespillutil.h"
58 #include "belistsched.h"
62 #include "bearch_arm_t.h"
64 #include "arm_new_nodes.h"
65 #include "gen_arm_regalloc_if.h"
66 #include "arm_transform.h"
67 #include "arm_optimize.h"
68 #include "arm_emitter.h"
69 #include "arm_map_regs.h"
71 static arch_irn_class_t arm_classify(const ir_node *irn)
74 /* TODO: we should mark reload/spill instructions and classify them here */
75 return arch_irn_class_none;
78 static ir_entity *arm_get_frame_entity(const ir_node *irn)
80 const arm_attr_t *attr = get_arm_attr_const(irn);
82 if (is_arm_FrameAddr(irn)) {
83 const arm_SymConst_attr_t *frame_attr = get_arm_SymConst_attr_const(irn);
84 return frame_attr->entity;
86 if (attr->is_load_store) {
87 const arm_load_store_attr_t *load_store_attr
88 = get_arm_load_store_attr_const(irn);
89 if (load_store_attr->is_frame_entity) {
90 return load_store_attr->entity;
97 * This function is called by the generic backend to correct offsets for
98 * nodes accessing the stack.
100 static void arm_set_stack_bias(ir_node *irn, int bias)
102 if (is_arm_FrameAddr(irn)) {
103 arm_SymConst_attr_t *attr = get_arm_SymConst_attr(irn);
104 attr->fp_offset += bias;
106 arm_load_store_attr_t *attr = get_arm_load_store_attr(irn);
107 assert(attr->base.is_load_store);
108 attr->offset += bias;
112 static int arm_get_sp_bias(const ir_node *irn)
114 /* We don't have any nodes changing the stack pointer.
115 We probably want to support post-/pre increment/decrement later */
120 /* fill register allocator interface */
122 static const arch_irn_ops_t arm_irn_ops = {
124 arm_get_frame_entity,
127 NULL, /* get_inverse */
128 NULL, /* get_op_estimated_cost */
129 NULL, /* possible_memory_operand */
130 NULL, /* perform_memory_operand */
134 * Transforms the standard Firm graph into
137 static void arm_prepare_graph(ir_graph *irg)
139 /* transform nodes into assembler instructions */
140 arm_transform_graph(irg);
142 /* do local optimizations (mainly CSE) */
143 local_optimize_graph(irg);
145 /* do code placement, to optimize the position of constants */
149 static void arm_collect_frame_entity_nodes(ir_node *node, void *data)
151 be_fec_env_t *env = (be_fec_env_t*)data;
155 const arm_load_store_attr_t *attr;
157 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
158 mode = get_irn_mode(node);
159 align = get_mode_size_bytes(mode);
160 be_node_needs_frame_entity(env, node, mode, align);
164 switch (get_arm_irn_opcode(node)) {
172 attr = get_arm_load_store_attr_const(node);
173 entity = attr->entity;
174 mode = attr->load_store_mode;
175 align = get_mode_size_bytes(mode);
178 if (!attr->is_frame_entity)
180 be_node_needs_frame_entity(env, node, mode, align);
183 static void arm_set_frame_entity(ir_node *node, ir_entity *entity)
185 if (is_be_node(node)) {
186 be_node_set_frame_entity(node, entity);
188 arm_load_store_attr_t *attr = get_arm_load_store_attr(node);
189 attr->entity = entity;
193 static void transform_Reload(ir_node *node)
195 ir_node *block = get_nodes_block(node);
196 dbg_info *dbgi = get_irn_dbg_info(node);
197 ir_node *ptr = get_irn_n(node, n_be_Reload_frame);
198 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
199 ir_mode *mode = get_irn_mode(node);
200 ir_entity *entity = be_get_frame_entity(node);
201 const arch_register_t *reg;
205 ir_node *sched_point = sched_prev(node);
207 load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true);
208 sched_add_after(sched_point, load);
211 proj = new_rd_Proj(dbgi, load, mode, pn_arm_Ldr_res);
213 reg = arch_get_irn_register(node);
214 arch_set_irn_register(proj, reg);
216 exchange(node, proj);
219 static void transform_Spill(ir_node *node)
221 ir_node *block = get_nodes_block(node);
222 dbg_info *dbgi = get_irn_dbg_info(node);
223 ir_node *ptr = get_irn_n(node, n_be_Spill_frame);
224 ir_graph *irg = get_irn_irg(node);
225 ir_node *mem = get_irg_no_mem(irg);
226 ir_node *val = get_irn_n(node, n_be_Spill_val);
227 ir_mode *mode = get_irn_mode(val);
228 ir_entity *entity = be_get_frame_entity(node);
229 ir_node *sched_point;
232 sched_point = sched_prev(node);
233 store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0,
237 sched_add_after(sched_point, store);
239 exchange(node, store);
242 static void arm_after_ra_walker(ir_node *block, void *data)
244 ir_node *node, *prev;
247 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
248 prev = sched_prev(node);
250 if (be_is_Reload(node)) {
251 transform_Reload(node);
252 } else if (be_is_Spill(node)) {
253 transform_Spill(node);
259 * Called immediately before emit phase.
261 static void arm_finish_irg(ir_graph *irg)
263 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
264 bool at_begin = stack_layout->sp_relative ? true : false;
265 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
267 irg_walk_graph(irg, NULL, arm_collect_frame_entity_nodes, fec_env);
268 be_assign_entities(fec_env, arm_set_frame_entity, at_begin);
269 be_free_frame_entity_coalescer(fec_env);
271 irg_block_walk_graph(irg, NULL, arm_after_ra_walker, NULL);
273 /* fix stack entity offsets */
274 be_abi_fix_stack_nodes(irg);
275 be_abi_fix_stack_bias(irg);
277 /* do peephole optimizations and fix stack offsets */
278 arm_peephole_optimization(irg);
281 static void arm_before_ra(ir_graph *irg)
283 be_sched_fix_flags(irg, &arm_reg_classes[CLASS_arm_flags], NULL, NULL);
287 * Initializes the code generator.
289 static void arm_init_graph(ir_graph *irg)
296 * Maps all intrinsic calls that the backend support
297 * and map all instructions the backend did not support
300 static void arm_handle_intrinsics(void)
302 ir_type *tp, *int_tp, *uint_tp;
306 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
308 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
310 int_tp = get_type_for_mode(mode_Is);
311 uint_tp = get_type_for_mode(mode_Iu);
313 /* ARM has neither a signed div instruction ... */
315 i_instr_record *map_Div = &records[n_records++].i_instr;
317 tp = new_type_method(2, 1);
318 set_method_param_type(tp, 0, int_tp);
319 set_method_param_type(tp, 1, int_tp);
320 set_method_res_type(tp, 0, int_tp);
322 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
323 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
324 rt_iDiv.mode = mode_T;
325 rt_iDiv.res_mode = mode_Is;
326 rt_iDiv.mem_proj_nr = pn_Div_M;
327 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
328 rt_iDiv.exc_proj_nr = pn_Div_X_except;
329 rt_iDiv.res_proj_nr = pn_Div_res;
331 add_entity_linkage(rt_iDiv.ent, IR_LINKAGE_CONSTANT);
332 set_entity_visibility(rt_iDiv.ent, ir_visibility_external);
334 map_Div->kind = INTRINSIC_INSTR;
335 map_Div->op = op_Div;
336 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
337 map_Div->ctx = &rt_iDiv;
339 /* ... nor an unsigned div instruction ... */
341 i_instr_record *map_Div = &records[n_records++].i_instr;
343 tp = new_type_method(2, 1);
344 set_method_param_type(tp, 0, uint_tp);
345 set_method_param_type(tp, 1, uint_tp);
346 set_method_res_type(tp, 0, uint_tp);
348 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
349 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
350 rt_uDiv.mode = mode_T;
351 rt_uDiv.res_mode = mode_Iu;
352 rt_uDiv.mem_proj_nr = pn_Div_M;
353 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
354 rt_uDiv.exc_proj_nr = pn_Div_X_except;
355 rt_uDiv.res_proj_nr = pn_Div_res;
357 set_entity_visibility(rt_uDiv.ent, ir_visibility_external);
359 map_Div->kind = INTRINSIC_INSTR;
360 map_Div->op = op_Div;
361 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
362 map_Div->ctx = &rt_uDiv;
364 /* ... nor a signed mod instruction ... */
366 i_instr_record *map_Mod = &records[n_records++].i_instr;
368 tp = new_type_method(2, 1);
369 set_method_param_type(tp, 0, int_tp);
370 set_method_param_type(tp, 1, int_tp);
371 set_method_res_type(tp, 0, int_tp);
373 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
374 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
375 rt_iMod.mode = mode_T;
376 rt_iMod.res_mode = mode_Is;
377 rt_iMod.mem_proj_nr = pn_Mod_M;
378 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
379 rt_iMod.exc_proj_nr = pn_Mod_X_except;
380 rt_iMod.res_proj_nr = pn_Mod_res;
382 set_entity_visibility(rt_iMod.ent, ir_visibility_external);
384 map_Mod->kind = INTRINSIC_INSTR;
385 map_Mod->op = op_Mod;
386 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
387 map_Mod->ctx = &rt_iMod;
389 /* ... nor an unsigned mod. */
391 i_instr_record *map_Mod = &records[n_records++].i_instr;
393 tp = new_type_method(2, 1);
394 set_method_param_type(tp, 0, uint_tp);
395 set_method_param_type(tp, 1, uint_tp);
396 set_method_res_type(tp, 0, uint_tp);
398 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
399 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
400 rt_uMod.mode = mode_T;
401 rt_uMod.res_mode = mode_Iu;
402 rt_uMod.mem_proj_nr = pn_Mod_M;
403 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
404 rt_uMod.exc_proj_nr = pn_Mod_X_except;
405 rt_uMod.res_proj_nr = pn_Mod_res;
407 set_entity_visibility(rt_uMod.ent, ir_visibility_external);
409 map_Mod->kind = INTRINSIC_INSTR;
410 map_Mod->op = op_Mod;
411 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
412 map_Mod->ctx = &rt_uMod;
416 lower_intrinsics(records, n_records, /*part_block_used=*/0);
419 extern const arch_isa_if_t arm_isa_if;
420 static arm_isa_t arm_isa_template = {
422 &arm_isa_if, /* isa interface */
427 &arm_registers[REG_SP], /* stack pointer */
428 &arm_registers[REG_R11], /* base pointer */
429 &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */
430 2, /* power of two stack alignment for calls, 2^2 == 4 */
431 NULL, /* main environment */
433 5, /* reload costs */
434 true, /* we do have custom abi handling */
436 ARM_FPU_ARCH_FPE, /* FPU architecture */
440 * Initializes the backend ISA and opens the output file.
442 static arch_env_t *arm_init(FILE *file_handle)
444 arm_isa_t *isa = XMALLOC(arm_isa_t);
445 *isa = arm_isa_template;
449 be_emit_init(file_handle);
451 arm_create_opcodes(&arm_irn_ops);
452 arm_handle_intrinsics();
454 be_gas_emit_types = false;
462 * Closes the output file and frees the ISA structure.
464 static void arm_done(void *self)
466 arm_isa_t *isa = (arm_isa_t*)self;
468 be_gas_emit_decls(isa->base.main_env);
475 * Get the register class which shall be used to store a value of a given mode.
476 * @param self The this pointer.
477 * @param mode The mode in question.
478 * @return A register class which can hold values of the given mode.
480 static const arch_register_class_t *arm_get_reg_class_for_mode(const ir_mode *mode)
482 if (mode_is_float(mode))
483 return &arm_reg_classes[CLASS_arm_fpa];
485 return &arm_reg_classes[CLASS_arm_gp];
489 * Returns the necessary byte alignment for storing a register of given class.
491 static int arm_get_reg_class_alignment(const arch_register_class_t *cls)
494 /* ARM is a 32 bit CPU, no need for other alignment */
499 * Return irp irgs in the desired order.
501 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list)
509 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
510 * @return 1 if allowed, 0 otherwise
512 static int arm_is_mux_allowed(ir_node *sel, ir_node *mux_false,
521 static asm_constraint_flags_t arm_parse_asm_constraint(const char **c)
523 /* asm not supported */
525 return ASM_CONSTRAINT_FLAG_INVALID;
528 static int arm_is_valid_clobber(const char *clobber)
534 static void arm_lower_for_target(void)
536 size_t i, n_irgs = get_irp_n_irgs();
538 /* lower compound param handling */
539 lower_calls_with_compounds(LF_RETURN_HIDDEN);
541 for (i = 0; i < n_irgs; ++i) {
542 ir_graph *irg = get_irp_irg(i);
543 lower_switch(irg, 4, 256, true);
546 for (i = 0; i < n_irgs; ++i) {
547 ir_graph *irg = get_irp_irg(i);
548 /* Turn all small CopyBs into loads/stores and all bigger CopyBs into
550 * TODO: These constants need arm-specific tuning. */
551 lower_CopyB(irg, 31, 32, false);
556 * Returns the libFirm configuration parameter for this backend.
558 static const backend_params *arm_get_libfirm_params(void)
560 static ir_settings_arch_dep_t ad = {
562 1, /* Muls are fast enough on ARM but ... */
563 31, /* ... one shift would be possible better */
564 NULL, /* no evaluator function */
565 0, /* SMUL is needed, only in Arch M */
566 0, /* UMUL is needed, only in Arch M */
567 32, /* SMUL & UMUL available for 32 bit */
569 static backend_params p = {
570 0, /* don't support inline assembler yet */
571 1, /* support Rotl nodes */
573 1, /* modulo shift efficient */
574 0, /* non-modulo shift not efficient */
575 &ad, /* will be set later */
576 arm_is_mux_allowed, /* allow_ifconv function */
577 32, /* machine size */
578 NULL, /* float arithmetic mode (TODO) */
579 NULL, /* long long type */
580 NULL, /* unsigned long long type */
581 NULL, /* long double type */
582 0, /* no trampoline support: size 0 */
583 0, /* no trampoline support: align 0 */
584 NULL, /* no trampoline support: no trampoline builder */
585 4 /* alignment of stack parameter */
591 /* fpu set architectures. */
592 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
593 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
594 { "fpe", ARM_FPU_ARCH_FPE },
595 { "fpa", ARM_FPU_ARCH_FPA },
596 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
597 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
598 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
602 static lc_opt_enum_int_var_t arch_fpu_var = {
603 &arm_isa_template.fpu_arch, arm_fpu_items
606 static const lc_opt_table_entry_t arm_options[] = {
607 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
611 const arch_isa_if_t arm_isa_if = {
613 arm_lower_for_target,
615 NULL, /* handle_intrinsics */
616 arm_get_reg_class_for_mode,
618 arm_get_reg_class_alignment,
619 arm_get_libfirm_params,
621 NULL, /* mark remat */
622 arm_parse_asm_constraint,
623 arm_is_valid_clobber,
626 NULL, /* get_pic_base */
627 NULL, /* before_abi */
632 NULL, /* register_saved_by */
637 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm)
638 void be_init_arch_arm(void)
640 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
641 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
643 lc_opt_add_table(arm_grp, arm_options);
645 be_register_isa_if("arm", &arm_isa_if);
647 arm_init_transform();