2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Oliver Richter, Tobias Gneist
30 #include <libcore/lc_opts.h>
31 #include <libcore/lc_opts_enum.h>
33 #include "pseudo_irg.h"
45 #include "../bearch_t.h" /* the general register allocator interface */
46 #include "../benode_t.h"
47 #include "../belower.h"
48 #include "../besched_t.h"
51 #include "../bemachine.h"
52 #include "../beilpsched.h"
53 #include "../bemodule.h"
54 #include "../beirg_t.h"
55 #include "../bespillslots.h"
56 #include "../begnuas.h"
58 #include "bearch_arm_t.h"
60 #include "arm_new_nodes.h" /* arm nodes interface */
61 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
62 #include "arm_transform.h"
63 #include "arm_emitter.h"
64 #include "arm_map_regs.h"
66 #define DEBUG_MODULE "firm.be.arm.isa"
68 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
69 static set *cur_reg_set = NULL;
71 /**************************************************
74 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
75 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
76 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
77 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
80 **************************************************/
83 * Return register requirements for a arm node.
84 * If the node returns a tuple (mode_T) then the proj's
85 * will be asked for this information.
88 arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node,
90 long node_pos = pos == -1 ? 0 : pos;
91 ir_mode *mode = get_irn_mode(node);
92 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
94 if (is_Block(node) || mode == mode_X || mode == mode_M) {
95 return arch_no_register_req;
98 if (mode == mode_T && pos < 0) {
99 return arch_no_register_req;
103 /* in case of a proj, we need to get the correct OUT slot */
104 /* of the node corresponding to the proj number */
106 return arch_no_register_req;
109 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
110 node = skip_Proj_const(node);
113 /* get requirements for our own nodes */
114 if (is_arm_irn(node)) {
115 const arch_register_req_t *req;
117 req = get_arm_in_req(node, pos);
119 req = get_arm_out_req(node, node_pos);
125 /* unknown should be transformed by now */
126 assert(!is_Unknown(node));
127 return arch_no_register_req;
130 static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
133 if (get_irn_mode(irn) == mode_X) {
138 pos = get_Proj_proj(irn);
139 irn = skip_Proj(irn);
142 if (is_arm_irn(irn)) {
143 const arch_register_t **slots;
145 slots = get_arm_slots(irn);
149 /* here we set the registers for the Phi nodes */
150 arm_set_firm_reg(irn, reg, cur_reg_set);
154 static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) {
156 const arch_register_t *reg = NULL;
160 if (get_irn_mode(irn) == mode_X) {
164 pos = get_Proj_proj(irn);
165 irn = skip_Proj_const(irn);
168 if (is_arm_irn(irn)) {
169 const arch_register_t **slots;
170 slots = get_arm_slots(irn);
174 reg = arm_get_firm_reg(irn, cur_reg_set);
180 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
181 irn = skip_Proj_const(irn);
184 return arch_irn_class_branch;
186 else if (is_arm_irn(irn)) {
187 return arch_irn_class_normal;
193 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
194 irn = skip_Proj_const(irn);
196 if (is_arm_irn(irn)) {
197 return get_arm_flags(irn);
199 else if (is_Unknown(irn)) {
200 return arch_irn_flags_ignore;
206 static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
207 /* TODO: return the entity assigned to the frame */
211 static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
212 /* TODO: set the entity assigned to the frame */
216 * This function is called by the generic backend to correct offsets for
217 * nodes accessing the stack.
219 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
220 /* TODO: correct offset if irn accesses the stack */
223 static int arm_get_sp_bias(const void *self, const ir_node *irn) {
227 /* fill register allocator interface */
229 static const arch_irn_ops_if_t arm_irn_ops_if = {
235 arm_get_frame_entity,
236 arm_set_frame_entity,
239 NULL, /* get_inverse */
240 NULL, /* get_op_estimated_cost */
241 NULL, /* possible_memory_operand */
242 NULL, /* perform_memory_operand */
245 arm_irn_ops_t arm_irn_ops = {
252 /**************************************************
255 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
256 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
257 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
258 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
261 **************************************************/
264 * Transforms the standard Firm graph into
267 static void arm_prepare_graph(void *self) {
268 arm_code_gen_t *cg = self;
270 /* transform nodes into assembler instructions */
271 arm_transform_graph(cg);
273 /* do local optimizations (mainly CSE) */
274 local_optimize_graph(cg->irg);
277 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
279 /* do code placement, to optimize the position of constants */
283 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
287 * Called immediately before emit phase.
289 static void arm_finish_irg(void *self) {
290 /* TODO: - fix offsets for nodes accessing stack
297 * These are some hooks which must be filled but are probably not needed.
299 static void arm_before_sched(void *self) {
300 /* Some stuff you need to do after scheduling but before register allocation */
303 static void arm_before_ra(void *self) {
304 /* Some stuff you need to do immediately after register allocation */
308 * We transform Spill and Reload here. This needs to be done before
309 * stack biasing otherwise we would miss the corrected offset for these nodes.
311 static void arm_after_ra(void *self) {
312 arm_code_gen_t *cg = self;
313 be_coalesce_spillslots(cg->birg);
317 * Emits the code, closes the output file and frees
318 * the code generator interface.
320 static void arm_emit_and_done(void *self) {
321 arm_code_gen_t *cg = self;
322 ir_graph *irg = cg->irg;
324 arm_gen_routine(cg, irg);
328 /* de-allocate code generator */
329 del_set(cg->reg_set);
334 * Move a double floating point value into an integer register.
335 * Place the move operation into block bl.
337 * Handle some special cases here:
338 * 1.) A constant: simply split into two
339 * 2.) A load: simply split into two
341 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
342 ir_node **resH, ir_node **resL) {
344 tarval *tv = get_Const_tarval(arg);
347 /* get the upper 32 bits */
348 v = get_tarval_sub_bits(tv, 7);
349 v = (v << 8) | get_tarval_sub_bits(tv, 6);
350 v = (v << 8) | get_tarval_sub_bits(tv, 5);
351 v = (v << 8) | get_tarval_sub_bits(tv, 4);
352 *resH = new_Const_long(mode_Is, v);
354 /* get the lower 32 bits */
355 v = get_tarval_sub_bits(tv, 3);
356 v = (v << 8) | get_tarval_sub_bits(tv, 2);
357 v = (v << 8) | get_tarval_sub_bits(tv, 1);
358 v = (v << 8) | get_tarval_sub_bits(tv, 0);
359 *resL = new_Const_long(mode_Is, v);
361 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
362 /* FIXME: handling of low/high depends on LE/BE here */
366 ir_graph *irg = current_ir_graph;
369 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
371 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
372 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
373 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
379 * Move a single floating point value into an integer register.
380 * Place the move operation into block bl.
382 * Handle some special cases here:
383 * 1.) A constant: simply move
384 * 2.) A load: simply load
386 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) {
388 tarval *tv = get_Const_tarval(arg);
391 /* get the lower 32 bits */
392 v = get_tarval_sub_bits(tv, 3);
393 v = (v << 8) | get_tarval_sub_bits(tv, 2);
394 v = (v << 8) | get_tarval_sub_bits(tv, 1);
395 v = (v << 8) | get_tarval_sub_bits(tv, 0);
396 return new_Const_long(mode_Is, v);
398 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
401 load = skip_Proj(arg);
408 * Convert the arguments of a call to support the
409 * ARM calling convention of general purpose AND floating
412 static void handle_calls(ir_node *call, void *env)
414 arm_code_gen_t *cg = env;
415 int i, j, n, size, idx, flag, n_param, n_res;
416 ir_type *mtp, *new_mtd, *new_tp[5];
417 ir_node *new_in[5], **in;
423 /* check, if we need conversions */
424 n = get_Call_n_params(call);
425 mtp = get_Call_type(call);
426 assert(get_method_n_params(mtp) == n);
428 /* it's always enough to handle the first 4 parameters */
431 flag = size = idx = 0;
432 bl = get_nodes_block(call);
433 for (i = 0; i < n; ++i) {
434 ir_type *param_tp = get_method_param_type(mtp, i);
436 if (is_compound_type(param_tp)) {
437 /* an aggregate parameter: bad case */
441 /* a primitive parameter */
442 ir_mode *mode = get_type_mode(param_tp);
444 if (mode_is_float(mode)) {
445 if (get_mode_size_bits(mode) > 32) {
446 ir_node *mem = get_Call_mem(call);
448 /* Beware: ARM wants the high part first */
450 new_tp[idx] = cg->int_tp;
451 new_tp[idx+1] = cg->int_tp;
452 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
454 set_Call_mem(call, mem);
458 new_tp[idx] = cg->int_tp;
459 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
466 new_tp[idx] = param_tp;
467 new_in[idx] = get_Call_param(call, i);
476 /* if flag is NOT set, no need to translate the method type */
480 /* construct a new method type */
482 n_param = get_method_n_params(mtp) - n + idx;
483 n_res = get_method_n_ress(mtp);
484 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
486 for (i = 0; i < idx; ++i)
487 set_method_param_type(new_mtd, i, new_tp[i]);
488 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
489 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
490 for (i = 0; i < n_res; ++i)
491 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
493 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
494 set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp));
496 if (is_lowered_type(mtp)) {
497 mtp = get_associated_type(mtp);
499 set_lowered_type(mtp, new_mtd);
501 set_Call_type(call, new_mtd);
503 /* calculate new in array of the Call */
504 NEW_ARR_A(ir_node *, in, n_param + 2);
505 for (i = 0; i < idx; ++i)
506 in[2 + i] = new_in[i];
507 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
508 in[2 + j++] = get_Call_param(call, i);
510 in[0] = get_Call_mem(call);
511 in[1] = get_Call_ptr(call);
513 /* finally, change the call inputs */
514 set_irn_in(call, n_param + 2, in);
518 * Handle graph transformations before the abi converter does its work.
520 static void arm_before_abi(void *self) {
521 arm_code_gen_t *cg = self;
523 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
527 static void *arm_cg_init(be_irg_t *birg);
529 static const arch_code_generator_if_t arm_code_gen_if = {
531 arm_before_abi, /* before abi introduce */
534 arm_before_sched, /* before scheduling hook */
535 arm_before_ra, /* before register allocation hook */
542 * Initializes the code generator.
544 static void *arm_cg_init(be_irg_t *birg) {
545 static ir_type *int_tp = NULL;
546 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
550 /* create an integer type with machine size */
551 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
554 cg = xmalloc(sizeof(*cg));
555 cg->impl = &arm_code_gen_if;
557 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
558 cg->arch_env = birg->main_env->arch_env;
562 cg->have_fp_insn = 0;
563 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
565 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
567 cur_reg_set = cg->reg_set;
571 /* enter the current code generator */
574 return (arch_code_generator_t *)cg;
579 * Maps all intrinsic calls that the backend support
580 * and map all instructions the backend did not support
583 static void arm_handle_intrinsics(void) {
584 ir_type *tp, *int_tp, *uint_tp;
588 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
590 int_tp = new_type_primitive(ID("int"), mode_Is);
591 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
593 /* ARM has neither a signed div instruction ... */
596 i_instr_record *map_Div = &records[n_records++].i_instr;
598 tp = new_type_method(ID("rt_iDiv"), 2, 1);
599 set_method_param_type(tp, 0, int_tp);
600 set_method_param_type(tp, 1, int_tp);
601 set_method_res_type(tp, 0, int_tp);
603 rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
604 rt_Div.mode = mode_T;
605 rt_Div.res_mode = mode_Is;
606 rt_Div.mem_proj_nr = pn_Div_M;
607 rt_Div.regular_proj_nr = pn_Div_X_regular;
608 rt_Div.exc_proj_nr = pn_Div_X_except;
609 rt_Div.exc_mem_proj_nr = pn_Div_M;
610 rt_Div.res_proj_nr = pn_Div_res;
612 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
614 map_Div->kind = INTRINSIC_INSTR;
615 map_Div->op = op_Div;
616 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
617 map_Div->ctx = &rt_Div;
619 /* ... nor an unsigned div instruction ... */
622 i_instr_record *map_Div = &records[n_records++].i_instr;
624 tp = new_type_method(ID("rt_uDiv"), 2, 1);
625 set_method_param_type(tp, 0, uint_tp);
626 set_method_param_type(tp, 1, uint_tp);
627 set_method_res_type(tp, 0, uint_tp);
629 rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
630 rt_Div.mode = mode_T;
631 rt_Div.res_mode = mode_Iu;
632 rt_Div.mem_proj_nr = pn_Div_M;
633 rt_Div.regular_proj_nr = pn_Div_X_regular;
634 rt_Div.exc_proj_nr = pn_Div_X_except;
635 rt_Div.exc_mem_proj_nr = pn_Div_M;
636 rt_Div.res_proj_nr = pn_Div_res;
638 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
640 map_Div->kind = INTRINSIC_INSTR;
641 map_Div->op = op_Div;
642 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
643 map_Div->ctx = &rt_Div;
645 /* ... nor a signed mod instruction ... */
648 i_instr_record *map_Mod = &records[n_records++].i_instr;
650 tp = new_type_method(ID("rt_iMod"), 2, 1);
651 set_method_param_type(tp, 0, int_tp);
652 set_method_param_type(tp, 1, int_tp);
653 set_method_res_type(tp, 0, int_tp);
655 rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
656 rt_Mod.mode = mode_T;
657 rt_Mod.res_mode = mode_Is;
658 rt_Mod.mem_proj_nr = pn_Mod_M;
659 rt_Mod.regular_proj_nr = pn_Mod_X_regular;
660 rt_Mod.exc_proj_nr = pn_Mod_X_except;
661 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
662 rt_Mod.res_proj_nr = pn_Mod_res;
664 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
666 map_Mod->kind = INTRINSIC_INSTR;
667 map_Mod->op = op_Mod;
668 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
669 map_Mod->ctx = &rt_Mod;
671 /* ... nor an unsigned mod. */
674 i_instr_record *map_Mod = &records[n_records++].i_instr;
676 tp = new_type_method(ID("rt_uMod"), 2, 1);
677 set_method_param_type(tp, 0, uint_tp);
678 set_method_param_type(tp, 1, uint_tp);
679 set_method_res_type(tp, 0, uint_tp);
681 rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
682 rt_Mod.mode = mode_T;
683 rt_Mod.res_mode = mode_Iu;
684 rt_Mod.mem_proj_nr = pn_Mod_M;
685 rt_Mod.regular_proj_nr = pn_Mod_X_regular;
686 rt_Mod.exc_proj_nr = pn_Mod_X_except;
687 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
688 rt_Mod.res_proj_nr = pn_Mod_res;
690 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
692 map_Mod->kind = INTRINSIC_INSTR;
693 map_Mod->op = op_Mod;
694 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
695 map_Mod->ctx = &rt_Mod;
699 lower_intrinsics(records, n_records);
702 /*****************************************************************
703 * ____ _ _ _____ _____
704 * | _ \ | | | | |_ _|/ ____| /\
705 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
706 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
707 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
708 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
710 *****************************************************************/
712 static arm_isa_t arm_isa_template = {
714 &arm_isa_if, /* isa interface */
715 &arm_gp_regs[REG_SP], /* stack pointer */
716 &arm_gp_regs[REG_R11], /* base pointer */
717 -1, /* stack direction */
718 NULL, /* main environment */
720 5, /* reload costs */
722 0, /* use generic register names instead of SP, LR, PC */
723 ARM_FPU_ARCH_FPE, /* FPU architecture */
724 NULL, /* current code generator */
725 { NULL, }, /* emitter environment */
729 * Initializes the backend ISA and opens the output file.
731 static void *arm_init(FILE *file_handle) {
732 static int inited = 0;
738 isa = xmalloc(sizeof(*isa));
739 memcpy(isa, &arm_isa_template, sizeof(*isa));
741 arm_register_init(isa);
744 be_emit_init_env(&isa->emit, file_handle);
746 arm_create_opcodes();
747 arm_register_copy_attr_func();
748 arm_handle_intrinsics();
750 /* we mark referenced global entities, so we can only emit those which
751 * are actually referenced. (Note: you mustn't use the type visited flag
752 * elsewhere in the backend)
754 inc_master_type_visited();
763 * Closes the output file and frees the ISA structure.
765 static void arm_done(void *self) {
766 arm_isa_t *isa = self;
768 be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
770 be_emit_destroy_env(&isa->emit);
776 * Report the number of register classes.
777 * If we don't have fp instructions, report only GP
778 * here to speed up register allocation (and makes dumps
779 * smaller and more readable).
781 static int arm_get_n_reg_class(const void *self) {
782 const arm_isa_t *isa = self;
784 /* ARGH! is called BEFORE transform */
786 return isa->cg->have_fp_insn ? 2 : 1;
790 * Return the register class with requested index.
792 static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
793 return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa];
797 * Get the register class which shall be used to store a value of a given mode.
798 * @param self The this pointer.
799 * @param mode The mode in question.
800 * @return A register class which can hold values of the given mode.
802 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
803 if (mode_is_float(mode))
804 return &arm_reg_classes[CLASS_arm_fpa];
806 return &arm_reg_classes[CLASS_arm_gp];
810 * Produces the type which sits between the stack args and the locals on the stack.
811 * it will contain the return address and space to store the old base pointer.
812 * @return The Firm type modelling the ABI between type.
814 static ir_type *arm_get_between_type(void *self) {
815 static ir_type *between_type = NULL;
816 static ir_entity *old_bp_ent = NULL;
819 ir_entity *ret_addr_ent;
820 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
821 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
823 between_type = new_type_class(new_id_from_str("arm_between_type"));
824 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
825 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
827 set_entity_offset(old_bp_ent, 0);
828 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
829 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
837 be_abi_call_flags_bits_t flags;
838 const arch_env_t *arch_env;
839 const arch_isa_t *isa;
843 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
845 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
846 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
847 env->flags = fl.bits;
849 env->arch_env = arch_env;
850 env->isa = arch_env->isa;
854 static void arm_abi_dont_save_regs(void *self, pset *s)
856 arm_abi_env_t *env = self;
857 if (env->flags.try_omit_fp)
858 pset_insert_ptr(s, env->isa->bp);
864 * Build the ARM prolog
866 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
867 ir_node *keep, *store;
868 arm_abi_env_t *env = self;
869 ir_graph *irg = env->irg;
870 ir_node *block = get_irg_start_block(irg);
871 // ir_node *regs[16];
873 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
875 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
876 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
877 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
878 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
879 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
880 // ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]);
881 // ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]);
882 // ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]);
883 // ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]);
885 if(env->flags.try_omit_fp)
888 ip = be_new_Copy(gp, irg, block, sp );
889 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
890 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
892 // if (r0) regs[n_regs++] = r0;
893 // if (r1) regs[n_regs++] = r1;
894 // if (r2) regs[n_regs++] = r2;
895 // if (r3) regs[n_regs++] = r3;
896 // sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
897 // set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
898 // arch_set_irn_register(env->arch_env, sp, env->isa->sp);
899 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
901 // set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
902 // arch_set_irn_register(env->arch_env, store, env->isa->sp);
904 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
905 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
906 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
908 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
909 be_node_set_reg_class(keep, 1, gp);
910 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
911 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
913 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
914 new_tarval_from_long(4, get_irn_mode(fp)));
916 //set_arm_req_out_all(fp, fp_req);
917 //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
918 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
920 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
921 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
922 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2);
923 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3);
924 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
925 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
926 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
927 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
928 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
933 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
934 arm_abi_env_t *env = self;
935 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
936 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
937 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
938 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
940 // TODO: Activate Omit fp in epilogue
941 if(env->flags.try_omit_fp) {
942 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
943 add_irn_dep(curr_sp, *mem);
945 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
946 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
947 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
948 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
950 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
951 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
952 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
953 be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
957 tarval *tv = new_tarval_from_long(12,mode_Iu);
958 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
960 //set_arm_req_out_all(sub12_node, sub12_req);
961 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
962 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
964 //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
965 //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
966 //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
967 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
968 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
969 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
970 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
971 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
972 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
973 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
975 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
976 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
977 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
978 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
981 static const be_abi_callbacks_t arm_abi_callbacks = {
984 arm_get_between_type,
985 arm_abi_dont_save_regs,
992 * Get the ABI restrictions for procedure calls.
993 * @param self The this pointer.
994 * @param method_type The type of the method (procedure) in question.
995 * @param abi The abi object to be modified
997 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1001 int n = get_method_n_params(method_type);
1002 be_abi_call_flags_t flags = {
1004 0, /* store from left to right */
1005 0, /* store arguments sequential */
1006 1, /* try to omit the frame pointer */
1007 1, /* the function can use any register as frame pointer */
1008 1 /* a call can take the callee's address as an immediate */
1012 /* set stack parameter passing style */
1013 be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
1015 for (i = 0; i < n; i++) {
1016 /* reg = get reg for param i; */
1017 /* be_abi_call_param_reg(abi, i, reg); */
1020 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1022 be_abi_call_param_stack(abi, i, 4, 0, 0);
1025 /* default: return value is in R0 resp. F0 */
1026 assert(get_method_n_ress(method_type) < 2);
1027 if (get_method_n_ress(method_type) > 0) {
1028 tp = get_method_res_type(method_type, 0);
1029 mode = get_type_mode(tp);
1031 be_abi_call_res_reg(abi, 0,
1032 mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]);
1036 static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1037 return &arm_irn_ops;
1040 const arch_irn_handler_t arm_irn_handler = {
1044 const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
1045 return &arm_irn_handler;
1048 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1049 if(!is_arm_irn(irn))
1056 * Initializes the code generator interface.
1058 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1059 return &arm_code_gen_if;
1062 list_sched_selector_t arm_sched_selector;
1065 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1067 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1068 memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1069 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1070 return &arm_sched_selector;
1073 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
1078 * Returns the necessary byte alignment for storing a register of given class.
1080 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1081 /* ARM is a 32 bit CPU, no need for other alignment */
1085 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1091 static const be_machine_t *arm_get_machine(const void *self) {
1098 * Return irp irgs in the desired order.
1100 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
1105 * Returns the libFirm configuration parameter for this backend.
1107 static const backend_params *arm_get_libfirm_params(void) {
1108 static arch_dep_params_t ad = {
1110 1, /* Muls are fast enough on ARM but ... */
1111 1, /* ... one shift would be possible better */
1112 0, /* SMUL is needed, only in Arch M*/
1113 0, /* UMUL is needed, only in Arch M */
1114 32, /* SMUL & UMUL available for 32 bit */
1116 static backend_params p = {
1117 1, /* need dword lowering */
1118 0, /* don't support inline assembler yet */
1119 0, /* no different calling conventions */
1120 NULL, /* no additional opcodes */
1121 NULL, /* will be set later */
1122 NULL, /* but yet no creator function */
1123 NULL, /* context for create_intrinsic_fkt */
1124 NULL, /* no if conversion settings */
1131 /* fpu set architectures. */
1132 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1133 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1134 { "fpe", ARM_FPU_ARCH_FPE },
1135 { "fpa", ARM_FPU_ARCH_FPA },
1136 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1137 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1138 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1142 static lc_opt_enum_int_var_t arch_fpu_var = {
1143 &arm_isa_template.fpu_arch, arm_fpu_items
1146 static const lc_opt_table_entry_t arm_options[] = {
1147 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1148 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1152 const arch_isa_if_t arm_isa_if = {
1155 arm_get_n_reg_class,
1157 arm_get_reg_class_for_mode,
1159 arm_get_irn_handler,
1160 arm_get_code_generator_if,
1161 arm_get_list_sched_selector,
1162 arm_get_ilp_sched_selector,
1163 arm_get_reg_class_alignment,
1164 arm_get_libfirm_params,
1165 arm_get_allowed_execution_units,
1170 void be_init_arch_arm(void)
1172 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1173 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1175 lc_opt_add_table(arm_grp, arm_options);
1177 be_register_isa_if("arm", &arm_isa_if);
1179 arm_init_transform();
1182 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);