2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist
29 #include "lc_opts_enum.h"
31 #include "pseudo_irg.h"
38 #include "iroptimize.h"
47 #include "../bearch.h"
48 #include "../benode.h"
49 #include "../belower.h"
50 #include "../besched.h"
53 #include "../bemachine.h"
54 #include "../beilpsched.h"
55 #include "../bemodule.h"
57 #include "../bespillslots.h"
58 #include "../begnuas.h"
59 #include "../belistsched.h"
60 #include "../beflags.h"
62 #include "bearch_arm_t.h"
64 #include "arm_new_nodes.h"
65 #include "gen_arm_regalloc_if.h"
66 #include "arm_transform.h"
67 #include "arm_optimize.h"
68 #include "arm_emitter.h"
69 #include "arm_map_regs.h"
71 static arch_irn_class_t arm_classify(const ir_node *irn)
77 static ir_entity *arm_get_frame_entity(const ir_node *irn)
79 const arm_attr_t *attr = get_arm_attr_const(irn);
81 if (is_arm_FrameAddr(irn)) {
82 const arm_SymConst_attr_t *attr = get_irn_generic_attr_const(irn);
85 if (attr->is_load_store) {
86 const arm_load_store_attr_t *load_store_attr
87 = get_arm_load_store_attr_const(irn);
88 if (load_store_attr->is_frame_entity) {
89 return load_store_attr->entity;
95 static void arm_set_frame_entity(ir_node *irn, ir_entity *ent)
99 panic("arm_set_frame_entity() called. This should not happen.");
103 * This function is called by the generic backend to correct offsets for
104 * nodes accessing the stack.
106 static void arm_set_stack_bias(ir_node *irn, int bias)
108 if (is_arm_FrameAddr(irn)) {
109 arm_SymConst_attr_t *attr = get_irn_generic_attr(irn);
110 attr->fp_offset += bias;
112 arm_load_store_attr_t *attr = get_arm_load_store_attr(irn);
113 assert(attr->base.is_load_store);
114 attr->offset += bias;
118 static int arm_get_sp_bias(const ir_node *irn)
120 /* We don't have any nodes changing the stack pointer.
121 TODO: we probably want to support post-/pre increment/decrement later */
126 /* fill register allocator interface */
128 static const arch_irn_ops_t arm_irn_ops = {
131 arm_get_frame_entity,
132 arm_set_frame_entity,
135 NULL, /* get_inverse */
136 NULL, /* get_op_estimated_cost */
137 NULL, /* possible_memory_operand */
138 NULL, /* perform_memory_operand */
142 * Transforms the standard Firm graph into
145 static void arm_prepare_graph(void *self)
147 arm_code_gen_t *cg = self;
149 /* transform nodes into assembler instructions */
150 arm_transform_graph(cg);
152 /* do local optimizations (mainly CSE) */
153 local_optimize_graph(cg->irg);
156 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
158 /* do code placement, to optimize the position of constants */
162 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
166 * Called immediately before emit phase.
168 static void arm_finish_irg(void *self)
170 arm_code_gen_t *cg = self;
172 /* do peephole optimizations and fix stack offsets */
173 arm_peephole_optimization(cg);
176 static ir_node *arm_flags_remat(ir_node *node, ir_node *after)
181 if (is_Block(after)) {
184 block = get_nodes_block(after);
186 copy = exact_copy(node);
187 set_nodes_block(copy, block);
188 sched_add_after(after, copy);
192 static void arm_before_ra(void *self)
194 arm_code_gen_t *cg = self;
196 be_sched_fix_flags(cg->birg, &arm_reg_classes[CLASS_arm_flags],
200 static void transform_Reload(ir_node *node)
202 ir_graph *irg = get_irn_irg(node);
203 ir_node *block = get_nodes_block(node);
204 dbg_info *dbgi = get_irn_dbg_info(node);
205 ir_node *ptr = get_irg_frame(irg);
206 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
207 ir_mode *mode = get_irn_mode(node);
208 ir_entity *entity = be_get_frame_entity(node);
209 const arch_register_t *reg;
213 ir_node *sched_point = sched_prev(node);
215 load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true);
216 sched_add_after(sched_point, load);
219 proj = new_rd_Proj(dbgi, block, load, mode, pn_arm_Ldr_res);
221 reg = arch_get_irn_register(node);
222 arch_set_irn_register(proj, reg);
224 exchange(node, proj);
227 static void transform_Spill(ir_node *node)
229 ir_graph *irg = get_irn_irg(node);
230 ir_node *block = get_nodes_block(node);
231 dbg_info *dbgi = get_irn_dbg_info(node);
232 ir_node *ptr = get_irg_frame(irg);
233 ir_node *mem = new_NoMem();
234 ir_node *val = get_irn_n(node, be_pos_Spill_val);
235 ir_mode *mode = get_irn_mode(val);
236 ir_entity *entity = be_get_frame_entity(node);
237 ir_node *sched_point;
240 sched_point = sched_prev(node);
241 store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0,
245 sched_add_after(sched_point, store);
247 exchange(node, store);
250 static void arm_after_ra_walker(ir_node *block, void *data)
252 ir_node *node, *prev;
255 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
256 prev = sched_prev(node);
258 if (be_is_Reload(node)) {
259 transform_Reload(node);
260 } else if (be_is_Spill(node)) {
261 transform_Spill(node);
266 static void arm_after_ra(void *self)
268 arm_code_gen_t *cg = self;
269 be_coalesce_spillslots(cg->birg);
271 irg_block_walk_graph(cg->irg, NULL, arm_after_ra_walker, NULL);
275 * Emits the code, closes the output file and frees
276 * the code generator interface.
278 static void arm_emit_and_done(void *self)
280 arm_code_gen_t *cg = self;
281 ir_graph *irg = cg->irg;
283 arm_gen_routine(cg, irg);
285 /* de-allocate code generator */
286 del_set(cg->reg_set);
291 * Move a double floating point value into an integer register.
292 * Place the move operation into block bl.
294 * Handle some special cases here:
295 * 1.) A constant: simply split into two
296 * 2.) A load: simply split into two
298 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
299 ir_node **resH, ir_node **resL)
302 tarval *tv = get_Const_tarval(arg);
305 /* get the upper 32 bits */
306 v = get_tarval_sub_bits(tv, 7);
307 v = (v << 8) | get_tarval_sub_bits(tv, 6);
308 v = (v << 8) | get_tarval_sub_bits(tv, 5);
309 v = (v << 8) | get_tarval_sub_bits(tv, 4);
310 *resH = new_Const_long(mode_Is, v);
312 /* get the lower 32 bits */
313 v = get_tarval_sub_bits(tv, 3);
314 v = (v << 8) | get_tarval_sub_bits(tv, 2);
315 v = (v << 8) | get_tarval_sub_bits(tv, 1);
316 v = (v << 8) | get_tarval_sub_bits(tv, 0);
317 *resL = new_Const_long(mode_Is, v);
318 } else if (is_Load(skip_Proj(arg))) {
319 /* FIXME: handling of low/high depends on LE/BE here */
320 panic("Unimplemented convert_dbl_to_int() case");
325 conv = new_bd_arm_fpaDbl2GP(NULL, bl, arg, mem);
327 *resL = new_r_Proj(bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
328 *resH = new_r_Proj(bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
329 mem = new_r_Proj(bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
335 * Move a single floating point value into an integer register.
336 * Place the move operation into block bl.
338 * Handle some special cases here:
339 * 1.) A constant: simply move
340 * 2.) A load: simply load
342 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg)
347 tarval *tv = get_Const_tarval(arg);
350 /* get the lower 32 bits */
351 v = get_tarval_sub_bits(tv, 3);
352 v = (v << 8) | get_tarval_sub_bits(tv, 2);
353 v = (v << 8) | get_tarval_sub_bits(tv, 1);
354 v = (v << 8) | get_tarval_sub_bits(tv, 0);
355 return new_Const_long(mode_Is, v);
356 } else if (is_Load(skip_Proj(arg))) {
359 load = skip_Proj(arg);
361 panic("Unimplemented convert_sng_to_int() case");
365 * Convert the arguments of a call to support the
366 * ARM calling convention of general purpose AND floating
369 static void handle_calls(ir_node *call, void *env)
371 arm_code_gen_t *cg = env;
372 int i, j, n, size, idx, flag, n_param, n_res, first_variadic;
373 ir_type *mtp, *new_mtd, *new_tp[5];
374 ir_node *new_in[5], **in;
380 /* check, if we need conversions */
381 n = get_Call_n_params(call);
382 mtp = get_Call_type(call);
383 assert(get_method_n_params(mtp) == n);
385 /* it's always enough to handle the first 4 parameters */
388 flag = size = idx = 0;
389 bl = get_nodes_block(call);
390 for (i = 0; i < n; ++i) {
391 ir_type *param_tp = get_method_param_type(mtp, i);
393 if (is_compound_type(param_tp)) {
394 /* an aggregate parameter: bad case */
398 /* a primitive parameter */
399 ir_mode *mode = get_type_mode(param_tp);
401 if (mode_is_float(mode)) {
402 if (get_mode_size_bits(mode) > 32) {
403 ir_node *mem = get_Call_mem(call);
405 /* Beware: ARM wants the high part first */
407 new_tp[idx] = cg->int_tp;
408 new_tp[idx+1] = cg->int_tp;
409 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
411 set_Call_mem(call, mem);
415 new_tp[idx] = cg->int_tp;
416 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
423 new_tp[idx] = param_tp;
424 new_in[idx] = get_Call_param(call, i);
433 /* if flag is NOT set, no need to translate the method type */
437 /* construct a new method type */
439 n_param = get_method_n_params(mtp) - n + idx;
440 n_res = get_method_n_ress(mtp);
441 new_mtd = new_d_type_method(n_param, n_res, get_type_dbg_info(mtp));
443 for (i = 0; i < idx; ++i)
444 set_method_param_type(new_mtd, i, new_tp[i]);
445 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
446 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
447 for (i = 0; i < n_res; ++i)
448 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
450 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
451 first_variadic = get_method_first_variadic_param_index(mtp);
452 if (first_variadic >= 0)
453 set_method_first_variadic_param_index(new_mtd, first_variadic);
455 if (is_lowered_type(mtp)) {
456 mtp = get_associated_type(mtp);
458 set_lowered_type(mtp, new_mtd);
460 set_Call_type(call, new_mtd);
462 /* calculate new in array of the Call */
463 NEW_ARR_A(ir_node *, in, n_param + 2);
464 for (i = 0; i < idx; ++i)
465 in[2 + i] = new_in[i];
466 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
467 in[2 + j++] = get_Call_param(call, i);
469 in[0] = get_Call_mem(call);
470 in[1] = get_Call_ptr(call);
472 /* finally, change the call inputs */
473 set_irn_in(call, n_param + 2, in);
477 * Handle graph transformations before the abi converter does its work.
479 static void arm_before_abi(void *self)
481 arm_code_gen_t *cg = self;
483 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
487 static void *arm_cg_init(be_irg_t *birg);
489 static const arch_code_generator_if_t arm_code_gen_if = {
491 NULL, /* get_pic_base */
492 arm_before_abi, /* before abi introduce */
495 arm_before_ra, /* before register allocation hook */
502 * Initializes the code generator.
504 static void *arm_cg_init(be_irg_t *birg)
506 static ir_type *int_tp = NULL;
507 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env;
511 /* create an integer type with machine size */
512 int_tp = new_type_primitive(mode_Is);
515 cg = XMALLOC(arm_code_gen_t);
516 cg->impl = &arm_code_gen_if;
518 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
522 cg->have_fp_insn = 0;
523 cg->unknown_gp = NULL;
524 cg->unknown_fpa = NULL;
525 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
527 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
529 /* enter the current code generator */
532 return (arch_code_generator_t *)cg;
537 * Maps all intrinsic calls that the backend support
538 * and map all instructions the backend did not support
541 static void arm_handle_intrinsics(void)
543 ir_type *tp, *int_tp, *uint_tp;
547 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
549 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
551 int_tp = new_type_primitive(mode_Is);
552 uint_tp = new_type_primitive(mode_Iu);
554 /* ARM has neither a signed div instruction ... */
556 i_instr_record *map_Div = &records[n_records++].i_instr;
558 tp = new_type_method(2, 1);
559 set_method_param_type(tp, 0, int_tp);
560 set_method_param_type(tp, 1, int_tp);
561 set_method_res_type(tp, 0, int_tp);
563 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
564 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
565 rt_iDiv.mode = mode_T;
566 rt_iDiv.res_mode = mode_Is;
567 rt_iDiv.mem_proj_nr = pn_Div_M;
568 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
569 rt_iDiv.exc_proj_nr = pn_Div_X_except;
570 rt_iDiv.exc_mem_proj_nr = pn_Div_M;
571 rt_iDiv.res_proj_nr = pn_Div_res;
573 add_entity_linkage(rt_iDiv.ent, IR_LINKAGE_CONSTANT);
574 set_entity_visibility(rt_iDiv.ent, ir_visibility_external);
576 map_Div->kind = INTRINSIC_INSTR;
577 map_Div->op = op_Div;
578 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
579 map_Div->ctx = &rt_iDiv;
581 /* ... nor an unsigned div instruction ... */
583 i_instr_record *map_Div = &records[n_records++].i_instr;
585 tp = new_type_method(2, 1);
586 set_method_param_type(tp, 0, uint_tp);
587 set_method_param_type(tp, 1, uint_tp);
588 set_method_res_type(tp, 0, uint_tp);
590 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
591 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
592 rt_uDiv.mode = mode_T;
593 rt_uDiv.res_mode = mode_Iu;
594 rt_uDiv.mem_proj_nr = pn_Div_M;
595 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
596 rt_uDiv.exc_proj_nr = pn_Div_X_except;
597 rt_uDiv.exc_mem_proj_nr = pn_Div_M;
598 rt_uDiv.res_proj_nr = pn_Div_res;
600 set_entity_visibility(rt_uDiv.ent, ir_visibility_external);
602 map_Div->kind = INTRINSIC_INSTR;
603 map_Div->op = op_Div;
604 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
605 map_Div->ctx = &rt_uDiv;
607 /* ... nor a signed mod instruction ... */
609 i_instr_record *map_Mod = &records[n_records++].i_instr;
611 tp = new_type_method(2, 1);
612 set_method_param_type(tp, 0, int_tp);
613 set_method_param_type(tp, 1, int_tp);
614 set_method_res_type(tp, 0, int_tp);
616 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
617 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
618 rt_iMod.mode = mode_T;
619 rt_iMod.res_mode = mode_Is;
620 rt_iMod.mem_proj_nr = pn_Mod_M;
621 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
622 rt_iMod.exc_proj_nr = pn_Mod_X_except;
623 rt_iMod.exc_mem_proj_nr = pn_Mod_M;
624 rt_iMod.res_proj_nr = pn_Mod_res;
626 set_entity_visibility(rt_iMod.ent, ir_visibility_external);
628 map_Mod->kind = INTRINSIC_INSTR;
629 map_Mod->op = op_Mod;
630 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
631 map_Mod->ctx = &rt_iMod;
633 /* ... nor an unsigned mod. */
635 i_instr_record *map_Mod = &records[n_records++].i_instr;
637 tp = new_type_method(2, 1);
638 set_method_param_type(tp, 0, uint_tp);
639 set_method_param_type(tp, 1, uint_tp);
640 set_method_res_type(tp, 0, uint_tp);
642 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
643 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
644 rt_uMod.mode = mode_T;
645 rt_uMod.res_mode = mode_Iu;
646 rt_uMod.mem_proj_nr = pn_Mod_M;
647 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
648 rt_uMod.exc_proj_nr = pn_Mod_X_except;
649 rt_uMod.exc_mem_proj_nr = pn_Mod_M;
650 rt_uMod.res_proj_nr = pn_Mod_res;
652 set_entity_visibility(rt_uMod.ent, ir_visibility_external);
654 map_Mod->kind = INTRINSIC_INSTR;
655 map_Mod->op = op_Mod;
656 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
657 map_Mod->ctx = &rt_uMod;
661 lower_intrinsics(records, n_records, /*part_block_used=*/0);
664 /*****************************************************************
665 * ____ _ _ _____ _____
666 * | _ \ | | | | |_ _|/ ____| /\
667 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
668 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
669 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
670 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
672 *****************************************************************/
674 static arm_isa_t arm_isa_template = {
676 &arm_isa_if, /* isa interface */
677 &arm_gp_regs[REG_SP], /* stack pointer */
678 &arm_gp_regs[REG_R11], /* base pointer */
679 &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */
680 -1, /* stack direction */
681 2, /* power of two stack alignment for calls, 2^2 == 4 */
682 NULL, /* main environment */
684 5, /* reload costs */
686 0, /* use generic register names instead of SP, LR, PC */
687 ARM_FPU_ARCH_FPE, /* FPU architecture */
688 NULL, /* current code generator */
692 * Initializes the backend ISA and opens the output file.
694 static arch_env_t *arm_init(FILE *file_handle)
696 static int inited = 0;
702 isa = XMALLOC(arm_isa_t);
703 memcpy(isa, &arm_isa_template, sizeof(*isa));
708 be_emit_init(file_handle);
710 arm_create_opcodes(&arm_irn_ops);
711 arm_handle_intrinsics();
713 be_gas_emit_types = false;
715 /* needed for the debug support */
716 be_gas_emit_switch_section(GAS_SECTION_TEXT);
717 be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
718 be_emit_write_line();
721 return &isa->arch_env;
727 * Closes the output file and frees the ISA structure.
729 static void arm_done(void *self)
731 arm_isa_t *isa = self;
733 be_gas_emit_decls(isa->arch_env.main_env);
741 * Report the number of register classes.
742 * If we don't have fp instructions, report only GP
743 * here to speed up register allocation (and makes dumps
744 * smaller and more readable).
746 static unsigned arm_get_n_reg_class(void)
752 * Return the register class with requested index.
754 static const arch_register_class_t *arm_get_reg_class(unsigned i)
756 assert(i < N_CLASSES);
757 return &arm_reg_classes[i];
761 * Get the register class which shall be used to store a value of a given mode.
762 * @param self The this pointer.
763 * @param mode The mode in question.
764 * @return A register class which can hold values of the given mode.
766 const arch_register_class_t *arm_get_reg_class_for_mode(const ir_mode *mode)
768 if (mode_is_float(mode))
769 return &arm_reg_classes[CLASS_arm_fpa];
771 return &arm_reg_classes[CLASS_arm_gp];
775 * Produces the type which sits between the stack args and the locals on the stack.
776 * it will contain the return address and space to store the old base pointer.
777 * @return The Firm type modeling the ABI between type.
779 static ir_type *arm_get_between_type(void *self)
781 static ir_type *between_type = NULL;
784 if (between_type == NULL) {
785 between_type = new_type_class(new_id_from_str("arm_between_type"));
786 set_type_size_bytes(between_type, 0);
794 be_abi_call_flags_bits_t flags;
795 const arch_env_t *arch_env;
799 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
801 arm_abi_env_t *env = XMALLOC(arm_abi_env_t);
802 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
803 env->flags = fl.bits;
805 env->arch_env = arch_env;
810 * Generate the routine prologue.
812 * @param self The callback object.
813 * @param mem A pointer to the mem node. Update this if you define new memory.
814 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
815 * @param stack_bias Points to the current stack bias, can be modified if needed.
817 * @return The register which shall be used as a stack frame base.
819 * All nodes which define registers in @p reg_map must keep @p reg_map current.
821 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
823 arm_abi_env_t *env = self;
827 arch_register_class_t *gp;
829 ir_node *fp, *ip, *lr, *pc;
830 ir_node *sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
834 if (env->flags.try_omit_fp)
835 return env->arch_env->sp;
837 fp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
838 ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
839 lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
840 pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
842 gp = &arm_reg_classes[CLASS_arm_gp];
844 block = get_irg_start_block(irg);
846 /* mark bp register as ignore */
847 be_set_constr_single_reg_out(get_Proj_pred(fp),
848 get_Proj_proj(fp), env->arch_env->bp,
849 arch_register_req_type_ignore);
851 /* copy SP to IP (so we can spill it */
852 ip = be_new_Copy(gp, block, sp);
853 be_set_constr_single_reg_out(ip, 0, &arm_gp_regs[REG_R12], 0);
856 store = new_bd_arm_StoreStackM4Inc(NULL, block, sp, fp, ip, lr, pc, *mem);
858 sp = new_r_Proj(block, store, env->arch_env->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
859 arch_set_irn_register(sp, env->arch_env->sp);
860 *mem = new_r_Proj(block, store, mode_M, pn_arm_StoreStackM4Inc_M);
862 /* frame pointer is ip-4 (because ip is our old sp value) */
863 fp = new_bd_arm_Sub_imm(NULL, block, ip, 4, 0);
864 arch_set_irn_register(fp, env->arch_env->bp);
866 /* beware: we change the fp but the StoreStackM4Inc above wants the old
867 * fp value. We are not allowed to spill or anything in the prolog, so we
868 * have to enforce some order here. (scheduler/regalloc are too stupid
869 * to extract this order from register requirements) */
870 add_irn_dep(fp, store);
872 fp = be_new_Copy(gp, block, fp); // XXX Gammelfix: only be_ have custom register requirements
873 be_set_constr_single_reg_out(fp, 0, env->arch_env->bp,
874 arch_register_req_type_ignore);
875 arch_set_irn_register(fp, env->arch_env->bp);
877 be_abi_reg_map_set(reg_map, env->arch_env->bp, fp);
878 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], ip);
879 be_abi_reg_map_set(reg_map, env->arch_env->sp, sp);
880 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
881 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
883 return env->arch_env->bp;
887 * Builds the ARM epilogue
889 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
891 arm_abi_env_t *env = self;
892 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
893 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
894 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
895 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
897 // TODO: Activate Omit fp in epilogue
898 if (env->flags.try_omit_fp) {
899 ir_node *incsp = be_new_IncSP(env->arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
904 load_node = new_bd_arm_LoadStackM3Epilogue(NULL, bl, curr_bp, *mem);
906 curr_bp = new_r_Proj(bl, load_node, env->arch_env->bp->reg_class->mode, pn_arm_LoadStackM3Epilogue_res0);
907 curr_sp = new_r_Proj(bl, load_node, env->arch_env->sp->reg_class->mode, pn_arm_LoadStackM3Epilogue_res1);
908 curr_pc = new_r_Proj(bl, load_node, mode_Iu, pn_arm_LoadStackM3Epilogue_res2);
909 *mem = new_r_Proj(bl, load_node, mode_M, pn_arm_LoadStackM3Epilogue_M);
910 arch_set_irn_register(curr_bp, env->arch_env->bp);
911 arch_set_irn_register(curr_sp, env->arch_env->sp);
912 arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]);
914 be_abi_reg_map_set(reg_map, env->arch_env->sp, curr_sp);
915 be_abi_reg_map_set(reg_map, env->arch_env->bp, curr_bp);
916 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
917 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
920 static const be_abi_callbacks_t arm_abi_callbacks = {
923 arm_get_between_type,
930 * Get the ABI restrictions for procedure calls.
931 * @param self The this pointer.
932 * @param method_type The type of the method (procedure) in question.
933 * @param abi The abi object to be modified
935 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi)
940 int n = get_method_n_params(method_type);
941 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
944 /* set abi flags for calls */
945 call_flags.bits.left_to_right = 0;
946 call_flags.bits.store_args_sequential = 0;
947 /* call_flags.bits.try_omit_fp don't change this we can handle both */
948 call_flags.bits.fp_free = 0;
949 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
951 /* set stack parameter passing style */
952 be_abi_call_set_flags(abi, call_flags, &arm_abi_callbacks);
954 for (i = 0; i < n; i++) {
955 /* reg = get reg for param i; */
956 /* be_abi_call_param_reg(abi, i, reg); */
958 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
960 tp = get_method_param_type(method_type, i);
961 mode = get_type_mode(tp);
962 be_abi_call_param_stack(abi, i, mode, 4, 0, 0);
966 /* set return registers */
967 n = get_method_n_ress(method_type);
969 assert(n <= 2 && "more than two results not supported");
971 /* In case of 64bit returns, we will have two 32bit values */
973 tp = get_method_res_type(method_type, 0);
974 mode = get_type_mode(tp);
976 assert(!mode_is_float(mode) && "two FP results not supported");
978 tp = get_method_res_type(method_type, 1);
979 mode = get_type_mode(tp);
981 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
983 be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0]);
984 be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1]);
986 const arch_register_t *reg;
988 tp = get_method_res_type(method_type, 0);
989 assert(is_atomic_type(tp));
990 mode = get_type_mode(tp);
992 reg = mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0];
993 be_abi_call_res_reg(abi, 0, reg);
997 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn)
1000 if (!is_arm_irn(irn))
1007 * Initializes the code generator interface.
1009 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self)
1012 return &arm_code_gen_if;
1015 list_sched_selector_t arm_sched_selector;
1018 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1020 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector)
1023 memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
1024 /* arm_sched_selector.exectime = arm_sched_exectime; */
1025 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1026 return &arm_sched_selector;
1030 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self)
1037 * Returns the necessary byte alignment for storing a register of given class.
1039 static int arm_get_reg_class_alignment(const arch_register_class_t *cls)
1042 /* ARM is a 32 bit CPU, no need for other alignment */
1046 static const be_execution_unit_t ***arm_get_allowed_execution_units(const ir_node *irn)
1050 panic("Unimplemented arm_get_allowed_execution_units()");
1053 static const be_machine_t *arm_get_machine(const void *self)
1057 panic("Unimplemented arm_get_machine()");
1061 * Return irp irgs in the desired order.
1063 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list)
1071 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1072 * @return 1 if allowed, 0 otherwise
1074 static int arm_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1084 static asm_constraint_flags_t arm_parse_asm_constraint(const char **c)
1086 /* asm not supported */
1088 return ASM_CONSTRAINT_FLAG_INVALID;
1091 static int arm_is_valid_clobber(const char *clobber)
1098 * Returns the libFirm configuration parameter for this backend.
1100 static const backend_params *arm_get_libfirm_params(void)
1102 static const ir_settings_if_conv_t ifconv = {
1103 4, /* maxdepth, doesn't matter for Psi-conversion */
1104 arm_is_mux_allowed /* allows or disallows Mux creation for given selector */
1106 static ir_settings_arch_dep_t ad = {
1108 1, /* Muls are fast enough on ARM but ... */
1109 31, /* ... one shift would be possible better */
1110 NULL, /* no evaluator function */
1111 0, /* SMUL is needed, only in Arch M */
1112 0, /* UMUL is needed, only in Arch M */
1113 32, /* SMUL & UMUL available for 32 bit */
1115 static backend_params p = {
1116 1, /* need dword lowering */
1117 0, /* don't support inline assembler yet */
1118 NULL, /* will be set later */
1119 NULL, /* but yet no creator function */
1120 NULL, /* context for create_intrinsic_fkt */
1121 NULL, /* ifconv_info will be set below */
1122 NULL, /* float arithmetic mode (TODO) */
1123 0, /* no trampoline support: size 0 */
1124 0, /* no trampoline support: align 0 */
1125 NULL, /* no trampoline support: no trampoline builder */
1126 4 /* alignment of stack parameter */
1130 p.if_conv_info = &ifconv;
1134 /* fpu set architectures. */
1135 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1136 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1137 { "fpe", ARM_FPU_ARCH_FPE },
1138 { "fpa", ARM_FPU_ARCH_FPA },
1139 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1140 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1141 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1145 static lc_opt_enum_int_var_t arch_fpu_var = {
1146 &arm_isa_template.fpu_arch, arm_fpu_items
1149 static const lc_opt_table_entry_t arm_options[] = {
1150 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1151 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1155 const arch_isa_if_t arm_isa_if = {
1158 NULL, /* handle_intrinsics */
1159 arm_get_n_reg_class,
1161 arm_get_reg_class_for_mode,
1163 arm_get_code_generator_if,
1164 arm_get_list_sched_selector,
1165 arm_get_ilp_sched_selector,
1166 arm_get_reg_class_alignment,
1167 arm_get_libfirm_params,
1168 arm_get_allowed_execution_units,
1171 NULL, /* mark remat */
1172 arm_parse_asm_constraint,
1173 arm_is_valid_clobber
1176 void be_init_arch_arm(void)
1178 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1179 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1181 lc_opt_add_table(arm_grp, arm_options);
1183 be_register_isa_if("arm", &arm_isa_if);
1185 arm_init_transform();
1189 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);