2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Oliver Richter, Tobias Gneist
30 #include <libcore/lc_opts.h>
31 #include <libcore/lc_opts_enum.h>
33 #include "pseudo_irg.h"
45 #include "../bearch_t.h" /* the general register allocator interface */
46 #include "../benode_t.h"
47 #include "../belower.h"
48 #include "../besched_t.h"
51 #include "../bemachine.h"
52 #include "../beilpsched.h"
53 #include "../bemodule.h"
54 #include "../beirg_t.h"
55 #include "../bespillslots.h"
56 #include "../begnuas.h"
58 #include "bearch_arm_t.h"
60 #include "arm_new_nodes.h" /* arm nodes interface */
61 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
62 #include "arm_transform.h"
63 #include "arm_emitter.h"
64 #include "arm_map_regs.h"
66 #define DEBUG_MODULE "firm.be.arm.isa"
68 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
69 static set *cur_reg_set = NULL;
71 /**************************************************
74 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
75 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
76 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
77 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
80 **************************************************/
83 * Return register requirements for a arm node.
84 * If the node returns a tuple (mode_T) then the proj's
85 * will be asked for this information.
88 arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node,
91 long node_pos = pos == -1 ? 0 : pos;
92 ir_mode *mode = get_irn_mode(node);
95 if (is_Block(node) || mode == mode_X || mode == mode_M) {
96 return arch_no_register_req;
99 if (mode == mode_T && pos < 0) {
100 return arch_no_register_req;
104 /* in case of a proj, we need to get the correct OUT slot */
105 /* of the node corresponding to the proj number */
107 return arch_no_register_req;
110 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
111 node = skip_Proj_const(node);
114 /* get requirements for our own nodes */
115 if (is_arm_irn(node)) {
116 const arch_register_req_t *req;
118 req = get_arm_in_req(node, pos);
120 req = get_arm_out_req(node, node_pos);
126 /* unknown should be transformed by now */
127 assert(!is_Unknown(node));
128 return arch_no_register_req;
131 static void arm_set_irn_reg(const void *self, ir_node *irn,
132 const arch_register_t *reg)
137 if (get_irn_mode(irn) == mode_X) {
142 pos = get_Proj_proj(irn);
143 irn = skip_Proj(irn);
146 if (is_arm_irn(irn)) {
147 const arch_register_t **slots;
149 slots = get_arm_slots(irn);
153 /* here we set the registers for the Phi nodes */
154 arm_set_firm_reg(irn, reg, cur_reg_set);
158 static const arch_register_t *arm_get_irn_reg(const void *self,
162 const arch_register_t *reg = NULL;
167 if (get_irn_mode(irn) == mode_X) {
171 pos = get_Proj_proj(irn);
172 irn = skip_Proj_const(irn);
175 if (is_arm_irn(irn)) {
176 const arch_register_t **slots;
177 slots = get_arm_slots(irn);
181 reg = arm_get_firm_reg(irn, cur_reg_set);
187 static arch_irn_class_t arm_classify(const void *self, const ir_node *irn)
190 irn = skip_Proj_const(irn);
193 return arch_irn_class_branch;
195 else if (is_arm_irn(irn)) {
196 return arch_irn_class_normal;
202 static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn)
205 irn = skip_Proj_const(irn);
207 if (is_arm_irn(irn)) {
208 return get_arm_flags(irn);
210 else if (is_Unknown(irn)) {
211 return arch_irn_flags_ignore;
217 static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn)
221 /* TODO: return the entity assigned to the frame */
225 static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
226 /* TODO: set the entity assigned to the frame */
230 * This function is called by the generic backend to correct offsets for
231 * nodes accessing the stack.
233 static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
234 /* TODO: correct offset if irn accesses the stack */
237 static int arm_get_sp_bias(const void *self, const ir_node *irn)
244 /* fill register allocator interface */
246 static const arch_irn_ops_if_t arm_irn_ops_if = {
252 arm_get_frame_entity,
253 arm_set_frame_entity,
256 NULL, /* get_inverse */
257 NULL, /* get_op_estimated_cost */
258 NULL, /* possible_memory_operand */
259 NULL, /* perform_memory_operand */
262 arm_irn_ops_t arm_irn_ops = {
269 /**************************************************
272 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
273 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
274 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
275 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
278 **************************************************/
281 * Transforms the standard Firm graph into
284 static void arm_prepare_graph(void *self) {
285 arm_code_gen_t *cg = self;
287 /* transform nodes into assembler instructions */
288 arm_transform_graph(cg);
290 /* do local optimizations (mainly CSE) */
291 local_optimize_graph(cg->irg);
294 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
296 /* do code placement, to optimize the position of constants */
300 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
304 * Called immediately before emit phase.
306 static void arm_finish_irg(void *self)
309 /* TODO: - fix offsets for nodes accessing stack
316 * These are some hooks which must be filled but are probably not needed.
318 static void arm_before_sched(void *self)
321 /* Some stuff you need to do after scheduling but before register allocation */
324 static void arm_before_ra(void *self)
327 /* Some stuff you need to do immediately after register allocation */
331 * We transform Spill and Reload here. This needs to be done before
332 * stack biasing otherwise we would miss the corrected offset for these nodes.
334 static void arm_after_ra(void *self)
336 arm_code_gen_t *cg = self;
337 be_coalesce_spillslots(cg->birg);
341 * Emits the code, closes the output file and frees
342 * the code generator interface.
344 static void arm_emit_and_done(void *self) {
345 arm_code_gen_t *cg = self;
346 ir_graph *irg = cg->irg;
348 arm_gen_routine(cg, irg);
352 /* de-allocate code generator */
353 del_set(cg->reg_set);
358 * Move a double floating point value into an integer register.
359 * Place the move operation into block bl.
361 * Handle some special cases here:
362 * 1.) A constant: simply split into two
363 * 2.) A load: simply split into two
365 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
366 ir_node **resH, ir_node **resL) {
368 tarval *tv = get_Const_tarval(arg);
371 /* get the upper 32 bits */
372 v = get_tarval_sub_bits(tv, 7);
373 v = (v << 8) | get_tarval_sub_bits(tv, 6);
374 v = (v << 8) | get_tarval_sub_bits(tv, 5);
375 v = (v << 8) | get_tarval_sub_bits(tv, 4);
376 *resH = new_Const_long(mode_Is, v);
378 /* get the lower 32 bits */
379 v = get_tarval_sub_bits(tv, 3);
380 v = (v << 8) | get_tarval_sub_bits(tv, 2);
381 v = (v << 8) | get_tarval_sub_bits(tv, 1);
382 v = (v << 8) | get_tarval_sub_bits(tv, 0);
383 *resL = new_Const_long(mode_Is, v);
385 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
386 /* FIXME: handling of low/high depends on LE/BE here */
390 ir_graph *irg = current_ir_graph;
393 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
395 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
396 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
397 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
403 * Move a single floating point value into an integer register.
404 * Place the move operation into block bl.
406 * Handle some special cases here:
407 * 1.) A constant: simply move
408 * 2.) A load: simply load
410 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg)
415 tarval *tv = get_Const_tarval(arg);
418 /* get the lower 32 bits */
419 v = get_tarval_sub_bits(tv, 3);
420 v = (v << 8) | get_tarval_sub_bits(tv, 2);
421 v = (v << 8) | get_tarval_sub_bits(tv, 1);
422 v = (v << 8) | get_tarval_sub_bits(tv, 0);
423 return new_Const_long(mode_Is, v);
425 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
428 load = skip_Proj(arg);
435 * Convert the arguments of a call to support the
436 * ARM calling convention of general purpose AND floating
439 static void handle_calls(ir_node *call, void *env)
441 arm_code_gen_t *cg = env;
442 int i, j, n, size, idx, flag, n_param, n_res;
443 ir_type *mtp, *new_mtd, *new_tp[5];
444 ir_node *new_in[5], **in;
450 /* check, if we need conversions */
451 n = get_Call_n_params(call);
452 mtp = get_Call_type(call);
453 assert(get_method_n_params(mtp) == n);
455 /* it's always enough to handle the first 4 parameters */
458 flag = size = idx = 0;
459 bl = get_nodes_block(call);
460 for (i = 0; i < n; ++i) {
461 ir_type *param_tp = get_method_param_type(mtp, i);
463 if (is_compound_type(param_tp)) {
464 /* an aggregate parameter: bad case */
468 /* a primitive parameter */
469 ir_mode *mode = get_type_mode(param_tp);
471 if (mode_is_float(mode)) {
472 if (get_mode_size_bits(mode) > 32) {
473 ir_node *mem = get_Call_mem(call);
475 /* Beware: ARM wants the high part first */
477 new_tp[idx] = cg->int_tp;
478 new_tp[idx+1] = cg->int_tp;
479 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
481 set_Call_mem(call, mem);
485 new_tp[idx] = cg->int_tp;
486 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
493 new_tp[idx] = param_tp;
494 new_in[idx] = get_Call_param(call, i);
503 /* if flag is NOT set, no need to translate the method type */
507 /* construct a new method type */
509 n_param = get_method_n_params(mtp) - n + idx;
510 n_res = get_method_n_ress(mtp);
511 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
513 for (i = 0; i < idx; ++i)
514 set_method_param_type(new_mtd, i, new_tp[i]);
515 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
516 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
517 for (i = 0; i < n_res; ++i)
518 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
520 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
521 set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp));
523 if (is_lowered_type(mtp)) {
524 mtp = get_associated_type(mtp);
526 set_lowered_type(mtp, new_mtd);
528 set_Call_type(call, new_mtd);
530 /* calculate new in array of the Call */
531 NEW_ARR_A(ir_node *, in, n_param + 2);
532 for (i = 0; i < idx; ++i)
533 in[2 + i] = new_in[i];
534 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
535 in[2 + j++] = get_Call_param(call, i);
537 in[0] = get_Call_mem(call);
538 in[1] = get_Call_ptr(call);
540 /* finally, change the call inputs */
541 set_irn_in(call, n_param + 2, in);
545 * Handle graph transformations before the abi converter does its work.
547 static void arm_before_abi(void *self) {
548 arm_code_gen_t *cg = self;
550 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
554 static void *arm_cg_init(be_irg_t *birg);
556 static const arch_code_generator_if_t arm_code_gen_if = {
558 arm_before_abi, /* before abi introduce */
561 arm_before_sched, /* before scheduling hook */
562 arm_before_ra, /* before register allocation hook */
569 * Initializes the code generator.
571 static void *arm_cg_init(be_irg_t *birg) {
572 static ir_type *int_tp = NULL;
573 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
577 /* create an integer type with machine size */
578 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
581 cg = xmalloc(sizeof(*cg));
582 cg->impl = &arm_code_gen_if;
584 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
585 cg->arch_env = birg->main_env->arch_env;
589 cg->have_fp_insn = 0;
590 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
592 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
594 cur_reg_set = cg->reg_set;
598 /* enter the current code generator */
601 return (arch_code_generator_t *)cg;
606 * Maps all intrinsic calls that the backend support
607 * and map all instructions the backend did not support
610 static void arm_handle_intrinsics(void) {
611 ir_type *tp, *int_tp, *uint_tp;
615 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
617 int_tp = new_type_primitive(ID("int"), mode_Is);
618 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
620 /* ARM has neither a signed div instruction ... */
623 i_instr_record *map_Div = &records[n_records++].i_instr;
625 tp = new_type_method(ID("rt_iDiv"), 2, 1);
626 set_method_param_type(tp, 0, int_tp);
627 set_method_param_type(tp, 1, int_tp);
628 set_method_res_type(tp, 0, int_tp);
630 rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
631 rt_Div.mode = mode_T;
632 rt_Div.res_mode = mode_Is;
633 rt_Div.mem_proj_nr = pn_Div_M;
634 rt_Div.regular_proj_nr = pn_Div_X_regular;
635 rt_Div.exc_proj_nr = pn_Div_X_except;
636 rt_Div.exc_mem_proj_nr = pn_Div_M;
637 rt_Div.res_proj_nr = pn_Div_res;
639 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
641 map_Div->kind = INTRINSIC_INSTR;
642 map_Div->op = op_Div;
643 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
644 map_Div->ctx = &rt_Div;
646 /* ... nor an unsigned div instruction ... */
649 i_instr_record *map_Div = &records[n_records++].i_instr;
651 tp = new_type_method(ID("rt_uDiv"), 2, 1);
652 set_method_param_type(tp, 0, uint_tp);
653 set_method_param_type(tp, 1, uint_tp);
654 set_method_res_type(tp, 0, uint_tp);
656 rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
657 rt_Div.mode = mode_T;
658 rt_Div.res_mode = mode_Iu;
659 rt_Div.mem_proj_nr = pn_Div_M;
660 rt_Div.regular_proj_nr = pn_Div_X_regular;
661 rt_Div.exc_proj_nr = pn_Div_X_except;
662 rt_Div.exc_mem_proj_nr = pn_Div_M;
663 rt_Div.res_proj_nr = pn_Div_res;
665 set_entity_visibility(rt_Div.ent, visibility_external_allocated);
667 map_Div->kind = INTRINSIC_INSTR;
668 map_Div->op = op_Div;
669 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
670 map_Div->ctx = &rt_Div;
672 /* ... nor a signed mod instruction ... */
675 i_instr_record *map_Mod = &records[n_records++].i_instr;
677 tp = new_type_method(ID("rt_iMod"), 2, 1);
678 set_method_param_type(tp, 0, int_tp);
679 set_method_param_type(tp, 1, int_tp);
680 set_method_res_type(tp, 0, int_tp);
682 rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
683 rt_Mod.mode = mode_T;
684 rt_Mod.res_mode = mode_Is;
685 rt_Mod.mem_proj_nr = pn_Mod_M;
686 rt_Mod.regular_proj_nr = pn_Mod_X_regular;
687 rt_Mod.exc_proj_nr = pn_Mod_X_except;
688 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
689 rt_Mod.res_proj_nr = pn_Mod_res;
691 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
693 map_Mod->kind = INTRINSIC_INSTR;
694 map_Mod->op = op_Mod;
695 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
696 map_Mod->ctx = &rt_Mod;
698 /* ... nor an unsigned mod. */
701 i_instr_record *map_Mod = &records[n_records++].i_instr;
703 tp = new_type_method(ID("rt_uMod"), 2, 1);
704 set_method_param_type(tp, 0, uint_tp);
705 set_method_param_type(tp, 1, uint_tp);
706 set_method_res_type(tp, 0, uint_tp);
708 rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
709 rt_Mod.mode = mode_T;
710 rt_Mod.res_mode = mode_Iu;
711 rt_Mod.mem_proj_nr = pn_Mod_M;
712 rt_Mod.regular_proj_nr = pn_Mod_X_regular;
713 rt_Mod.exc_proj_nr = pn_Mod_X_except;
714 rt_Mod.exc_mem_proj_nr = pn_Mod_M;
715 rt_Mod.res_proj_nr = pn_Mod_res;
717 set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
719 map_Mod->kind = INTRINSIC_INSTR;
720 map_Mod->op = op_Mod;
721 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
722 map_Mod->ctx = &rt_Mod;
726 lower_intrinsics(records, n_records);
729 /*****************************************************************
730 * ____ _ _ _____ _____
731 * | _ \ | | | | |_ _|/ ____| /\
732 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
733 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
734 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
735 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
737 *****************************************************************/
739 static arm_isa_t arm_isa_template = {
741 &arm_isa_if, /* isa interface */
742 &arm_gp_regs[REG_SP], /* stack pointer */
743 &arm_gp_regs[REG_R11], /* base pointer */
744 -1, /* stack direction */
745 NULL, /* main environment */
747 5, /* reload costs */
749 0, /* use generic register names instead of SP, LR, PC */
750 ARM_FPU_ARCH_FPE, /* FPU architecture */
751 NULL, /* current code generator */
752 { NULL, }, /* emitter environment */
756 * Initializes the backend ISA and opens the output file.
758 static void *arm_init(FILE *file_handle) {
759 static int inited = 0;
765 isa = xmalloc(sizeof(*isa));
766 memcpy(isa, &arm_isa_template, sizeof(*isa));
771 be_emit_init_env(&isa->emit, file_handle);
773 arm_create_opcodes();
774 arm_register_copy_attr_func();
775 arm_handle_intrinsics();
777 /* we mark referenced global entities, so we can only emit those which
778 * are actually referenced. (Note: you mustn't use the type visited flag
779 * elsewhere in the backend)
781 inc_master_type_visited();
790 * Closes the output file and frees the ISA structure.
792 static void arm_done(void *self) {
793 arm_isa_t *isa = self;
795 be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
797 be_emit_destroy_env(&isa->emit);
803 * Report the number of register classes.
804 * If we don't have fp instructions, report only GP
805 * here to speed up register allocation (and makes dumps
806 * smaller and more readable).
808 static int arm_get_n_reg_class(const void *self) {
809 const arm_isa_t *isa = self;
811 /* ARGH! is called BEFORE transform */
813 return isa->cg->have_fp_insn ? 2 : 1;
817 * Return the register class with requested index.
819 static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
820 return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa];
824 * Get the register class which shall be used to store a value of a given mode.
825 * @param self The this pointer.
826 * @param mode The mode in question.
827 * @return A register class which can hold values of the given mode.
829 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
830 if (mode_is_float(mode))
831 return &arm_reg_classes[CLASS_arm_fpa];
833 return &arm_reg_classes[CLASS_arm_gp];
837 * Produces the type which sits between the stack args and the locals on the stack.
838 * it will contain the return address and space to store the old base pointer.
839 * @return The Firm type modelling the ABI between type.
841 static ir_type *arm_get_between_type(void *self) {
842 static ir_type *between_type = NULL;
843 static ir_entity *old_bp_ent = NULL;
846 ir_entity *ret_addr_ent;
847 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
848 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
850 between_type = new_type_class(new_id_from_str("arm_between_type"));
851 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
852 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
854 set_entity_offset(old_bp_ent, 0);
855 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
856 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
864 be_abi_call_flags_bits_t flags;
865 const arch_env_t *arch_env;
866 const arch_isa_t *isa;
870 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
872 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
873 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
874 env->flags = fl.bits;
876 env->arch_env = arch_env;
877 env->isa = arch_env->isa;
881 static void arm_abi_dont_save_regs(void *self, pset *s)
883 arm_abi_env_t *env = self;
884 if (env->flags.try_omit_fp)
885 pset_insert_ptr(s, env->isa->bp);
891 * Build the ARM prolog
893 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
894 ir_node *keep, *store;
895 arm_abi_env_t *env = self;
896 ir_graph *irg = env->irg;
897 ir_node *block = get_irg_start_block(irg);
898 // ir_node *regs[16];
900 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
902 ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
903 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
904 ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
905 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
906 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
907 // ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]);
908 // ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]);
909 // ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]);
910 // ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]);
912 if(env->flags.try_omit_fp)
915 ip = be_new_Copy(gp, irg, block, sp );
916 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
917 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
919 // if (r0) regs[n_regs++] = r0;
920 // if (r1) regs[n_regs++] = r1;
921 // if (r2) regs[n_regs++] = r2;
922 // if (r3) regs[n_regs++] = r3;
923 // sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
924 // set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
925 // arch_set_irn_register(env->arch_env, sp, env->isa->sp);
926 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
928 // set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
929 // arch_set_irn_register(env->arch_env, store, env->isa->sp);
931 sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
932 arch_set_irn_register(env->arch_env, sp, env->isa->sp);
933 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
935 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
936 be_node_set_reg_class(keep, 1, gp);
937 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
938 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
940 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
941 new_tarval_from_long(4, get_irn_mode(fp)));
943 //set_arm_req_out_all(fp, fp_req);
944 //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
945 arch_set_irn_register(env->arch_env, fp, env->isa->bp);
947 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
948 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
949 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2);
950 // be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3);
951 be_abi_reg_map_set(reg_map, env->isa->bp, fp);
952 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
953 be_abi_reg_map_set(reg_map, env->isa->sp, sp);
954 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
955 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
960 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
961 arm_abi_env_t *env = self;
962 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
963 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
964 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
965 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
967 // TODO: Activate Omit fp in epilogue
968 if(env->flags.try_omit_fp) {
969 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
970 add_irn_dep(curr_sp, *mem);
972 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
973 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
974 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
975 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
977 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
978 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
979 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
980 be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
984 tarval *tv = new_tarval_from_long(12,mode_Iu);
985 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
987 //set_arm_req_out_all(sub12_node, sub12_req);
988 arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
989 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
991 //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
992 //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
993 //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
994 curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
995 curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
996 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
997 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
998 arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
999 arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
1000 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
1002 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
1003 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
1004 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
1005 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
1008 static const be_abi_callbacks_t arm_abi_callbacks = {
1011 arm_get_between_type,
1012 arm_abi_dont_save_regs,
1019 * Get the ABI restrictions for procedure calls.
1020 * @param self The this pointer.
1021 * @param method_type The type of the method (procedure) in question.
1022 * @param abi The abi object to be modified
1024 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1028 int n = get_method_n_params(method_type);
1029 be_abi_call_flags_t flags = {
1031 0, /* store from left to right */
1032 0, /* store arguments sequential */
1033 1, /* try to omit the frame pointer */
1034 1, /* the function can use any register as frame pointer */
1035 1 /* a call can take the callee's address as an immediate */
1039 /* set stack parameter passing style */
1040 be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
1042 for (i = 0; i < n; i++) {
1043 /* reg = get reg for param i; */
1044 /* be_abi_call_param_reg(abi, i, reg); */
1047 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1049 be_abi_call_param_stack(abi, i, 4, 0, 0);
1052 /* default: return value is in R0 resp. F0 */
1053 assert(get_method_n_ress(method_type) < 2);
1054 if (get_method_n_ress(method_type) > 0) {
1055 tp = get_method_res_type(method_type, 0);
1056 mode = get_type_mode(tp);
1058 be_abi_call_res_reg(abi, 0,
1059 mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]);
1063 static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1064 return &arm_irn_ops;
1067 const arch_irn_handler_t arm_irn_handler = {
1071 const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
1072 return &arm_irn_handler;
1075 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1076 if(!is_arm_irn(irn))
1083 * Initializes the code generator interface.
1085 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1086 return &arm_code_gen_if;
1089 list_sched_selector_t arm_sched_selector;
1092 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1094 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1095 memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1096 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1097 return &arm_sched_selector;
1100 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
1105 * Returns the necessary byte alignment for storing a register of given class.
1107 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1108 /* ARM is a 32 bit CPU, no need for other alignment */
1112 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1118 static const be_machine_t *arm_get_machine(const void *self) {
1125 * Return irp irgs in the desired order.
1127 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
1132 * Returns the libFirm configuration parameter for this backend.
1134 static const backend_params *arm_get_libfirm_params(void) {
1135 static arch_dep_params_t ad = {
1137 1, /* Muls are fast enough on ARM but ... */
1138 1, /* ... one shift would be possible better */
1139 0, /* SMUL is needed, only in Arch M*/
1140 0, /* UMUL is needed, only in Arch M */
1141 32, /* SMUL & UMUL available for 32 bit */
1143 static backend_params p = {
1144 1, /* need dword lowering */
1145 0, /* don't support inline assembler yet */
1146 NULL, /* no additional opcodes */
1147 NULL, /* will be set later */
1148 NULL, /* but yet no creator function */
1149 NULL, /* context for create_intrinsic_fkt */
1150 NULL, /* no if conversion settings */
1157 /* fpu set architectures. */
1158 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1159 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1160 { "fpe", ARM_FPU_ARCH_FPE },
1161 { "fpa", ARM_FPU_ARCH_FPA },
1162 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1163 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1164 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1168 static lc_opt_enum_int_var_t arch_fpu_var = {
1169 &arm_isa_template.fpu_arch, arm_fpu_items
1172 static const lc_opt_table_entry_t arm_options[] = {
1173 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1174 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1178 const arch_isa_if_t arm_isa_if = {
1181 arm_get_n_reg_class,
1183 arm_get_reg_class_for_mode,
1185 arm_get_irn_handler,
1186 arm_get_code_generator_if,
1187 arm_get_list_sched_selector,
1188 arm_get_ilp_sched_selector,
1189 arm_get_reg_class_alignment,
1190 arm_get_libfirm_params,
1191 arm_get_allowed_execution_units,
1196 void be_init_arch_arm(void)
1198 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1199 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1201 lc_opt_add_table(arm_grp, arm_options);
1203 be_register_isa_if("arm", &arm_isa_if);
1205 arm_init_transform();
1208 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);