2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Oliver Richter, Tobias Gneist
31 #include "lc_opts_enum.h"
33 #include "pseudo_irg.h"
40 #include "iroptimize.h"
48 #include "../bearch_t.h" /* the general register allocator interface */
49 #include "../benode_t.h"
50 #include "../belower.h"
51 #include "../besched_t.h"
54 #include "../bemachine.h"
55 #include "../beilpsched.h"
56 #include "../bemodule.h"
57 #include "../beirg_t.h"
58 #include "../bespillslots.h"
59 #include "../begnuas.h"
61 #include "bearch_arm_t.h"
63 #include "arm_new_nodes.h" /* arm nodes interface */
64 #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
65 #include "arm_transform.h"
66 #include "arm_optimize.h"
67 #include "arm_emitter.h"
68 #include "arm_map_regs.h"
70 #define DEBUG_MODULE "firm.be.arm.isa"
72 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
73 static set *cur_reg_set = NULL;
75 /**************************************************
78 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
79 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
80 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
81 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
84 **************************************************/
87 * Return register requirements for a arm node.
88 * If the node returns a tuple (mode_T) then the proj's
89 * will be asked for this information.
91 static const arch_register_req_t *arm_get_irn_reg_req(const ir_node *node,
94 long node_pos = pos == -1 ? 0 : pos;
95 ir_mode *mode = get_irn_mode(node);
97 if (is_Block(node) || mode == mode_X) {
98 return arch_no_register_req;
101 if (mode == mode_T && pos < 0) {
102 return arch_no_register_req;
107 return arch_no_register_req;
110 return arch_no_register_req;
113 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
114 node = skip_Proj_const(node);
117 /* get requirements for our own nodes */
118 if (is_arm_irn(node)) {
119 const arch_register_req_t *req;
121 req = get_arm_in_req(node, pos);
123 req = get_arm_out_req(node, node_pos);
129 /* unknown should be transformed by now */
130 assert(!is_Unknown(node));
131 return arch_no_register_req;
134 static void arm_set_irn_reg(ir_node *irn, const arch_register_t *reg)
138 if (get_irn_mode(irn) == mode_X) {
143 pos = get_Proj_proj(irn);
144 irn = skip_Proj(irn);
147 if (is_arm_irn(irn)) {
148 const arch_register_t **slots;
150 slots = get_arm_slots(irn);
154 /* here we set the registers for the Phi nodes */
155 arm_set_firm_reg(irn, reg, cur_reg_set);
159 static const arch_register_t *arm_get_irn_reg(const ir_node *irn)
162 const arch_register_t *reg = NULL;
166 if (get_irn_mode(irn) == mode_X) {
170 pos = get_Proj_proj(irn);
171 irn = skip_Proj_const(irn);
174 if (is_arm_irn(irn)) {
175 const arch_register_t **slots;
176 slots = get_arm_slots(irn);
180 reg = arm_get_firm_reg(irn, cur_reg_set);
186 static arch_irn_class_t arm_classify(const ir_node *irn)
188 irn = skip_Proj_const(irn);
191 return arch_irn_class_branch;
193 else if (is_arm_irn(irn)) {
194 return arch_irn_class_normal;
200 static arch_irn_flags_t arm_get_flags(const ir_node *irn)
202 arch_irn_flags_t flags = arch_irn_flags_none;
204 if(is_Unknown(irn)) {
205 return arch_irn_flags_ignore;
208 if (is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
209 ir_node *pred = get_Proj_pred(irn);
210 if (is_arm_irn(pred)) {
211 flags = get_arm_out_flags(pred, get_Proj_proj(irn));
216 if (is_arm_irn(irn)) {
217 flags |= get_arm_flags(irn);
223 static ir_entity *arm_get_frame_entity(const ir_node *irn) {
224 /* we do NOT transform be_Spill or be_Reload nodes, so we never
225 have frame access using ARM nodes. */
230 static void arm_set_frame_entity(ir_node *irn, ir_entity *ent) {
233 panic("arm_set_frame_entity() called. This should not happen.");
237 * This function is called by the generic backend to correct offsets for
238 * nodes accessing the stack.
240 static void arm_set_stack_bias(ir_node *irn, int bias)
244 /* TODO: correct offset if irn accesses the stack */
247 static int arm_get_sp_bias(const ir_node *irn)
253 /* fill register allocator interface */
255 static const arch_irn_ops_t arm_irn_ops = {
261 arm_get_frame_entity,
262 arm_set_frame_entity,
265 NULL, /* get_inverse */
266 NULL, /* get_op_estimated_cost */
267 NULL, /* possible_memory_operand */
268 NULL, /* perform_memory_operand */
271 /**************************************************
274 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
275 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
276 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
277 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
280 **************************************************/
283 * Transforms the standard Firm graph into
286 static void arm_prepare_graph(void *self) {
287 arm_code_gen_t *cg = self;
289 /* transform nodes into assembler instructions */
290 arm_transform_graph(cg);
292 /* do local optimizations (mainly CSE) */
293 local_optimize_graph(cg->irg);
296 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
298 /* do code placement, to optimize the position of constants */
302 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
306 * Called immediately before emit phase.
308 static void arm_finish_irg(void *self)
310 arm_code_gen_t *cg = self;
312 /* do peephole optimizations and fix stack offsets */
313 arm_peephole_optimization(cg);
318 * These are some hooks which must be filled but are probably not needed.
320 static void arm_before_sched(void *self)
323 /* Some stuff you need to do after scheduling but before register allocation */
326 static void arm_before_ra(void *self)
329 /* Some stuff you need to do immediately after register allocation */
333 * We transform Spill and Reload here. This needs to be done before
334 * stack biasing otherwise we would miss the corrected offset for these nodes.
336 static void arm_after_ra(void *self)
338 arm_code_gen_t *cg = self;
339 be_coalesce_spillslots(cg->birg);
343 * Emits the code, closes the output file and frees
344 * the code generator interface.
346 static void arm_emit_and_done(void *self) {
347 arm_code_gen_t *cg = self;
348 ir_graph *irg = cg->irg;
350 arm_gen_routine(cg, irg);
354 /* de-allocate code generator */
355 del_set(cg->reg_set);
360 * Move a double floating point value into an integer register.
361 * Place the move operation into block bl.
363 * Handle some special cases here:
364 * 1.) A constant: simply split into two
365 * 2.) A load: simply split into two
367 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
368 ir_node **resH, ir_node **resL) {
370 tarval *tv = get_Const_tarval(arg);
373 /* get the upper 32 bits */
374 v = get_tarval_sub_bits(tv, 7);
375 v = (v << 8) | get_tarval_sub_bits(tv, 6);
376 v = (v << 8) | get_tarval_sub_bits(tv, 5);
377 v = (v << 8) | get_tarval_sub_bits(tv, 4);
378 *resH = new_Const_long(mode_Is, v);
380 /* get the lower 32 bits */
381 v = get_tarval_sub_bits(tv, 3);
382 v = (v << 8) | get_tarval_sub_bits(tv, 2);
383 v = (v << 8) | get_tarval_sub_bits(tv, 1);
384 v = (v << 8) | get_tarval_sub_bits(tv, 0);
385 *resL = new_Const_long(mode_Is, v);
387 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
388 /* FIXME: handling of low/high depends on LE/BE here */
392 ir_graph *irg = current_ir_graph;
395 conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
397 *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
398 *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
399 mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
405 * Move a single floating point value into an integer register.
406 * Place the move operation into block bl.
408 * Handle some special cases here:
409 * 1.) A constant: simply move
410 * 2.) A load: simply load
412 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg)
417 tarval *tv = get_Const_tarval(arg);
420 /* get the lower 32 bits */
421 v = get_tarval_sub_bits(tv, 3);
422 v = (v << 8) | get_tarval_sub_bits(tv, 2);
423 v = (v << 8) | get_tarval_sub_bits(tv, 1);
424 v = (v << 8) | get_tarval_sub_bits(tv, 0);
425 return new_Const_long(mode_Is, v);
427 else if (get_irn_op(skip_Proj(arg)) == op_Load) {
430 load = skip_Proj(arg);
437 * Convert the arguments of a call to support the
438 * ARM calling convention of general purpose AND floating
441 static void handle_calls(ir_node *call, void *env)
443 arm_code_gen_t *cg = env;
444 int i, j, n, size, idx, flag, n_param, n_res, first_variadic;
445 ir_type *mtp, *new_mtd, *new_tp[5];
446 ir_node *new_in[5], **in;
452 /* check, if we need conversions */
453 n = get_Call_n_params(call);
454 mtp = get_Call_type(call);
455 assert(get_method_n_params(mtp) == n);
457 /* it's always enough to handle the first 4 parameters */
460 flag = size = idx = 0;
461 bl = get_nodes_block(call);
462 for (i = 0; i < n; ++i) {
463 ir_type *param_tp = get_method_param_type(mtp, i);
465 if (is_compound_type(param_tp)) {
466 /* an aggregate parameter: bad case */
470 /* a primitive parameter */
471 ir_mode *mode = get_type_mode(param_tp);
473 if (mode_is_float(mode)) {
474 if (get_mode_size_bits(mode) > 32) {
475 ir_node *mem = get_Call_mem(call);
477 /* Beware: ARM wants the high part first */
479 new_tp[idx] = cg->int_tp;
480 new_tp[idx+1] = cg->int_tp;
481 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
483 set_Call_mem(call, mem);
487 new_tp[idx] = cg->int_tp;
488 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
495 new_tp[idx] = param_tp;
496 new_in[idx] = get_Call_param(call, i);
505 /* if flag is NOT set, no need to translate the method type */
509 /* construct a new method type */
511 n_param = get_method_n_params(mtp) - n + idx;
512 n_res = get_method_n_ress(mtp);
513 new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
515 for (i = 0; i < idx; ++i)
516 set_method_param_type(new_mtd, i, new_tp[i]);
517 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
518 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
519 for (i = 0; i < n_res; ++i)
520 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
522 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
523 first_variadic = get_method_first_variadic_param_index(mtp);
524 if (first_variadic >= 0)
525 set_method_first_variadic_param_index(new_mtd, first_variadic);
527 if (is_lowered_type(mtp)) {
528 mtp = get_associated_type(mtp);
530 set_lowered_type(mtp, new_mtd);
532 set_Call_type(call, new_mtd);
534 /* calculate new in array of the Call */
535 NEW_ARR_A(ir_node *, in, n_param + 2);
536 for (i = 0; i < idx; ++i)
537 in[2 + i] = new_in[i];
538 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
539 in[2 + j++] = get_Call_param(call, i);
541 in[0] = get_Call_mem(call);
542 in[1] = get_Call_ptr(call);
544 /* finally, change the call inputs */
545 set_irn_in(call, n_param + 2, in);
549 * Handle graph transformations before the abi converter does its work.
551 static void arm_before_abi(void *self) {
552 arm_code_gen_t *cg = self;
554 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
558 static void *arm_cg_init(be_irg_t *birg);
560 static const arch_code_generator_if_t arm_code_gen_if = {
562 NULL, /* get_pic_base */
563 arm_before_abi, /* before abi introduce */
566 arm_before_sched, /* before scheduling hook */
567 arm_before_ra, /* before register allocation hook */
574 * Initializes the code generator.
576 static void *arm_cg_init(be_irg_t *birg) {
577 static ir_type *int_tp = NULL;
578 arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env;
582 /* create an integer type with machine size */
583 int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
586 cg = xmalloc(sizeof(*cg));
587 cg->impl = &arm_code_gen_if;
589 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
590 cg->arch_env = birg->main_env->arch_env;
594 cg->have_fp_insn = 0;
595 cg->unknown_gp = NULL;
596 cg->unknown_fpa = NULL;
597 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
599 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
601 cur_reg_set = cg->reg_set;
603 /* enter the current code generator */
606 return (arch_code_generator_t *)cg;
611 * Maps all intrinsic calls that the backend support
612 * and map all instructions the backend did not support
615 static void arm_handle_intrinsics(void) {
616 ir_type *tp, *int_tp, *uint_tp;
620 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
622 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
624 int_tp = new_type_primitive(ID("int"), mode_Is);
625 uint_tp = new_type_primitive(ID("uint"), mode_Iu);
627 /* ARM has neither a signed div instruction ... */
629 i_instr_record *map_Div = &records[n_records++].i_instr;
631 tp = new_type_method(ID("rt_iDiv"), 2, 1);
632 set_method_param_type(tp, 0, int_tp);
633 set_method_param_type(tp, 1, int_tp);
634 set_method_res_type(tp, 0, int_tp);
636 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
637 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
638 rt_iDiv.mode = mode_T;
639 rt_iDiv.res_mode = mode_Is;
640 rt_iDiv.mem_proj_nr = pn_Div_M;
641 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
642 rt_iDiv.exc_proj_nr = pn_Div_X_except;
643 rt_iDiv.exc_mem_proj_nr = pn_Div_M;
644 rt_iDiv.res_proj_nr = pn_Div_res;
646 set_entity_visibility(rt_iDiv.ent, visibility_external_allocated);
648 map_Div->kind = INTRINSIC_INSTR;
649 map_Div->op = op_Div;
650 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
651 map_Div->ctx = &rt_iDiv;
653 /* ... nor an unsigned div instruction ... */
655 i_instr_record *map_Div = &records[n_records++].i_instr;
657 tp = new_type_method(ID("rt_uDiv"), 2, 1);
658 set_method_param_type(tp, 0, uint_tp);
659 set_method_param_type(tp, 1, uint_tp);
660 set_method_res_type(tp, 0, uint_tp);
662 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
663 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
664 rt_uDiv.mode = mode_T;
665 rt_uDiv.res_mode = mode_Iu;
666 rt_uDiv.mem_proj_nr = pn_Div_M;
667 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
668 rt_uDiv.exc_proj_nr = pn_Div_X_except;
669 rt_uDiv.exc_mem_proj_nr = pn_Div_M;
670 rt_uDiv.res_proj_nr = pn_Div_res;
672 set_entity_visibility(rt_uDiv.ent, visibility_external_allocated);
674 map_Div->kind = INTRINSIC_INSTR;
675 map_Div->op = op_Div;
676 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
677 map_Div->ctx = &rt_uDiv;
679 /* ... nor a signed mod instruction ... */
681 i_instr_record *map_Mod = &records[n_records++].i_instr;
683 tp = new_type_method(ID("rt_iMod"), 2, 1);
684 set_method_param_type(tp, 0, int_tp);
685 set_method_param_type(tp, 1, int_tp);
686 set_method_res_type(tp, 0, int_tp);
688 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
689 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
690 rt_iMod.mode = mode_T;
691 rt_iMod.res_mode = mode_Is;
692 rt_iMod.mem_proj_nr = pn_Mod_M;
693 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
694 rt_iMod.exc_proj_nr = pn_Mod_X_except;
695 rt_iMod.exc_mem_proj_nr = pn_Mod_M;
696 rt_iMod.res_proj_nr = pn_Mod_res;
698 set_entity_visibility(rt_iMod.ent, visibility_external_allocated);
700 map_Mod->kind = INTRINSIC_INSTR;
701 map_Mod->op = op_Mod;
702 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
703 map_Mod->ctx = &rt_iMod;
705 /* ... nor an unsigned mod. */
707 i_instr_record *map_Mod = &records[n_records++].i_instr;
709 tp = new_type_method(ID("rt_uMod"), 2, 1);
710 set_method_param_type(tp, 0, uint_tp);
711 set_method_param_type(tp, 1, uint_tp);
712 set_method_res_type(tp, 0, uint_tp);
714 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
715 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
716 rt_uMod.mode = mode_T;
717 rt_uMod.res_mode = mode_Iu;
718 rt_uMod.mem_proj_nr = pn_Mod_M;
719 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
720 rt_uMod.exc_proj_nr = pn_Mod_X_except;
721 rt_uMod.exc_mem_proj_nr = pn_Mod_M;
722 rt_uMod.res_proj_nr = pn_Mod_res;
724 set_entity_visibility(rt_uMod.ent, visibility_external_allocated);
726 map_Mod->kind = INTRINSIC_INSTR;
727 map_Mod->op = op_Mod;
728 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
729 map_Mod->ctx = &rt_uMod;
733 lower_intrinsics(records, n_records, /*part_block_used=*/0);
736 /*****************************************************************
737 * ____ _ _ _____ _____
738 * | _ \ | | | | |_ _|/ ____| /\
739 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
740 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
741 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
742 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
744 *****************************************************************/
746 static arm_isa_t arm_isa_template = {
748 &arm_isa_if, /* isa interface */
749 &arm_gp_regs[REG_SP], /* stack pointer */
750 &arm_gp_regs[REG_R11], /* base pointer */
751 -1, /* stack direction */
752 2, /* power of two stack alignment for calls, 2^2 == 4 */
753 NULL, /* main environment */
755 5, /* reload costs */
757 0, /* use generic register names instead of SP, LR, PC */
758 ARM_FPU_ARCH_FPE, /* FPU architecture */
759 NULL, /* current code generator */
763 * Initializes the backend ISA and opens the output file.
765 static arch_env_t *arm_init(FILE *file_handle) {
766 static int inited = 0;
772 isa = xmalloc(sizeof(*isa));
773 memcpy(isa, &arm_isa_template, sizeof(*isa));
778 be_emit_init(file_handle);
780 arm_create_opcodes(&arm_irn_ops);
781 arm_handle_intrinsics();
783 /* we mark referenced global entities, so we can only emit those which
784 * are actually referenced. (Note: you mustn't use the type visited flag
785 * elsewhere in the backend)
787 inc_master_type_visited();
790 return &isa->arch_env;
796 * Closes the output file and frees the ISA structure.
798 static void arm_done(void *self) {
799 arm_isa_t *isa = self;
801 be_gas_emit_decls(isa->arch_env.main_env, 1);
809 * Report the number of register classes.
810 * If we don't have fp instructions, report only GP
811 * here to speed up register allocation (and makes dumps
812 * smaller and more readable).
814 static unsigned arm_get_n_reg_class(const void *self) {
820 * Return the register class with requested index.
822 static const arch_register_class_t *arm_get_reg_class(const void *self,
825 assert(i < N_CLASSES);
826 return &arm_reg_classes[i];
830 * Get the register class which shall be used to store a value of a given mode.
831 * @param self The this pointer.
832 * @param mode The mode in question.
833 * @return A register class which can hold values of the given mode.
835 const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
837 if (mode_is_float(mode))
838 return &arm_reg_classes[CLASS_arm_fpa];
840 return &arm_reg_classes[CLASS_arm_gp];
844 * Produces the type which sits between the stack args and the locals on the stack.
845 * it will contain the return address and space to store the old base pointer.
846 * @return The Firm type modeling the ABI between type.
848 static ir_type *arm_get_between_type(void *self) {
849 static ir_type *between_type = NULL;
850 static ir_entity *old_bp_ent = NULL;
853 if (between_type == NULL) {
854 ir_entity *ret_addr_ent;
855 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
856 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
858 between_type = new_type_class(new_id_from_str("arm_between_type"));
859 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
860 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
862 set_entity_offset(old_bp_ent, 0);
863 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
864 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
872 be_abi_call_flags_bits_t flags;
873 const arch_env_t *arch_env;
877 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
879 arm_abi_env_t *env = xmalloc(sizeof(env[0]));
880 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
881 env->flags = fl.bits;
883 env->arch_env = arch_env;
887 static void arm_abi_dont_save_regs(void *self, pset *s)
889 arm_abi_env_t *env = self;
890 if (env->flags.try_omit_fp)
891 pset_insert_ptr(s, env->arch_env->bp);
897 * Build the ARM prolog
899 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
900 ir_node *keep, *store;
901 arm_abi_env_t *env = self;
902 ir_graph *irg = env->irg;
903 ir_node *block = get_irg_start_block(irg);
904 arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
906 ir_node *fp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
907 ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
908 ir_node *sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
909 ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
910 ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
912 if (env->flags.try_omit_fp)
913 return env->arch_env->sp;
915 ip = be_new_Copy(gp, irg, block, sp);
916 arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
917 be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
919 store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
921 sp = new_r_Proj(irg, block, store, env->arch_env->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
922 arch_set_irn_register(env->arch_env, sp, env->arch_env->sp);
923 *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
925 keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
926 be_node_set_reg_class(keep, 1, gp);
927 arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
928 be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
930 fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp), 4);
931 arch_set_irn_register(env->arch_env, fp, env->arch_env->bp);
932 fp = be_new_Copy(gp, irg, block, fp); // XXX Gammelfix: only be_ nodes can have the ignore flag set
933 arch_set_irn_register(env->arch_env, fp, env->arch_env->bp);
934 be_node_set_flags(fp, BE_OUT_POS(0), arch_irn_flags_ignore);
936 be_abi_reg_map_set(reg_map, env->arch_env->bp, fp);
937 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
938 be_abi_reg_map_set(reg_map, env->arch_env->sp, sp);
939 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
940 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
942 return env->arch_env->bp;
946 * Builds the ARM epilogue
948 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
949 arm_abi_env_t *env = self;
950 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
951 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
952 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
953 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
955 // TODO: Activate Omit fp in epilogue
956 if (env->flags.try_omit_fp) {
957 curr_sp = be_new_IncSP(env->arch_env->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
958 add_irn_dep(curr_sp, *mem);
960 curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
961 be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
962 arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
963 be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
965 curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
966 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
967 be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
968 be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
972 sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, 12);
974 //set_arm_req_out_all(sub12_node, sub12_req);
975 arch_set_irn_register(env->arch_env, sub12_node, env->arch_env->sp);
976 load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
978 //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
979 //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
980 //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
981 curr_bp = new_r_Proj(env->irg, bl, load_node, env->arch_env->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
982 curr_sp = new_r_Proj(env->irg, bl, load_node, env->arch_env->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
983 curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
984 *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
985 arch_set_irn_register(env->arch_env, curr_bp, env->arch_env->bp);
986 arch_set_irn_register(env->arch_env, curr_sp, env->arch_env->sp);
987 arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
989 be_abi_reg_map_set(reg_map, env->arch_env->sp, curr_sp);
990 be_abi_reg_map_set(reg_map, env->arch_env->bp, curr_bp);
991 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
992 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
995 static const be_abi_callbacks_t arm_abi_callbacks = {
998 arm_get_between_type,
999 arm_abi_dont_save_regs,
1006 * Get the ABI restrictions for procedure calls.
1007 * @param self The this pointer.
1008 * @param method_type The type of the method (procedure) in question.
1009 * @param abi The abi object to be modified
1011 void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1015 int n = get_method_n_params(method_type);
1016 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1019 /* set abi flags for calls */
1020 call_flags.bits.left_to_right = 0;
1021 call_flags.bits.store_args_sequential = 0;
1022 /* call_flags.bits.try_omit_fp don't change this we can handle both */
1023 call_flags.bits.fp_free = 0;
1024 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1026 /* set stack parameter passing style */
1027 be_abi_call_set_flags(abi, call_flags, &arm_abi_callbacks);
1029 for (i = 0; i < n; i++) {
1030 /* reg = get reg for param i; */
1031 /* be_abi_call_param_reg(abi, i, reg); */
1033 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
1035 tp = get_method_param_type(method_type, i);
1036 mode = get_type_mode(tp);
1037 be_abi_call_param_stack(abi, i, mode, 4, 0, 0);
1041 /* set return registers */
1042 n = get_method_n_ress(method_type);
1044 assert(n <= 2 && "more than two results not supported");
1046 /* In case of 64bit returns, we will have two 32bit values */
1048 tp = get_method_res_type(method_type, 0);
1049 mode = get_type_mode(tp);
1051 assert(!mode_is_float(mode) && "two FP results not supported");
1053 tp = get_method_res_type(method_type, 1);
1054 mode = get_type_mode(tp);
1056 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1058 be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0]);
1059 be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1]);
1060 } else if (n == 1) {
1061 const arch_register_t *reg;
1063 tp = get_method_res_type(method_type, 0);
1064 assert(is_atomic_type(tp));
1065 mode = get_type_mode(tp);
1067 reg = mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0];
1068 be_abi_call_res_reg(abi, 0, reg);
1072 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1074 if(!is_arm_irn(irn))
1081 * Initializes the code generator interface.
1083 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
1085 return &arm_code_gen_if;
1088 list_sched_selector_t arm_sched_selector;
1091 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1093 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1095 memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
1096 /* arm_sched_selector.exectime = arm_sched_exectime; */
1097 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1098 return &arm_sched_selector;
1102 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
1108 * Returns the necessary byte alignment for storing a register of given class.
1110 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1113 /* ARM is a 32 bit CPU, no need for other alignment */
1117 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
1125 static const be_machine_t *arm_get_machine(const void *self) {
1133 * Return irp irgs in the desired order.
1135 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
1142 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1143 * @return 1 if allowed, 0 otherwise
1145 static int arm_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) {
1146 ir_node *cmp, *cmp_a, *phi;
1150 /* currently Psi support is not implemented */
1153 /* we don't want long long Psi */
1154 #define IS_BAD_PSI_MODE(mode) (!mode_is_float(mode) && get_mode_size_bits(mode) > 32)
1156 if (get_irn_mode(sel) != mode_b)
1159 cmp = get_Proj_pred(sel);
1160 cmp_a = get_Cmp_left(cmp);
1161 mode = get_irn_mode(cmp_a);
1163 if (IS_BAD_PSI_MODE(mode))
1166 /* check the Phi nodes */
1167 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1168 ir_node *pred_i = get_irn_n(phi, i);
1169 ir_node *pred_j = get_irn_n(phi, j);
1170 ir_mode *mode_i = get_irn_mode(pred_i);
1171 ir_mode *mode_j = get_irn_mode(pred_j);
1173 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1177 #undef IS_BAD_PSI_MODE
1183 * Returns the libFirm configuration parameter for this backend.
1185 static const backend_params *arm_get_libfirm_params(void) {
1186 static const ir_settings_if_conv_t ifconv = {
1187 4, /* maxdepth, doesn't matter for Psi-conversion */
1188 arm_is_psi_allowed /* allows or disallows Psi creation for given selector */
1190 static ir_settings_arch_dep_t ad = {
1192 1, /* Muls are fast enough on ARM but ... */
1193 31, /* ... one shift would be possible better */
1194 NULL, /* no evaluator function */
1195 0, /* SMUL is needed, only in Arch M */
1196 0, /* UMUL is needed, only in Arch M */
1197 32, /* SMUL & UMUL available for 32 bit */
1199 static backend_params p = {
1200 1, /* need dword lowering */
1201 0, /* don't support inline assembler yet */
1202 0, /* no immediate floating point mode. */
1203 NULL, /* no additional opcodes */
1204 NULL, /* will be set later */
1205 NULL, /* but yet no creator function */
1206 NULL, /* context for create_intrinsic_fkt */
1207 NULL, /* will be set below */
1208 NULL /* no immediate fp mode */
1212 p.if_conv_info = &ifconv;
1216 /* fpu set architectures. */
1217 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1218 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1219 { "fpe", ARM_FPU_ARCH_FPE },
1220 { "fpa", ARM_FPU_ARCH_FPA },
1221 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1222 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1223 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1227 static lc_opt_enum_int_var_t arch_fpu_var = {
1228 &arm_isa_template.fpu_arch, arm_fpu_items
1231 static const lc_opt_table_entry_t arm_options[] = {
1232 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1233 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1237 const arch_isa_if_t arm_isa_if = {
1240 arm_get_n_reg_class,
1242 arm_get_reg_class_for_mode,
1244 arm_get_code_generator_if,
1245 arm_get_list_sched_selector,
1246 arm_get_ilp_sched_selector,
1247 arm_get_reg_class_alignment,
1248 arm_get_libfirm_params,
1249 arm_get_allowed_execution_units,
1254 void be_init_arch_arm(void)
1256 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1257 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1259 lc_opt_add_table(arm_grp, arm_options);
1261 be_register_isa_if("arm", &arm_isa_if);
1263 arm_init_transform();
1267 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);