2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main arm backend driver file.
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist
29 #include "lc_opts_enum.h"
31 #include "pseudo_irg.h"
38 #include "iroptimize.h"
48 #include "../bearch.h"
49 #include "../benode.h"
50 #include "../belower.h"
51 #include "../besched.h"
54 #include "../bemachine.h"
55 #include "../beilpsched.h"
56 #include "../bemodule.h"
58 #include "../bespillslots.h"
59 #include "../begnuas.h"
60 #include "../belistsched.h"
61 #include "../beflags.h"
63 #include "bearch_arm_t.h"
65 #include "arm_new_nodes.h"
66 #include "gen_arm_regalloc_if.h"
67 #include "arm_transform.h"
68 #include "arm_optimize.h"
69 #include "arm_emitter.h"
70 #include "arm_map_regs.h"
72 static arch_irn_class_t arm_classify(const ir_node *irn)
78 static ir_entity *arm_get_frame_entity(const ir_node *irn)
80 const arm_attr_t *attr = get_arm_attr_const(irn);
82 if (is_arm_FrameAddr(irn)) {
83 const arm_SymConst_attr_t *attr = get_irn_generic_attr_const(irn);
86 if (attr->is_load_store) {
87 const arm_load_store_attr_t *load_store_attr
88 = get_arm_load_store_attr_const(irn);
89 if (load_store_attr->is_frame_entity) {
90 return load_store_attr->entity;
96 static void arm_set_frame_entity(ir_node *irn, ir_entity *ent)
100 panic("arm_set_frame_entity() called. This should not happen.");
104 * This function is called by the generic backend to correct offsets for
105 * nodes accessing the stack.
107 static void arm_set_stack_bias(ir_node *irn, int bias)
109 if (is_arm_FrameAddr(irn)) {
110 arm_SymConst_attr_t *attr = get_irn_generic_attr(irn);
111 attr->fp_offset += bias;
113 arm_load_store_attr_t *attr = get_arm_load_store_attr(irn);
114 assert(attr->base.is_load_store);
115 attr->offset += bias;
119 static int arm_get_sp_bias(const ir_node *irn)
121 /* We don't have any nodes changing the stack pointer.
122 TODO: we probably want to support post-/pre increment/decrement later */
127 /* fill register allocator interface */
129 static const arch_irn_ops_t arm_irn_ops = {
132 arm_get_frame_entity,
133 arm_set_frame_entity,
136 NULL, /* get_inverse */
137 NULL, /* get_op_estimated_cost */
138 NULL, /* possible_memory_operand */
139 NULL, /* perform_memory_operand */
143 * Transforms the standard Firm graph into
146 static void arm_prepare_graph(void *self)
148 arm_code_gen_t *cg = self;
150 /* transform nodes into assembler instructions */
151 arm_transform_graph(cg);
153 /* do local optimizations (mainly CSE) */
154 local_optimize_graph(cg->irg);
157 dump_ir_graph(cg->irg, "transformed");
159 /* do code placement, to optimize the position of constants */
163 dump_ir_graph(cg->irg, "place");
167 * Called immediately before emit phase.
169 static void arm_finish_irg(void *self)
171 arm_code_gen_t *cg = self;
173 /* do peephole optimizations and fix stack offsets */
174 arm_peephole_optimization(cg);
177 static ir_node *arm_flags_remat(ir_node *node, ir_node *after)
182 if (is_Block(after)) {
185 block = get_nodes_block(after);
187 copy = exact_copy(node);
188 set_nodes_block(copy, block);
189 sched_add_after(after, copy);
193 static void arm_before_ra(void *self)
195 arm_code_gen_t *cg = self;
197 be_sched_fix_flags(cg->irg, &arm_reg_classes[CLASS_arm_flags],
201 static void transform_Reload(ir_node *node)
203 ir_graph *irg = get_irn_irg(node);
204 ir_node *block = get_nodes_block(node);
205 dbg_info *dbgi = get_irn_dbg_info(node);
206 ir_node *ptr = get_irg_frame(irg);
207 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
208 ir_mode *mode = get_irn_mode(node);
209 ir_entity *entity = be_get_frame_entity(node);
210 const arch_register_t *reg;
214 ir_node *sched_point = sched_prev(node);
216 load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true);
217 sched_add_after(sched_point, load);
220 proj = new_rd_Proj(dbgi, load, mode, pn_arm_Ldr_res);
222 reg = arch_get_irn_register(node);
223 arch_set_irn_register(proj, reg);
225 exchange(node, proj);
228 static void transform_Spill(ir_node *node)
230 ir_graph *irg = get_irn_irg(node);
231 ir_node *block = get_nodes_block(node);
232 dbg_info *dbgi = get_irn_dbg_info(node);
233 ir_node *ptr = get_irg_frame(irg);
234 ir_node *mem = new_NoMem();
235 ir_node *val = get_irn_n(node, be_pos_Spill_val);
236 ir_mode *mode = get_irn_mode(val);
237 ir_entity *entity = be_get_frame_entity(node);
238 ir_node *sched_point;
241 sched_point = sched_prev(node);
242 store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0,
246 sched_add_after(sched_point, store);
248 exchange(node, store);
251 static void arm_after_ra_walker(ir_node *block, void *data)
253 ir_node *node, *prev;
256 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
257 prev = sched_prev(node);
259 if (be_is_Reload(node)) {
260 transform_Reload(node);
261 } else if (be_is_Spill(node)) {
262 transform_Spill(node);
267 static void arm_after_ra(void *self)
269 arm_code_gen_t *cg = self;
270 be_coalesce_spillslots(cg->irg);
272 irg_block_walk_graph(cg->irg, NULL, arm_after_ra_walker, NULL);
276 * Emits the code, closes the output file and frees
277 * the code generator interface.
279 static void arm_emit_and_done(void *self)
281 arm_code_gen_t *cg = self;
282 ir_graph *irg = cg->irg;
284 arm_gen_routine(cg, irg);
286 /* de-allocate code generator */
287 del_set(cg->reg_set);
292 * Move a double floating point value into an integer register.
293 * Place the move operation into block bl.
295 * Handle some special cases here:
296 * 1.) A constant: simply split into two
297 * 2.) A load: simply split into two
299 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
300 ir_node **resH, ir_node **resL)
303 tarval *tv = get_Const_tarval(arg);
306 /* get the upper 32 bits */
307 v = get_tarval_sub_bits(tv, 7);
308 v = (v << 8) | get_tarval_sub_bits(tv, 6);
309 v = (v << 8) | get_tarval_sub_bits(tv, 5);
310 v = (v << 8) | get_tarval_sub_bits(tv, 4);
311 *resH = new_Const_long(mode_Is, v);
313 /* get the lower 32 bits */
314 v = get_tarval_sub_bits(tv, 3);
315 v = (v << 8) | get_tarval_sub_bits(tv, 2);
316 v = (v << 8) | get_tarval_sub_bits(tv, 1);
317 v = (v << 8) | get_tarval_sub_bits(tv, 0);
318 *resL = new_Const_long(mode_Is, v);
319 } else if (is_Load(skip_Proj(arg))) {
320 /* FIXME: handling of low/high depends on LE/BE here */
321 panic("Unimplemented convert_dbl_to_int() case");
326 conv = new_bd_arm_fpaDbl2GP(NULL, bl, arg, mem);
328 *resL = new_r_Proj(conv, mode_Is, pn_arm_fpaDbl2GP_low);
329 *resH = new_r_Proj(conv, mode_Is, pn_arm_fpaDbl2GP_high);
330 mem = new_r_Proj(conv, mode_M, pn_arm_fpaDbl2GP_M);
336 * Move a single floating point value into an integer register.
337 * Place the move operation into block bl.
339 * Handle some special cases here:
340 * 1.) A constant: simply move
341 * 2.) A load: simply load
343 static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg)
348 tarval *tv = get_Const_tarval(arg);
351 /* get the lower 32 bits */
352 v = get_tarval_sub_bits(tv, 3);
353 v = (v << 8) | get_tarval_sub_bits(tv, 2);
354 v = (v << 8) | get_tarval_sub_bits(tv, 1);
355 v = (v << 8) | get_tarval_sub_bits(tv, 0);
356 return new_Const_long(mode_Is, v);
358 panic("Unimplemented convert_sng_to_int() case");
362 * Convert the arguments of a call to support the
363 * ARM calling convention of general purpose AND floating
366 static void handle_calls(ir_node *call, void *env)
368 arm_code_gen_t *cg = env;
369 int i, j, n, size, idx, flag, n_param, n_res, first_variadic;
370 ir_type *mtp, *new_mtd, *new_tp[5];
371 ir_node *new_in[5], **in;
377 /* check, if we need conversions */
378 n = get_Call_n_params(call);
379 mtp = get_Call_type(call);
380 assert(get_method_n_params(mtp) == n);
382 /* it's always enough to handle the first 4 parameters */
385 flag = size = idx = 0;
386 bl = get_nodes_block(call);
387 for (i = 0; i < n; ++i) {
388 ir_type *param_tp = get_method_param_type(mtp, i);
390 if (is_compound_type(param_tp)) {
391 /* an aggregate parameter: bad case */
395 /* a primitive parameter */
396 ir_mode *mode = get_type_mode(param_tp);
398 if (mode_is_float(mode)) {
399 if (get_mode_size_bits(mode) > 32) {
400 ir_node *mem = get_Call_mem(call);
402 /* Beware: ARM wants the high part first */
404 new_tp[idx] = cg->int_tp;
405 new_tp[idx+1] = cg->int_tp;
406 mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
408 set_Call_mem(call, mem);
412 new_tp[idx] = cg->int_tp;
413 new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
420 new_tp[idx] = param_tp;
421 new_in[idx] = get_Call_param(call, i);
430 /* if flag is NOT set, no need to translate the method type */
434 /* construct a new method type */
436 n_param = get_method_n_params(mtp) - n + idx;
437 n_res = get_method_n_ress(mtp);
438 new_mtd = new_d_type_method(n_param, n_res, get_type_dbg_info(mtp));
440 for (i = 0; i < idx; ++i)
441 set_method_param_type(new_mtd, i, new_tp[i]);
442 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
443 set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
444 for (i = 0; i < n_res; ++i)
445 set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
447 set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
448 first_variadic = get_method_first_variadic_param_index(mtp);
449 if (first_variadic >= 0)
450 set_method_first_variadic_param_index(new_mtd, first_variadic);
452 if (is_lowered_type(mtp)) {
453 mtp = get_associated_type(mtp);
455 set_lowered_type(mtp, new_mtd);
457 set_Call_type(call, new_mtd);
459 /* calculate new in array of the Call */
460 NEW_ARR_A(ir_node *, in, n_param + 2);
461 for (i = 0; i < idx; ++i)
462 in[2 + i] = new_in[i];
463 for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
464 in[2 + j++] = get_Call_param(call, i);
466 in[0] = get_Call_mem(call);
467 in[1] = get_Call_ptr(call);
469 /* finally, change the call inputs */
470 set_irn_in(call, n_param + 2, in);
474 * Handle graph transformations before the abi converter does its work.
476 static void arm_before_abi(void *self)
478 arm_code_gen_t *cg = self;
480 irg_walk_graph(cg->irg, NULL, handle_calls, cg);
484 static void *arm_cg_init(ir_graph *irg);
486 static const arch_code_generator_if_t arm_code_gen_if = {
488 NULL, /* get_pic_base */
489 arm_before_abi, /* before abi introduce */
492 arm_before_ra, /* before register allocation hook */
499 * Initializes the code generator.
501 static void *arm_cg_init(ir_graph *irg)
503 static ir_type *int_tp = NULL;
504 arm_isa_t *isa = (arm_isa_t *) be_get_irg_arch_env(irg);
508 /* create an integer type with machine size */
509 int_tp = new_type_primitive(mode_Is);
512 cg = XMALLOC(arm_code_gen_t);
513 cg->impl = &arm_code_gen_if;
515 cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
518 cg->have_fp_insn = 0;
519 cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
521 FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
523 /* enter the current code generator */
526 return (arch_code_generator_t *)cg;
531 * Maps all intrinsic calls that the backend support
532 * and map all instructions the backend did not support
535 static void arm_handle_intrinsics(void)
537 ir_type *tp, *int_tp, *uint_tp;
541 runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
543 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
545 int_tp = new_type_primitive(mode_Is);
546 uint_tp = new_type_primitive(mode_Iu);
548 /* ARM has neither a signed div instruction ... */
550 i_instr_record *map_Div = &records[n_records++].i_instr;
552 tp = new_type_method(2, 1);
553 set_method_param_type(tp, 0, int_tp);
554 set_method_param_type(tp, 1, int_tp);
555 set_method_res_type(tp, 0, int_tp);
557 rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
558 set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
559 rt_iDiv.mode = mode_T;
560 rt_iDiv.res_mode = mode_Is;
561 rt_iDiv.mem_proj_nr = pn_Div_M;
562 rt_iDiv.regular_proj_nr = pn_Div_X_regular;
563 rt_iDiv.exc_proj_nr = pn_Div_X_except;
564 rt_iDiv.exc_mem_proj_nr = pn_Div_M;
565 rt_iDiv.res_proj_nr = pn_Div_res;
567 add_entity_linkage(rt_iDiv.ent, IR_LINKAGE_CONSTANT);
568 set_entity_visibility(rt_iDiv.ent, ir_visibility_external);
570 map_Div->kind = INTRINSIC_INSTR;
571 map_Div->op = op_Div;
572 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
573 map_Div->ctx = &rt_iDiv;
575 /* ... nor an unsigned div instruction ... */
577 i_instr_record *map_Div = &records[n_records++].i_instr;
579 tp = new_type_method(2, 1);
580 set_method_param_type(tp, 0, uint_tp);
581 set_method_param_type(tp, 1, uint_tp);
582 set_method_res_type(tp, 0, uint_tp);
584 rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
585 set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
586 rt_uDiv.mode = mode_T;
587 rt_uDiv.res_mode = mode_Iu;
588 rt_uDiv.mem_proj_nr = pn_Div_M;
589 rt_uDiv.regular_proj_nr = pn_Div_X_regular;
590 rt_uDiv.exc_proj_nr = pn_Div_X_except;
591 rt_uDiv.exc_mem_proj_nr = pn_Div_M;
592 rt_uDiv.res_proj_nr = pn_Div_res;
594 set_entity_visibility(rt_uDiv.ent, ir_visibility_external);
596 map_Div->kind = INTRINSIC_INSTR;
597 map_Div->op = op_Div;
598 map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
599 map_Div->ctx = &rt_uDiv;
601 /* ... nor a signed mod instruction ... */
603 i_instr_record *map_Mod = &records[n_records++].i_instr;
605 tp = new_type_method(2, 1);
606 set_method_param_type(tp, 0, int_tp);
607 set_method_param_type(tp, 1, int_tp);
608 set_method_res_type(tp, 0, int_tp);
610 rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
611 set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
612 rt_iMod.mode = mode_T;
613 rt_iMod.res_mode = mode_Is;
614 rt_iMod.mem_proj_nr = pn_Mod_M;
615 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
616 rt_iMod.exc_proj_nr = pn_Mod_X_except;
617 rt_iMod.exc_mem_proj_nr = pn_Mod_M;
618 rt_iMod.res_proj_nr = pn_Mod_res;
620 set_entity_visibility(rt_iMod.ent, ir_visibility_external);
622 map_Mod->kind = INTRINSIC_INSTR;
623 map_Mod->op = op_Mod;
624 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
625 map_Mod->ctx = &rt_iMod;
627 /* ... nor an unsigned mod. */
629 i_instr_record *map_Mod = &records[n_records++].i_instr;
631 tp = new_type_method(2, 1);
632 set_method_param_type(tp, 0, uint_tp);
633 set_method_param_type(tp, 1, uint_tp);
634 set_method_res_type(tp, 0, uint_tp);
636 rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
637 set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
638 rt_uMod.mode = mode_T;
639 rt_uMod.res_mode = mode_Iu;
640 rt_uMod.mem_proj_nr = pn_Mod_M;
641 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
642 rt_uMod.exc_proj_nr = pn_Mod_X_except;
643 rt_uMod.exc_mem_proj_nr = pn_Mod_M;
644 rt_uMod.res_proj_nr = pn_Mod_res;
646 set_entity_visibility(rt_uMod.ent, ir_visibility_external);
648 map_Mod->kind = INTRINSIC_INSTR;
649 map_Mod->op = op_Mod;
650 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
651 map_Mod->ctx = &rt_uMod;
655 lower_intrinsics(records, n_records, /*part_block_used=*/0);
659 static arm_isa_t arm_isa_template = {
661 &arm_isa_if, /* isa interface */
662 &arm_gp_regs[REG_SP], /* stack pointer */
663 &arm_gp_regs[REG_R11], /* base pointer */
664 &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */
665 -1, /* stack direction */
666 2, /* power of two stack alignment for calls, 2^2 == 4 */
667 NULL, /* main environment */
669 5, /* reload costs */
670 false, /* no custom abi handling */
672 0, /* use generic register names instead of SP, LR, PC */
673 ARM_FPU_ARCH_FPE, /* FPU architecture */
674 NULL, /* current code generator */
678 * Initializes the backend ISA and opens the output file.
680 static arch_env_t *arm_init(FILE *file_handle)
682 static int inited = 0;
688 isa = XMALLOC(arm_isa_t);
689 memcpy(isa, &arm_isa_template, sizeof(*isa));
694 be_emit_init(file_handle);
696 arm_create_opcodes(&arm_irn_ops);
697 arm_handle_intrinsics();
699 be_gas_emit_types = false;
701 /* needed for the debug support */
702 be_gas_emit_switch_section(GAS_SECTION_TEXT);
703 be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
704 be_emit_write_line();
707 return &isa->arch_env;
713 * Closes the output file and frees the ISA structure.
715 static void arm_done(void *self)
717 arm_isa_t *isa = self;
719 be_gas_emit_decls(isa->arch_env.main_env);
727 * Report the number of register classes.
728 * If we don't have fp instructions, report only GP
729 * here to speed up register allocation (and makes dumps
730 * smaller and more readable).
732 static unsigned arm_get_n_reg_class(void)
738 * Return the register class with requested index.
740 static const arch_register_class_t *arm_get_reg_class(unsigned i)
742 assert(i < N_CLASSES);
743 return &arm_reg_classes[i];
747 * Get the register class which shall be used to store a value of a given mode.
748 * @param self The this pointer.
749 * @param mode The mode in question.
750 * @return A register class which can hold values of the given mode.
752 static const arch_register_class_t *arm_get_reg_class_for_mode(const ir_mode *mode)
754 if (mode_is_float(mode))
755 return &arm_reg_classes[CLASS_arm_fpa];
757 return &arm_reg_classes[CLASS_arm_gp];
761 * Produces the type which sits between the stack args and the locals on the stack.
762 * it will contain the return address and space to store the old base pointer.
763 * @return The Firm type modeling the ABI between type.
765 static ir_type *arm_get_between_type(void *self)
767 static ir_type *between_type = NULL;
770 if (between_type == NULL) {
771 between_type = new_type_class(new_id_from_str("arm_between_type"));
772 set_type_size_bytes(between_type, 0);
780 be_abi_call_flags_bits_t flags;
781 const arch_env_t *arch_env;
785 static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
787 arm_abi_env_t *env = XMALLOC(arm_abi_env_t);
788 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
789 env->flags = fl.bits;
791 env->arch_env = arch_env;
796 * Generate the routine prologue.
798 * @param self The callback object.
799 * @param mem A pointer to the mem node. Update this if you define new memory.
800 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
801 * @param stack_bias Points to the current stack bias, can be modified if needed.
803 * @return The register which shall be used as a stack frame base.
805 * All nodes which define registers in @p reg_map must keep @p reg_map current.
807 static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
809 arm_abi_env_t *env = self;
813 arch_register_class_t *gp;
815 ir_node *fp, *ip, *lr, *pc;
816 ir_node *sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
820 if (env->flags.try_omit_fp)
821 return env->arch_env->sp;
823 fp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
824 ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
825 lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
826 pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
828 gp = &arm_reg_classes[CLASS_arm_gp];
830 block = get_irg_start_block(irg);
832 /* mark bp register as ignore */
833 be_set_constr_single_reg_out(get_Proj_pred(fp),
834 get_Proj_proj(fp), env->arch_env->bp,
835 arch_register_req_type_ignore);
837 /* copy SP to IP (so we can spill it */
838 ip = be_new_Copy(gp, block, sp);
839 be_set_constr_single_reg_out(ip, 0, &arm_gp_regs[REG_R12], 0);
842 store = new_bd_arm_StoreStackM4Inc(NULL, block, sp, fp, ip, lr, pc, *mem);
844 sp = new_r_Proj(store, env->arch_env->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
845 arch_set_irn_register(sp, env->arch_env->sp);
846 *mem = new_r_Proj(store, mode_M, pn_arm_StoreStackM4Inc_M);
848 /* frame pointer is ip-4 (because ip is our old sp value) */
849 fp = new_bd_arm_Sub_imm(NULL, block, ip, 4, 0);
850 arch_set_irn_register(fp, env->arch_env->bp);
852 /* beware: we change the fp but the StoreStackM4Inc above wants the old
853 * fp value. We are not allowed to spill or anything in the prolog, so we
854 * have to enforce some order here. (scheduler/regalloc are too stupid
855 * to extract this order from register requirements) */
856 add_irn_dep(fp, store);
858 fp = be_new_Copy(gp, block, fp); // XXX Gammelfix: only be_ have custom register requirements
859 be_set_constr_single_reg_out(fp, 0, env->arch_env->bp,
860 arch_register_req_type_ignore);
861 arch_set_irn_register(fp, env->arch_env->bp);
863 be_abi_reg_map_set(reg_map, env->arch_env->bp, fp);
864 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], ip);
865 be_abi_reg_map_set(reg_map, env->arch_env->sp, sp);
866 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
867 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
869 return env->arch_env->bp;
873 * Builds the ARM epilogue
875 static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
877 arm_abi_env_t *env = self;
878 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
879 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
880 ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
881 ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
883 // TODO: Activate Omit fp in epilogue
884 if (env->flags.try_omit_fp) {
885 ir_node *incsp = be_new_IncSP(env->arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
890 load_node = new_bd_arm_LoadStackM3Epilogue(NULL, bl, curr_bp, *mem);
892 curr_bp = new_r_Proj(load_node, env->arch_env->bp->reg_class->mode, pn_arm_LoadStackM3Epilogue_res0);
893 curr_sp = new_r_Proj(load_node, env->arch_env->sp->reg_class->mode, pn_arm_LoadStackM3Epilogue_res1);
894 curr_pc = new_r_Proj(load_node, mode_Iu, pn_arm_LoadStackM3Epilogue_res2);
895 *mem = new_r_Proj(load_node, mode_M, pn_arm_LoadStackM3Epilogue_M);
896 arch_set_irn_register(curr_bp, env->arch_env->bp);
897 arch_set_irn_register(curr_sp, env->arch_env->sp);
898 arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]);
900 be_abi_reg_map_set(reg_map, env->arch_env->sp, curr_sp);
901 be_abi_reg_map_set(reg_map, env->arch_env->bp, curr_bp);
902 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
903 be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
906 static const be_abi_callbacks_t arm_abi_callbacks = {
909 arm_get_between_type,
916 * Get the ABI restrictions for procedure calls.
917 * @param self The this pointer.
918 * @param method_type The type of the method (procedure) in question.
919 * @param abi The abi object to be modified
921 static void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi)
926 int n = get_method_n_params(method_type);
927 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
930 /* set abi flags for calls */
931 call_flags.bits.left_to_right = 0;
932 call_flags.bits.store_args_sequential = 0;
933 /* call_flags.bits.try_omit_fp don't change this we can handle both */
934 call_flags.bits.fp_free = 0;
935 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
937 /* set stack parameter passing style */
938 be_abi_call_set_flags(abi, call_flags, &arm_abi_callbacks);
940 for (i = 0; i < n; i++) {
941 /* reg = get reg for param i; */
942 /* be_abi_call_param_reg(abi, i, reg); */
944 be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i), ABI_CONTEXT_BOTH);
946 tp = get_method_param_type(method_type, i);
947 mode = get_type_mode(tp);
948 be_abi_call_param_stack(abi, i, mode, 4, 0, 0, ABI_CONTEXT_BOTH);
952 /* set return registers */
953 n = get_method_n_ress(method_type);
955 assert(n <= 2 && "more than two results not supported");
957 /* In case of 64bit returns, we will have two 32bit values */
959 tp = get_method_res_type(method_type, 0);
960 mode = get_type_mode(tp);
962 assert(!mode_is_float(mode) && "two FP results not supported");
964 tp = get_method_res_type(method_type, 1);
965 mode = get_type_mode(tp);
967 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
969 be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0], ABI_CONTEXT_BOTH);
970 be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1], ABI_CONTEXT_BOTH);
972 const arch_register_t *reg;
974 tp = get_method_res_type(method_type, 0);
975 assert(is_atomic_type(tp));
976 mode = get_type_mode(tp);
978 reg = mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0];
979 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
983 static int arm_to_appear_in_schedule(void *block_env, const ir_node *irn)
986 if (!is_arm_irn(irn))
993 * Initializes the code generator interface.
995 static const arch_code_generator_if_t *arm_get_code_generator_if(void *self)
998 return &arm_code_gen_if;
1001 list_sched_selector_t arm_sched_selector;
1004 * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
1006 static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector)
1009 memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
1010 /* arm_sched_selector.exectime = arm_sched_exectime; */
1011 arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
1012 return &arm_sched_selector;
1016 static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self)
1023 * Returns the necessary byte alignment for storing a register of given class.
1025 static int arm_get_reg_class_alignment(const arch_register_class_t *cls)
1028 /* ARM is a 32 bit CPU, no need for other alignment */
1032 static const be_execution_unit_t ***arm_get_allowed_execution_units(const ir_node *irn)
1036 panic("Unimplemented arm_get_allowed_execution_units()");
1039 static const be_machine_t *arm_get_machine(const void *self)
1043 panic("Unimplemented arm_get_machine()");
1047 * Return irp irgs in the desired order.
1049 static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list)
1057 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1058 * @return 1 if allowed, 0 otherwise
1060 static int arm_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1070 static asm_constraint_flags_t arm_parse_asm_constraint(const char **c)
1072 /* asm not supported */
1074 return ASM_CONSTRAINT_FLAG_INVALID;
1077 static int arm_is_valid_clobber(const char *clobber)
1084 * Returns the libFirm configuration parameter for this backend.
1086 static const backend_params *arm_get_libfirm_params(void)
1088 static const ir_settings_if_conv_t ifconv = {
1089 4, /* maxdepth, doesn't matter for Psi-conversion */
1090 arm_is_mux_allowed /* allows or disallows Mux creation for given selector */
1092 static ir_settings_arch_dep_t ad = {
1094 1, /* Muls are fast enough on ARM but ... */
1095 31, /* ... one shift would be possible better */
1096 NULL, /* no evaluator function */
1097 0, /* SMUL is needed, only in Arch M */
1098 0, /* UMUL is needed, only in Arch M */
1099 32, /* SMUL & UMUL available for 32 bit */
1101 static backend_params p = {
1102 1, /* need dword lowering */
1103 0, /* don't support inline assembler yet */
1104 NULL, /* will be set later */
1105 NULL, /* but yet no creator function */
1106 NULL, /* context for create_intrinsic_fkt */
1107 NULL, /* ifconv_info will be set below */
1108 NULL, /* float arithmetic mode (TODO) */
1109 0, /* no trampoline support: size 0 */
1110 0, /* no trampoline support: align 0 */
1111 NULL, /* no trampoline support: no trampoline builder */
1112 4 /* alignment of stack parameter */
1116 p.if_conv_info = &ifconv;
1120 /* fpu set architectures. */
1121 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
1122 { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
1123 { "fpe", ARM_FPU_ARCH_FPE },
1124 { "fpa", ARM_FPU_ARCH_FPA },
1125 { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
1126 { "vfp1", ARM_FPU_ARCH_VFP_V1 },
1127 { "vfp2", ARM_FPU_ARCH_VFP_V2 },
1131 static lc_opt_enum_int_var_t arch_fpu_var = {
1132 &arm_isa_template.fpu_arch, arm_fpu_items
1135 static const lc_opt_table_entry_t arm_options[] = {
1136 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
1137 LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
1141 const arch_isa_if_t arm_isa_if = {
1144 NULL, /* handle_intrinsics */
1145 arm_get_n_reg_class,
1147 arm_get_reg_class_for_mode,
1149 arm_get_code_generator_if,
1150 arm_get_list_sched_selector,
1151 arm_get_ilp_sched_selector,
1152 arm_get_reg_class_alignment,
1153 arm_get_libfirm_params,
1154 arm_get_allowed_execution_units,
1157 NULL, /* mark remat */
1158 arm_parse_asm_constraint,
1159 arm_is_valid_clobber
1162 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);
1163 void be_init_arch_arm(void)
1165 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1166 lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
1168 lc_opt_add_table(arm_grp, arm_options);
1170 be_register_isa_if("arm", &arm_isa_if);
1172 arm_init_transform();