2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
41 #include "../benode.h"
43 #include "../beutil.h"
44 #include "../betranshlp.h"
45 #include "../beabihelper.h"
48 #include "bearch_arm_t.h"
49 #include "arm_nodes_attr.h"
50 #include "arm_transform.h"
51 #include "arm_optimize.h"
52 #include "arm_new_nodes.h"
53 #include "arm_map_regs.h"
54 #include "arm_cconv.h"
56 #include "gen_arm_regalloc_if.h"
60 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 /** hold the current code generator during transformation */
63 static arm_code_gen_t *env_cg;
65 static const arch_register_t *sp_reg = &arm_gp_regs[REG_SP];
66 static ir_mode *mode_gp;
67 static beabi_helper_env_t *abihelper;
68 static calling_convention_t *cconv = NULL;
70 static pmap *node_to_stack;
72 static bool mode_needs_gp_reg(ir_mode *mode)
74 return mode_is_int(mode) || mode_is_reference(mode);
78 * create firm graph for a constant
80 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
87 /* We only have 8 bit immediates. So we possibly have to combine several
88 * operations to construct the desired value.
90 * we can either create the value by adding bits to 0 or by removing bits
91 * from an register with all bits set. Try which alternative needs fewer
93 arm_gen_vals_from_word(value, &v);
94 arm_gen_vals_from_word(~value, &vn);
98 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
99 be_dep_on_frame(result);
101 for (cnt = 1; cnt < vn.ops; ++cnt) {
102 result = new_bd_arm_Bic_imm(dbgi, block, result,
103 vn.values[cnt], vn.rors[cnt]);
107 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
108 be_dep_on_frame(result);
110 for (cnt = 1; cnt < v.ops; ++cnt) {
111 result = new_bd_arm_Or_imm(dbgi, block, result,
112 v.values[cnt], v.rors[cnt]);
119 * Create a DAG constructing a given Const.
121 * @param irn a Firm const
123 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
125 tarval *tv = get_Const_tarval(irn);
126 ir_mode *mode = get_tarval_mode(tv);
129 if (mode_is_reference(mode)) {
130 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
131 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
132 tv = tarval_convert_to(tv, mode_Iu);
134 value = get_tarval_long(tv);
135 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
139 * Create an And that will zero out upper bits.
141 * @param dbgi debug info
142 * @param block the basic block
143 * @param op the original node
144 * param src_bits number of lower bits that will remain
146 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
150 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
151 } else if (src_bits == 16) {
152 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
153 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
156 panic("zero extension only supported for 8 and 16 bits");
161 * Generate code for a sign extension.
163 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
166 int shift_width = 32 - src_bits;
167 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
168 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
172 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
175 int bits = get_mode_size_bits(orig_mode);
179 if (mode_is_signed(orig_mode)) {
180 return gen_sign_extension(dbgi, block, op, bits);
182 return gen_zero_extension(dbgi, block, op, bits);
187 * returns true if it is assured, that the upper bits of a node are "clean"
188 * which means for a 16 or 8 bit value, that the upper bits in the register
189 * are 0 for unsigned and a copy of the last significant bit for signed
192 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
194 (void) transformed_node;
201 * Transforms a Conv node.
203 * @return The created ia32 Conv node
205 static ir_node *gen_Conv(ir_node *node)
207 ir_node *block = be_transform_node(get_nodes_block(node));
208 ir_node *op = get_Conv_op(node);
209 ir_node *new_op = be_transform_node(op);
210 ir_mode *src_mode = get_irn_mode(op);
211 ir_mode *dst_mode = get_irn_mode(node);
212 dbg_info *dbg = get_irn_dbg_info(node);
214 if (src_mode == dst_mode)
217 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
218 env_cg->have_fp_insn = 1;
220 if (USE_FPA(env_cg->isa)) {
221 if (mode_is_float(src_mode)) {
222 if (mode_is_float(dst_mode)) {
223 /* from float to float */
224 return new_bd_arm_fpaMvf(dbg, block, new_op, dst_mode);
226 /* from float to int */
227 return new_bd_arm_fpaFix(dbg, block, new_op, dst_mode);
230 /* from int to float */
231 return new_bd_arm_fpaFlt(dbg, block, new_op, dst_mode);
233 } else if (USE_VFP(env_cg->isa)) {
234 panic("VFP not supported yet");
236 panic("Softfloat not supported yet");
238 } else { /* complete in gp registers */
239 int src_bits = get_mode_size_bits(src_mode);
240 int dst_bits = get_mode_size_bits(dst_mode);
244 if (src_bits == dst_bits) {
245 /* kill unneccessary conv */
249 if (src_bits < dst_bits) {
257 if (upper_bits_clean(new_op, min_mode)) {
261 if (mode_is_signed(min_mode)) {
262 return gen_sign_extension(dbg, block, new_op, min_bits);
264 return gen_zero_extension(dbg, block, new_op, min_bits);
274 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
276 unsigned val, low_pos, high_pos;
281 val = get_tarval_long(get_Const_tarval(node));
293 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
295 So we determine the smallest even position with a bit set
296 and the highest even position with no bit set anymore.
297 If the difference between these 2 is <= 8, then we can encode the value
300 low_pos = ntz(val) & ~1u;
301 high_pos = (32-nlz(val)+1) & ~1u;
303 if (high_pos - low_pos <= 8) {
304 res->imm_8 = val >> low_pos;
305 res->rot = 32 - low_pos;
310 res->rot = 34 - high_pos;
311 val = val >> (32-res->rot) | val << (res->rot);
321 static bool is_downconv(const ir_node *node)
329 /* we only want to skip the conv when we're the only user
330 * (not optimal but for now...)
332 if (get_irn_n_edges(node) > 1)
335 src_mode = get_irn_mode(get_Conv_op(node));
336 dest_mode = get_irn_mode(node);
338 mode_needs_gp_reg(src_mode) &&
339 mode_needs_gp_reg(dest_mode) &&
340 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
343 static ir_node *arm_skip_downconv(ir_node *node)
345 while (is_downconv(node))
346 node = get_Conv_op(node);
352 MATCH_COMMUTATIVE = 1 << 0,
353 MATCH_SIZE_NEUTRAL = 1 << 1,
356 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
357 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
359 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
360 new_binop_reg_func new_reg, new_binop_imm_func new_imm)
362 ir_node *block = be_transform_node(get_nodes_block(node));
363 ir_node *op1 = get_binop_left(node);
365 ir_node *op2 = get_binop_right(node);
367 dbg_info *dbgi = get_irn_dbg_info(node);
370 if (flags & MATCH_SIZE_NEUTRAL) {
371 op1 = arm_skip_downconv(op1);
372 op2 = arm_skip_downconv(op2);
374 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
377 if (try_encode_as_immediate(op2, &imm)) {
378 ir_node *new_op1 = be_transform_node(op1);
379 return new_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
381 new_op2 = be_transform_node(op2);
382 if ((flags & MATCH_COMMUTATIVE) && try_encode_as_immediate(op1, &imm)) {
383 return new_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
385 new_op1 = be_transform_node(op1);
387 return new_reg(dbgi, block, new_op1, new_op2);
391 * Creates an ARM Add.
393 * @return the created arm Add node
395 static ir_node *gen_Add(ir_node *node)
397 ir_mode *mode = get_irn_mode(node);
399 if (mode_is_float(mode)) {
400 ir_node *block = be_transform_node(get_nodes_block(node));
401 ir_node *op1 = get_Add_left(node);
402 ir_node *op2 = get_Add_right(node);
403 dbg_info *dbgi = get_irn_dbg_info(node);
404 ir_node *new_op1 = be_transform_node(op1);
405 ir_node *new_op2 = be_transform_node(op2);
406 env_cg->have_fp_insn = 1;
407 if (USE_FPA(env_cg->isa)) {
409 if (is_arm_fpaMvf_i(new_op1))
410 return new_bd_arm_fpaAdf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1));
411 if (is_arm_fpaMvf_i(new_op2))
412 return new_bd_arm_fpaAdf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2));
414 return new_bd_arm_fpaAdf(dbgi, block, new_op1, new_op2, mode);
415 } else if (USE_VFP(env_cg->isa)) {
416 assert(mode != mode_E && "IEEE Extended FP not supported");
417 panic("VFP not supported yet");
419 panic("Softfloat not supported yet");
424 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
426 new_op2 = get_irn_n(new_op1, 1);
427 new_op1 = get_irn_n(new_op1, 0);
429 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
431 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
433 new_op1 = get_irn_n(new_op2, 0);
434 new_op2 = get_irn_n(new_op2, 1);
436 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
440 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
441 new_bd_arm_Add_reg, new_bd_arm_Add_imm);
446 * Creates an ARM Mul.
448 * @return the created arm Mul node
450 static ir_node *gen_Mul(ir_node *node)
452 ir_node *block = be_transform_node(get_nodes_block(node));
453 ir_node *op1 = get_Mul_left(node);
454 ir_node *new_op1 = be_transform_node(op1);
455 ir_node *op2 = get_Mul_right(node);
456 ir_node *new_op2 = be_transform_node(op2);
457 ir_mode *mode = get_irn_mode(node);
458 dbg_info *dbg = get_irn_dbg_info(node);
460 if (mode_is_float(mode)) {
461 env_cg->have_fp_insn = 1;
462 if (USE_FPA(env_cg->isa)) {
464 if (is_arm_Mov_i(new_op1))
465 return new_bd_arm_fpaMuf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
466 if (is_arm_Mov_i(new_op2))
467 return new_bd_arm_fpaMuf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
469 return new_bd_arm_fpaMuf(dbg, block, new_op1, new_op2, mode);
470 } else if (USE_VFP(env_cg->isa)) {
471 assert(mode != mode_E && "IEEE Extended FP not supported");
472 panic("VFP not supported yet");
474 panic("Softfloat not supported yet");
477 assert(mode_is_data(mode));
478 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
481 static ir_node *gen_Quot(ir_node *node)
483 ir_node *block = be_transform_node(get_nodes_block(node));
484 ir_node *op1 = get_Quot_left(node);
485 ir_node *new_op1 = be_transform_node(op1);
486 ir_node *op2 = get_Quot_right(node);
487 ir_node *new_op2 = be_transform_node(op2);
488 ir_mode *mode = get_irn_mode(node);
489 dbg_info *dbg = get_irn_dbg_info(node);
491 assert(mode != mode_E && "IEEE Extended FP not supported");
493 env_cg->have_fp_insn = 1;
494 if (USE_FPA(env_cg->isa)) {
496 if (is_arm_Mov_i(new_op1))
497 return new_bd_arm_fpaRdf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
498 if (is_arm_Mov_i(new_op2))
499 return new_bd_arm_fpaDvf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
501 return new_bd_arm_fpaDvf(dbg, block, new_op1, new_op2, mode);
502 } else if (USE_VFP(env_cg->isa)) {
503 assert(mode != mode_E && "IEEE Extended FP not supported");
504 panic("VFP not supported yet");
506 panic("Softfloat not supported yet");
510 static ir_node *gen_And(ir_node *node)
512 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
513 new_bd_arm_And_reg, new_bd_arm_And_imm);
516 static ir_node *gen_Or(ir_node *node)
518 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
519 new_bd_arm_Or_reg, new_bd_arm_Or_imm);
522 static ir_node *gen_Eor(ir_node *node)
524 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
525 new_bd_arm_Eor_reg, new_bd_arm_Eor_imm);
528 static ir_node *gen_Sub(ir_node *node)
530 ir_node *block = be_transform_node(get_nodes_block(node));
531 ir_node *op1 = get_Sub_left(node);
532 ir_node *new_op1 = be_transform_node(op1);
533 ir_node *op2 = get_Sub_right(node);
534 ir_node *new_op2 = be_transform_node(op2);
535 ir_mode *mode = get_irn_mode(node);
536 dbg_info *dbgi = get_irn_dbg_info(node);
538 if (mode_is_float(mode)) {
539 env_cg->have_fp_insn = 1;
540 if (USE_FPA(env_cg->isa)) {
542 if (is_arm_Mov_i(new_op1))
543 return new_bd_arm_fpaRsf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1));
544 if (is_arm_Mov_i(new_op2))
545 return new_bd_arm_fpaSuf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2));
547 return new_bd_arm_fpaSuf(dbgi, block, new_op1, new_op2, mode);
548 } else if (USE_VFP(env_cg->isa)) {
549 assert(mode != mode_E && "IEEE Extended FP not supported");
550 panic("VFP not supported yet");
552 panic("Softfloat not supported yet");
555 return gen_int_binop(node, MATCH_SIZE_NEUTRAL,
556 new_bd_arm_Sub_reg, new_bd_arm_Sub_imm);
560 static bool can_use_shift_constant(unsigned int val,
561 arm_shift_modifier_t modifier)
565 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
570 static ir_node *make_shift(ir_node *node, match_flags_t flags,
571 arm_shift_modifier_t shift_modifier)
573 ir_node *block = be_transform_node(get_nodes_block(node));
574 ir_node *op1 = get_binop_left(node);
575 ir_node *op2 = get_binop_right(node);
576 dbg_info *dbgi = get_irn_dbg_info(node);
580 if (flags & MATCH_SIZE_NEUTRAL) {
581 op1 = arm_skip_downconv(op1);
582 op2 = arm_skip_downconv(op2);
585 new_op1 = be_transform_node(op1);
587 tarval *tv = get_Const_tarval(op2);
588 unsigned int val = get_tarval_long(tv);
589 assert(tarval_is_long(tv));
590 if (can_use_shift_constant(val, shift_modifier)) {
591 switch (shift_modifier) {
592 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
593 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
594 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
595 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
596 default: panic("unexpected shift modifier");
598 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
599 shift_modifier, val);
603 new_op2 = be_transform_node(op2);
604 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
608 static ir_node *gen_Shl(ir_node *node)
610 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
613 static ir_node *gen_Shr(ir_node *node)
615 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
618 static ir_node *gen_Shrs(ir_node *node)
620 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
623 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
625 ir_node *block = be_transform_node(get_nodes_block(node));
626 ir_node *new_op1 = be_transform_node(op1);
627 dbg_info *dbgi = get_irn_dbg_info(node);
628 ir_node *new_op2 = be_transform_node(op2);
630 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
634 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
636 ir_node *block = be_transform_node(get_nodes_block(node));
637 ir_node *new_op1 = be_transform_node(op1);
638 dbg_info *dbgi = get_irn_dbg_info(node);
639 ir_node *new_op2 = be_transform_node(op2);
641 /* Note: there is no Rol on arm, we have to use Ror */
642 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
643 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
647 static ir_node *gen_Rotl(ir_node *node)
649 ir_node *rotate = NULL;
650 ir_node *op1 = get_Rotl_left(node);
651 ir_node *op2 = get_Rotl_right(node);
653 /* Firm has only RotL, so we are looking for a right (op2)
654 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
655 that means we can create a RotR. */
658 ir_node *right = get_Add_right(op2);
659 if (is_Const(right)) {
660 tarval *tv = get_Const_tarval(right);
661 ir_mode *mode = get_irn_mode(node);
662 long bits = get_mode_size_bits(mode);
663 ir_node *left = get_Add_left(op2);
665 if (is_Minus(left) &&
666 tarval_is_long(tv) &&
667 get_tarval_long(tv) == bits &&
669 rotate = gen_Ror(node, op1, get_Minus_op(left));
671 } else if (is_Sub(op2)) {
672 ir_node *left = get_Sub_left(op2);
673 if (is_Const(left)) {
674 tarval *tv = get_Const_tarval(left);
675 ir_mode *mode = get_irn_mode(node);
676 long bits = get_mode_size_bits(mode);
677 ir_node *right = get_Sub_right(op2);
679 if (tarval_is_long(tv) &&
680 get_tarval_long(tv) == bits &&
682 rotate = gen_Ror(node, op1, right);
684 } else if (is_Const(op2)) {
685 tarval *tv = get_Const_tarval(op2);
686 ir_mode *mode = get_irn_mode(node);
687 long bits = get_mode_size_bits(mode);
689 if (tarval_is_long(tv) && bits == 32) {
690 ir_node *block = be_transform_node(get_nodes_block(node));
691 ir_node *new_op1 = be_transform_node(op1);
692 dbg_info *dbgi = get_irn_dbg_info(node);
694 bits = (bits - get_tarval_long(tv)) & 31;
695 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
699 if (rotate == NULL) {
700 rotate = gen_Rol(node, op1, op2);
706 static ir_node *gen_Not(ir_node *node)
708 ir_node *block = be_transform_node(get_nodes_block(node));
709 ir_node *op = get_Not_op(node);
710 ir_node *new_op = be_transform_node(op);
711 dbg_info *dbgi = get_irn_dbg_info(node);
713 /* TODO: we could do alot more here with all the Mvn variations */
715 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
718 static ir_node *gen_Abs(ir_node *node)
720 ir_node *block = be_transform_node(get_nodes_block(node));
721 ir_node *op = get_Abs_op(node);
722 ir_node *new_op = be_transform_node(op);
723 dbg_info *dbgi = get_irn_dbg_info(node);
724 ir_mode *mode = get_irn_mode(node);
726 if (mode_is_float(mode)) {
727 env_cg->have_fp_insn = 1;
728 if (USE_FPA(env_cg->isa)) {
729 return new_bd_arm_fpaAbs(dbgi, block, new_op, mode);
730 } else if (USE_VFP(env_cg->isa)) {
731 assert(mode != mode_E && "IEEE Extended FP not supported");
732 panic("VFP not supported yet");
734 panic("Softfloat not supported yet");
737 assert(mode_is_data(mode));
738 return new_bd_arm_Abs(dbgi, block, new_op);
741 static ir_node *gen_Minus(ir_node *node)
743 ir_node *block = be_transform_node(get_nodes_block(node));
744 ir_node *op = get_Minus_op(node);
745 ir_node *new_op = be_transform_node(op);
746 dbg_info *dbgi = get_irn_dbg_info(node);
747 ir_mode *mode = get_irn_mode(node);
749 if (mode_is_float(mode)) {
750 env_cg->have_fp_insn = 1;
751 if (USE_FPA(env_cg->isa)) {
752 return new_bd_arm_fpaMvf(dbgi, block, op, mode);
753 } else if (USE_VFP(env_cg->isa)) {
754 assert(mode != mode_E && "IEEE Extended FP not supported");
755 panic("VFP not supported yet");
757 panic("Softfloat not supported yet");
760 assert(mode_is_data(mode));
761 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
764 static ir_node *gen_Load(ir_node *node)
766 ir_node *block = be_transform_node(get_nodes_block(node));
767 ir_node *ptr = get_Load_ptr(node);
768 ir_node *new_ptr = be_transform_node(ptr);
769 ir_node *mem = get_Load_mem(node);
770 ir_node *new_mem = be_transform_node(mem);
771 ir_mode *mode = get_Load_mode(node);
772 dbg_info *dbgi = get_irn_dbg_info(node);
773 ir_node *new_load = NULL;
775 if (mode_is_float(mode)) {
776 env_cg->have_fp_insn = 1;
777 if (USE_FPA(env_cg->isa)) {
778 new_load = new_bd_arm_fpaLdf(dbgi, block, new_ptr, new_mem, mode);
779 } else if (USE_VFP(env_cg->isa)) {
780 assert(mode != mode_E && "IEEE Extended FP not supported");
781 panic("VFP not supported yet");
783 panic("Softfloat not supported yet");
786 assert(mode_is_data(mode) && "unsupported mode for Load");
788 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
790 set_irn_pinned(new_load, get_irn_pinned(node));
792 /* check for special case: the loaded value might not be used */
793 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
794 /* add a result proj and a Keep to produce a pseudo use */
795 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
796 be_new_Keep(block, 1, &proj);
802 static ir_node *gen_Store(ir_node *node)
804 ir_node *block = be_transform_node(get_nodes_block(node));
805 ir_node *ptr = get_Store_ptr(node);
806 ir_node *new_ptr = be_transform_node(ptr);
807 ir_node *mem = get_Store_mem(node);
808 ir_node *new_mem = be_transform_node(mem);
809 ir_node *val = get_Store_value(node);
810 ir_node *new_val = be_transform_node(val);
811 ir_mode *mode = get_irn_mode(val);
812 dbg_info *dbgi = get_irn_dbg_info(node);
813 ir_node *new_store = NULL;
815 if (mode_is_float(mode)) {
816 env_cg->have_fp_insn = 1;
817 if (USE_FPA(env_cg->isa)) {
818 new_store = new_bd_arm_fpaStf(dbgi, block, new_ptr, new_val,
820 } else if (USE_VFP(env_cg->isa)) {
821 assert(mode != mode_E && "IEEE Extended FP not supported");
822 panic("VFP not supported yet");
824 panic("Softfloat not supported yet");
827 assert(mode_is_data(mode) && "unsupported mode for Store");
828 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
831 set_irn_pinned(new_store, get_irn_pinned(node));
835 static ir_node *gen_Jmp(ir_node *node)
837 ir_node *block = get_nodes_block(node);
838 ir_node *new_block = be_transform_node(block);
839 dbg_info *dbgi = get_irn_dbg_info(node);
841 return new_bd_arm_Jmp(dbgi, new_block);
844 static ir_node *gen_SwitchJmp(ir_node *node)
846 ir_node *block = be_transform_node(get_nodes_block(node));
847 ir_node *selector = get_Cond_selector(node);
848 dbg_info *dbgi = get_irn_dbg_info(node);
849 ir_node *new_op = be_transform_node(selector);
850 ir_node *const_graph;
854 const ir_edge_t *edge;
861 foreach_out_edge(node, edge) {
862 proj = get_edge_src_irn(edge);
863 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
865 pn = get_Proj_proj(proj);
867 min = pn<min ? pn : min;
868 max = pn>max ? pn : max;
871 n_projs = max - translation + 1;
873 foreach_out_edge(node, edge) {
874 proj = get_edge_src_irn(edge);
875 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
877 pn = get_Proj_proj(proj) - translation;
878 set_Proj_proj(proj, pn);
881 const_graph = create_const_graph_value(dbgi, block, translation);
882 sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
883 return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
886 static ir_node *gen_Cmp(ir_node *node)
888 ir_node *block = be_transform_node(get_nodes_block(node));
889 ir_node *op1 = get_Cmp_left(node);
890 ir_node *op2 = get_Cmp_right(node);
891 ir_mode *cmp_mode = get_irn_mode(op1);
892 dbg_info *dbgi = get_irn_dbg_info(node);
897 if (mode_is_float(cmp_mode)) {
898 /* TODO: this is broken... */
899 new_op1 = be_transform_node(op1);
900 new_op2 = be_transform_node(op2);
902 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
904 panic("FloatCmp NIY");
906 ir_node *new_op2 = be_transform_node(op2);
907 /* floating point compare */
908 pn_Cmp pnc = get_Proj_proj(selector);
910 if (pnc & pn_Cmp_Uo) {
911 /* check for unordered, need cmf */
912 return new_bd_arm_fpaCmfBra(dbgi, block, new_op1, new_op2, pnc);
914 /* Hmm: use need cmfe */
915 return new_bd_arm_fpaCmfeBra(dbgi, block, new_op1, new_op2, pnc);
919 assert(get_irn_mode(op2) == cmp_mode);
920 is_unsigned = !mode_is_signed(cmp_mode);
922 /* compare with 0 can be done with Tst */
923 if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) {
924 new_op1 = be_transform_node(op1);
925 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
926 return new_bd_arm_Tst_reg(dbgi, block, new_op1, new_op1, false,
929 if (is_Const(op1) && tarval_is_null(get_Const_tarval(op1))) {
930 new_op2 = be_transform_node(op2);
931 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
932 return new_bd_arm_Tst_reg(dbgi, block, new_op2, new_op2, true,
936 /* integer compare, TODO: use shifer_op in all its combinations */
937 new_op1 = be_transform_node(op1);
938 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
939 new_op2 = be_transform_node(op2);
940 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
941 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
945 static ir_node *gen_Cond(ir_node *node)
947 ir_node *selector = get_Cond_selector(node);
948 ir_mode *mode = get_irn_mode(selector);
953 if (mode != mode_b) {
954 return gen_SwitchJmp(node);
956 assert(is_Proj(selector));
958 block = be_transform_node(get_nodes_block(node));
959 dbgi = get_irn_dbg_info(node);
960 flag_node = be_transform_node(get_Proj_pred(selector));
962 return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector));
965 static tarval *fpa_imm[3][fpa_max];
969 * Check, if a floating point tarval is an fpa immediate, i.e.
970 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
972 static int is_fpa_immediate(tarval *tv)
974 ir_mode *mode = get_tarval_mode(tv);
977 switch (get_mode_size_bits(mode)) {
988 if (tarval_is_negative(tv)) {
993 for (j = 0; j < fpa_max; ++j) {
994 if (tv == fpa_imm[i][j])
1001 static ir_node *gen_Const(ir_node *node)
1003 ir_node *block = be_transform_node(get_nodes_block(node));
1004 ir_mode *mode = get_irn_mode(node);
1005 dbg_info *dbg = get_irn_dbg_info(node);
1007 if (mode_is_float(mode)) {
1008 env_cg->have_fp_insn = 1;
1009 if (USE_FPA(env_cg->isa)) {
1010 tarval *tv = get_Const_tarval(node);
1012 int imm = is_fpa_immediate(tv);
1014 if (imm != fpa_max) {
1016 node = new_bd_arm_fpaMvf_i(dbg, block, mode, imm);
1018 node = new_bd_arm_fpaMnf_i(dbg, block, mode, -imm);
1023 node = new_bd_arm_fpaConst(dbg, block, tv);
1025 be_dep_on_frame(node);
1027 } else if (USE_VFP(env_cg->isa)) {
1028 assert(mode != mode_E && "IEEE Extended FP not supported");
1029 panic("VFP not supported yet");
1031 panic("Softfloat not supported yet");
1034 return create_const_graph(node, block);
1037 static ir_node *gen_SymConst(ir_node *node)
1039 ir_node *block = be_transform_node(get_nodes_block(node));
1040 ir_entity *entity = get_SymConst_entity(node);
1041 dbg_info *dbgi = get_irn_dbg_info(node);
1044 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
1045 be_dep_on_frame(new_node);
1049 static ir_node *gen_CopyB(ir_node *node)
1051 ir_node *block = be_transform_node(get_nodes_block(node));
1052 ir_node *src = get_CopyB_src(node);
1053 ir_node *new_src = be_transform_node(src);
1054 ir_node *dst = get_CopyB_dst(node);
1055 ir_node *new_dst = be_transform_node(dst);
1056 ir_node *mem = get_CopyB_mem(node);
1057 ir_node *new_mem = be_transform_node(mem);
1058 dbg_info *dbg = get_irn_dbg_info(node);
1059 int size = get_type_size_bytes(get_CopyB_type(node));
1063 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
1064 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
1066 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1067 new_bd_arm_EmptyReg(dbg, block),
1068 new_bd_arm_EmptyReg(dbg, block),
1069 new_bd_arm_EmptyReg(dbg, block),
1073 static ir_node *gen_Proj_Load(ir_node *node)
1075 ir_node *load = get_Proj_pred(node);
1076 ir_node *new_load = be_transform_node(load);
1077 dbg_info *dbgi = get_irn_dbg_info(node);
1078 long proj = get_Proj_proj(node);
1080 /* renumber the proj */
1081 switch (get_arm_irn_opcode(new_load)) {
1083 /* handle all gp loads equal: they have the same proj numbers. */
1084 if (proj == pn_Load_res) {
1085 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1086 } else if (proj == pn_Load_M) {
1087 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1090 case iro_arm_fpaLdf:
1091 if (proj == pn_Load_res) {
1092 ir_mode *mode = get_Load_mode(load);
1093 return new_rd_Proj(dbgi, new_load, mode, pn_arm_fpaLdf_res);
1094 } else if (proj == pn_Load_M) {
1095 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_fpaLdf_M);
1101 panic("Unsupported Proj from Load");
1104 static ir_node *gen_Proj_CopyB(ir_node *node)
1106 ir_node *pred = get_Proj_pred(node);
1107 ir_node *new_pred = be_transform_node(pred);
1108 dbg_info *dbgi = get_irn_dbg_info(node);
1109 long proj = get_Proj_proj(node);
1113 if (is_arm_CopyB(new_pred)) {
1114 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1120 panic("Unsupported Proj from CopyB");
1123 static ir_node *gen_Proj_Quot(ir_node *node)
1125 ir_node *pred = get_Proj_pred(node);
1126 ir_node *new_pred = be_transform_node(pred);
1127 dbg_info *dbgi = get_irn_dbg_info(node);
1128 ir_mode *mode = get_irn_mode(node);
1129 long proj = get_Proj_proj(node);
1133 if (is_arm_fpaDvf(new_pred)) {
1134 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaDvf_M);
1135 } else if (is_arm_fpaRdf(new_pred)) {
1136 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaRdf_M);
1137 } else if (is_arm_fpaFdv(new_pred)) {
1138 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaFdv_M);
1139 } else if (is_arm_fpaFrd(new_pred)) {
1140 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaFrd_M);
1144 if (is_arm_fpaDvf(new_pred)) {
1145 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaDvf_res);
1146 } else if (is_arm_fpaRdf(new_pred)) {
1147 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaRdf_res);
1148 } else if (is_arm_fpaFdv(new_pred)) {
1149 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaFdv_res);
1150 } else if (is_arm_fpaFrd(new_pred)) {
1151 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaFrd_res);
1157 panic("Unsupported Proj from Quot");
1161 * Transform the Projs from a Cmp.
1163 static ir_node *gen_Proj_Cmp(ir_node *node)
1166 /* we should only be here in case of a Mux node */
1170 static ir_node *gen_Proj_Start(ir_node *node)
1172 ir_node *block = get_nodes_block(node);
1173 ir_node *new_block = be_transform_node(block);
1174 ir_node *barrier = be_transform_node(get_Proj_pred(node));
1175 long proj = get_Proj_proj(node);
1177 switch ((pn_Start) proj) {
1178 case pn_Start_X_initial_exec:
1179 /* we exchange the ProjX with a jump */
1180 return new_bd_arm_Jmp(NULL, new_block);
1183 return new_r_Proj(barrier, mode_M, 0);
1185 case pn_Start_T_args:
1189 case pn_Start_P_frame_base:
1190 return be_prolog_get_reg_value(abihelper, sp_reg);
1192 case pn_Start_P_tls:
1193 return new_bd_arm_LdTls(NULL, new_block);
1198 panic("unexpected start proj: %ld\n", proj);
1201 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1203 long pn = get_Proj_proj(node);
1204 const reg_or_stackslot_t *param;
1206 /* Proj->Proj->Start must be a method argument */
1207 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1209 param = &cconv->parameters[pn];
1211 if (param->reg0 != NULL) {
1212 /* argument transmitted in register */
1213 return be_prolog_get_reg_value(abihelper, param->reg0);
1215 /* argument transmitted on stack */
1216 ir_graph *irg = get_irn_irg(node);
1217 ir_node *block = get_nodes_block(node);
1218 ir_node *new_block = be_transform_node(block);
1219 ir_node *fp = get_irg_frame(irg);
1220 ir_node *mem = be_prolog_get_memory(abihelper);
1221 ir_mode *mode = get_type_mode(param->type);
1222 ir_node *load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1223 param->entity, 0, 0, true);
1224 ir_node *value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1225 set_irn_pinned(load, op_pin_state_floats);
1232 * Finds number of output value of a mode_T node which is constrained to
1233 * a single specific register.
1235 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1237 int n_outs = arch_irn_get_n_outs(node);
1240 for (o = 0; o < n_outs; ++o) {
1241 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1242 if (req == reg->single_req)
1248 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1250 long pn = get_Proj_proj(node);
1251 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1252 ir_node *new_call = be_transform_node(call);
1253 ir_type *function_type = get_Call_type(call);
1254 calling_convention_t *cconv = decide_calling_convention(function_type);
1255 const reg_or_stackslot_t *res = &cconv->results[pn];
1259 /* TODO 64bit modes */
1260 assert(res->reg0 != NULL && res->reg1 == NULL);
1261 regn = find_out_for_reg(new_call, res->reg0);
1263 panic("Internal error in calling convention for return %+F", node);
1265 mode = res->reg0->reg_class->mode;
1267 free_calling_convention(cconv);
1269 return new_r_Proj(new_call, mode, regn);
1272 static ir_node *gen_Proj_Call(ir_node *node)
1274 long pn = get_Proj_proj(node);
1275 ir_node *call = get_Proj_pred(node);
1276 ir_node *new_call = be_transform_node(call);
1278 switch ((pn_Call) pn) {
1280 return new_r_Proj(new_call, mode_M, 0);
1281 case pn_Call_X_regular:
1282 case pn_Call_X_except:
1283 case pn_Call_T_result:
1284 case pn_Call_P_value_res_base:
1288 panic("Unexpected Call proj %ld\n", pn);
1292 * Transform a Proj node.
1294 static ir_node *gen_Proj(ir_node *node)
1296 ir_node *pred = get_Proj_pred(node);
1297 long proj = get_Proj_proj(node);
1299 switch (get_irn_opcode(pred)) {
1301 if (proj == pn_Store_M) {
1302 return be_transform_node(pred);
1304 panic("Unsupported Proj from Store");
1307 return gen_Proj_Load(node);
1309 return gen_Proj_Call(node);
1311 return gen_Proj_CopyB(node);
1313 return gen_Proj_Quot(node);
1315 return gen_Proj_Cmp(node);
1317 return gen_Proj_Start(node);
1320 return be_duplicate_node(node);
1322 ir_node *pred_pred = get_Proj_pred(pred);
1323 if (is_Call(pred_pred)) {
1324 return gen_Proj_Proj_Call(node);
1325 } else if (is_Start(pred_pred)) {
1326 return gen_Proj_Proj_Start(node);
1331 panic("code selection didn't expect Proj after %+F\n", pred);
1335 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1337 static inline ir_node *create_const(ir_node **place,
1338 create_const_node_func func,
1339 const arch_register_t* reg)
1341 ir_node *block, *res;
1346 block = get_irg_start_block(env_cg->irg);
1347 res = func(NULL, block);
1348 arch_set_irn_register(res, reg);
1353 static ir_node *gen_Unknown(ir_node *node)
1355 ir_node *block = get_nodes_block(node);
1356 ir_node *new_block = be_transform_node(block);
1357 dbg_info *dbgi = get_irn_dbg_info(node);
1359 /* just produce a 0 */
1360 ir_mode *mode = get_irn_mode(node);
1361 if (mode_is_float(mode)) {
1362 tarval *tv = get_mode_null(mode);
1363 ir_node *node = new_bd_arm_fpaConst(dbgi, new_block, tv);
1364 be_dep_on_frame(node);
1366 } else if (mode_needs_gp_reg(mode)) {
1367 return create_const_graph_value(dbgi, new_block, 0);
1370 panic("Unexpected Unknown mode");
1374 * Produces the type which sits between the stack args and the locals on the
1375 * stack. It will contain the return address and space to store the old base
1377 * @return The Firm type modeling the ABI between type.
1379 static ir_type *arm_get_between_type(void)
1381 static ir_type *between_type = NULL;
1383 if (between_type == NULL) {
1384 between_type = new_type_class(new_id_from_str("arm_between_type"));
1385 set_type_size_bytes(between_type, 0);
1388 return between_type;
1391 static void create_stacklayout(ir_graph *irg)
1393 ir_entity *entity = get_irg_entity(irg);
1394 ir_type *function_type = get_entity_type(entity);
1395 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1400 /* calling conventions must be decided by now */
1401 assert(cconv != NULL);
1403 /* construct argument type */
1404 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1405 n_params = get_method_n_params(function_type);
1406 for (p = 0; p < n_params; ++p) {
1407 reg_or_stackslot_t *param = &cconv->parameters[p];
1411 if (param->type == NULL)
1414 snprintf(buf, sizeof(buf), "param_%d", p);
1415 id = new_id_from_str(buf);
1416 param->entity = new_entity(arg_type, id, param->type);
1417 set_entity_offset(param->entity, param->offset);
1420 /* TODO: what about external functions? we don't know most of the stack
1421 * layout for them. And probably don't need all of this... */
1422 memset(layout, 0, sizeof(*layout));
1424 layout->frame_type = get_irg_frame_type(irg);
1425 layout->between_type = arm_get_between_type();
1426 layout->arg_type = arg_type;
1427 layout->param_map = NULL; /* TODO */
1428 layout->initial_offset = 0;
1429 layout->initial_bias = 0;
1430 layout->stack_dir = -1;
1432 assert(N_FRAME_TYPES == 3);
1433 layout->order[0] = layout->frame_type;
1434 layout->order[1] = layout->between_type;
1435 layout->order[2] = layout->arg_type;
1439 * transform the start node to the prolog code + initial barrier
1441 static ir_node *gen_Start(ir_node *node)
1443 ir_graph *irg = get_irn_irg(node);
1444 ir_entity *entity = get_irg_entity(irg);
1445 ir_type *function_type = get_entity_type(entity);
1446 ir_node *block = get_nodes_block(node);
1447 ir_node *new_block = be_transform_node(block);
1448 dbg_info *dbgi = get_irn_dbg_info(node);
1455 /* stackpointer is important at function prolog */
1456 be_prolog_add_reg(abihelper, sp_reg,
1457 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1458 /* function parameters in registers */
1459 for (i = 0; i < get_method_n_params(function_type); ++i) {
1460 const reg_or_stackslot_t *param = &cconv->parameters[i];
1461 if (param->reg0 != NULL)
1462 be_prolog_add_reg(abihelper, param->reg0, 0);
1463 if (param->reg1 != NULL)
1464 be_prolog_add_reg(abihelper, param->reg1, 0);
1466 /* announce that we need the values of the callee save regs */
1467 for (i = 0; i < (int) (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
1468 be_prolog_add_reg(abihelper, callee_saves[i], 0);
1471 start = be_prolog_create_start(abihelper, dbgi, new_block);
1472 sp = be_prolog_get_reg_value(abihelper, sp_reg);
1473 incsp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
1474 be_prolog_set_reg_value(abihelper, sp_reg, incsp);
1475 barrier = be_prolog_create_barrier(abihelper, new_block);
1480 static ir_node *get_stack_pointer_for(ir_node *node)
1482 /* get predecessor in stack_order list */
1483 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1484 ir_node *stack_pred_transformed;
1487 if (stack_pred == NULL) {
1488 /* first stack user in the current block. We can simply use the
1489 * initial sp_proj for it */
1490 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1494 stack_pred_transformed = be_transform_node(stack_pred);
1495 stack = pmap_get(node_to_stack, stack_pred);
1496 if (stack == NULL) {
1497 return get_stack_pointer_for(stack_pred);
1504 * transform a Return node into epilogue code + return statement
1506 static ir_node *gen_Return(ir_node *node)
1508 ir_node *block = get_nodes_block(node);
1509 ir_node *new_block = be_transform_node(block);
1510 dbg_info *dbgi = get_irn_dbg_info(node);
1511 ir_node *mem = get_Return_mem(node);
1512 ir_node *new_mem = be_transform_node(mem);
1513 int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
1514 ir_node *sp_proj = get_stack_pointer_for(node);
1519 const arch_register_t *const result_regs[] = {
1520 &arm_gp_regs[REG_R0],
1521 &arm_gp_regs[REG_R1]
1524 be_epilog_begin(abihelper);
1525 be_epilog_set_memory(abihelper, new_mem);
1526 /* connect stack pointer with initial stack pointer. fix_stack phase
1527 will later serialize all stack pointer adjusting nodes */
1528 be_epilog_add_reg(abihelper, sp_reg,
1529 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1533 n_res = get_Return_n_ress(node);
1534 if (n_res > (int) (sizeof(result_regs)/sizeof(result_regs[0]))) {
1535 panic("Too many return values for arm backend (%+F)", node);
1537 for (i = 0; i < n_res; ++i) {
1538 ir_node *res_value = get_Return_res(node, i);
1539 ir_node *new_res_value = be_transform_node(res_value);
1540 const arch_register_t *reg = result_regs[i];
1541 be_epilog_add_reg(abihelper, reg, 0, new_res_value);
1544 /* connect callee saves with their values at the function begin */
1545 for (i = 0; i < n_callee_saves; ++i) {
1546 const arch_register_t *reg = callee_saves[i];
1547 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1548 be_epilog_add_reg(abihelper, reg, 0, value);
1551 /* create the barrier before the epilog code */
1552 be_epilog_create_barrier(abihelper, new_block);
1554 /* epilog code: an incsp */
1555 sp_proj = be_epilog_get_reg_value(abihelper, sp_reg);
1556 incsp = be_new_IncSP(sp_reg, new_block, sp_proj,
1557 BE_STACK_FRAME_SIZE_SHRINK, 0);
1558 be_epilog_set_reg_value(abihelper, sp_reg, incsp);
1560 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1565 static ir_node *gen_Call(ir_node *node)
1567 ir_graph *irg = get_irn_irg(node);
1568 ir_node *callee = get_Call_ptr(node);
1569 ir_node *block = get_nodes_block(node);
1570 ir_node *new_block = be_transform_node(block);
1571 ir_node *mem = get_Call_mem(node);
1572 ir_node *new_mem = be_transform_node(mem);
1573 dbg_info *dbgi = get_irn_dbg_info(node);
1574 ir_type *type = get_Call_type(node);
1575 calling_convention_t *cconv = decide_calling_convention(type);
1576 int n_params = get_Call_n_params(node);
1577 int n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
1578 /* max inputs: memory, callee, register arguments */
1579 int max_inputs = 2 + n_param_regs;
1580 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1581 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1582 struct obstack *obst = be_get_be_obst(irg);
1583 const arch_register_req_t **in_req
1584 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1588 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1589 ir_entity *entity = NULL;
1590 ir_node *incsp = NULL;
1597 assert(n_params == get_method_n_params(type));
1599 /* construct arguments */
1602 in_req[in_arity] = arch_no_register_req;
1606 for (p = 0; p < n_params; ++p) {
1607 ir_node *value = get_Call_param(node, p);
1608 ir_node *new_value = be_transform_node(value);
1609 const reg_or_stackslot_t *param = &cconv->parameters[p];
1610 const arch_register_t *reg = param->reg0;
1612 /* double not implemented yet */
1613 assert(get_mode_size_bits(get_irn_mode(value)) <= 32);
1614 assert(param->reg1 == NULL);
1617 in[in_arity] = new_value;
1618 if (reg == &arm_gp_regs[REG_LR]) {
1619 in_req[in_arity] = be_create_reg_req(obst,
1620 reg, arch_register_req_type_ignore);
1622 in_req[in_arity] = reg->single_req;
1628 if (incsp == NULL) {
1629 ir_node *new_frame = get_stack_pointer_for(node);
1630 incsp = be_new_IncSP(sp_reg, new_block, new_frame, cconv->param_stack_size, 1);
1632 mode = get_irn_mode(value);
1633 str = new_bd_arm_Str(dbgi, new_block, incsp, value, new_mem, mode,
1634 NULL, 0, param->offset, true);
1636 sync_ins[sync_arity++] = str;
1639 assert(in_arity <= max_inputs);
1641 /* construct memory input */
1642 if (sync_arity == 0) {
1643 in[mem_pos] = new_mem;
1644 } else if (sync_arity == 1) {
1645 in[mem_pos] = sync_ins[0];
1647 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1650 /* TODO: use a generic symconst matcher here */
1651 if (is_SymConst(callee)) {
1652 entity = get_SymConst_entity(callee);
1654 /* TODO: finish load matcher here */
1657 if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) {
1658 ir_node *load = get_Proj_pred(callee);
1659 ir_node *ptr = get_Load_ptr(load);
1660 ir_node *new_ptr = be_transform_node(ptr);
1661 ir_node *mem = get_Load_mem(load);
1662 ir_node *new_mem = be_transform_node(mem);
1663 ir_mode *mode = get_Load_mode(node);
1667 in[in_arity] = be_transform_node(callee);
1668 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1677 out_arity = 1 + n_caller_saves;
1679 if (entity != NULL) {
1680 /* TODO: use a generic symconst matcher here
1681 * so we can also handle entity+offset, etc. */
1682 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1685 * - use a proper shifter_operand matcher
1686 * - we could also use LinkLdrPC
1688 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1692 if (incsp != NULL) {
1693 /* IncSP to destroy the call stackframe */
1694 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
1696 /* if we are the last IncSP producer in a block then we have to keep
1698 * Note: This here keeps all producers which is more than necessary */
1699 add_irn_dep(incsp, res);
1702 pmap_insert(node_to_stack, node, incsp);
1705 set_arm_in_req_all(res, in_req);
1707 /* create output register reqs */
1708 arch_set_out_register_req(res, 0, arch_no_register_req);
1709 for (o = 1; o < n_caller_saves + 1; ++o) {
1710 const arch_register_t *reg = caller_saves[o-1];
1711 arch_set_out_register_req(res, o, reg->single_req);
1714 /* copy pinned attribute */
1715 set_irn_pinned(res, get_irn_pinned(node));
1717 free_calling_convention(cconv);
1721 static ir_node *gen_Sel(ir_node *node)
1723 dbg_info *dbgi = get_irn_dbg_info(node);
1724 ir_node *block = get_nodes_block(node);
1725 ir_node *new_block = be_transform_node(block);
1726 ir_node *ptr = get_Sel_ptr(node);
1727 ir_node *new_ptr = be_transform_node(ptr);
1728 ir_entity *entity = get_Sel_entity(node);
1730 /* must be the frame pointer all other sels must have been lowered
1732 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1733 /* we should not have value types from parameters anymore - they should be
1735 assert(get_entity_owner(entity) !=
1736 get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
1738 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1742 * Change some phi modes
1744 static ir_node *gen_Phi(ir_node *node)
1746 const arch_register_req_t *req;
1747 ir_node *block = be_transform_node(get_nodes_block(node));
1748 ir_graph *irg = current_ir_graph;
1749 dbg_info *dbgi = get_irn_dbg_info(node);
1750 ir_mode *mode = get_irn_mode(node);
1753 if (mode_needs_gp_reg(mode)) {
1754 /* we shouldn't have any 64bit stuff around anymore */
1755 assert(get_mode_size_bits(mode) <= 32);
1756 /* all integer operations are on 32bit registers now */
1758 req = arm_reg_classes[CLASS_arm_gp].class_req;
1760 req = arch_no_register_req;
1763 /* phi nodes allow loops, so we use the old arguments for now
1764 * and fix this later */
1765 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
1766 get_irn_in(node) + 1);
1767 copy_node_attr(irg, node, phi);
1768 be_duplicate_deps(node, phi);
1770 arch_set_out_register_req(phi, 0, req);
1772 be_enqueue_preds(node);
1779 * Enters all transform functions into the generic pointer
1781 static void arm_register_transformers(void)
1783 be_start_transform_setup();
1785 be_set_transform_function(op_Abs, gen_Abs);
1786 be_set_transform_function(op_Add, gen_Add);
1787 be_set_transform_function(op_And, gen_And);
1788 be_set_transform_function(op_Call, gen_Call);
1789 be_set_transform_function(op_Cmp, gen_Cmp);
1790 be_set_transform_function(op_Cond, gen_Cond);
1791 be_set_transform_function(op_Const, gen_Const);
1792 be_set_transform_function(op_Conv, gen_Conv);
1793 be_set_transform_function(op_CopyB, gen_CopyB);
1794 be_set_transform_function(op_Eor, gen_Eor);
1795 be_set_transform_function(op_Jmp, gen_Jmp);
1796 be_set_transform_function(op_Load, gen_Load);
1797 be_set_transform_function(op_Minus, gen_Minus);
1798 be_set_transform_function(op_Mul, gen_Mul);
1799 be_set_transform_function(op_Not, gen_Not);
1800 be_set_transform_function(op_Or, gen_Or);
1801 be_set_transform_function(op_Phi, gen_Phi);
1802 be_set_transform_function(op_Proj, gen_Proj);
1803 be_set_transform_function(op_Quot, gen_Quot);
1804 be_set_transform_function(op_Return, gen_Return);
1805 be_set_transform_function(op_Rotl, gen_Rotl);
1806 be_set_transform_function(op_Sel, gen_Sel);
1807 be_set_transform_function(op_Shl, gen_Shl);
1808 be_set_transform_function(op_Shr, gen_Shr);
1809 be_set_transform_function(op_Shrs, gen_Shrs);
1810 be_set_transform_function(op_Start, gen_Start);
1811 be_set_transform_function(op_Store, gen_Store);
1812 be_set_transform_function(op_Sub, gen_Sub);
1813 be_set_transform_function(op_SymConst, gen_SymConst);
1814 be_set_transform_function(op_Unknown, gen_Unknown);
1818 * Initialize fpa Immediate support.
1820 static void arm_init_fpa_immediate(void)
1822 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
1823 fpa_imm[0][fpa_null] = get_mode_null(mode_F);
1824 fpa_imm[0][fpa_one] = get_mode_one(mode_F);
1825 fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
1826 fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
1827 fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
1828 fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
1829 fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
1830 fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
1832 fpa_imm[1][fpa_null] = get_mode_null(mode_D);
1833 fpa_imm[1][fpa_one] = get_mode_one(mode_D);
1834 fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
1835 fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
1836 fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
1837 fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
1838 fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
1839 fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
1841 fpa_imm[2][fpa_null] = get_mode_null(mode_E);
1842 fpa_imm[2][fpa_one] = get_mode_one(mode_E);
1843 fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
1844 fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
1845 fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
1846 fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
1847 fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
1848 fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
1852 * Transform a Firm graph into an ARM graph.
1854 void arm_transform_graph(arm_code_gen_t *cg)
1856 static int imm_initialized = 0;
1857 ir_graph *irg = cg->irg;
1858 ir_entity *entity = get_irg_entity(irg);
1859 ir_type *frame_type;
1863 if (! imm_initialized) {
1864 arm_init_fpa_immediate();
1865 imm_initialized = 1;
1867 arm_register_transformers();
1870 node_to_stack = pmap_create();
1872 assert(abihelper == NULL);
1873 abihelper = be_abihelper_prepare(irg);
1874 be_collect_stacknodes(abihelper);
1875 assert(cconv == NULL);
1876 cconv = decide_calling_convention(get_entity_type(entity));
1877 create_stacklayout(irg);
1879 be_transform_graph(cg->irg, NULL);
1881 be_abihelper_finish(abihelper);
1884 free_calling_convention(cconv);
1887 frame_type = get_irg_frame_type(irg);
1888 if (get_type_state(frame_type) == layout_undefined) {
1889 default_layout_compound_type(frame_type);
1892 pmap_destroy(node_to_stack);
1893 node_to_stack = NULL;
1895 be_add_missing_keeps(irg);
1898 void arm_init_transform(void)
1900 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");